JP2009206144A - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】 トランジスタのL長と同じ距離かそれより短い距離の深さのトレンチを有すること、さらにトレンチの底部に埋め込み層を用いることで、ソース高濃度拡散層下端あるいはドレイン高濃度拡散層下端からトレンチ底面までの実効的なチャネル長をトレンチ上面のゲート長よりも短くすることができ、駆動能力を向上させることができる。
【選択図】 図1
Description
(1)第1導電型半導体基板と、前記第1導電型半導体基板上の所定の領域に形成された第2導電型埋め込み層と、前記第2導電型埋め込み層および前記第1導電型半導体基板の上に形成された第1導電型エピタキシャル成長層と、前記第1導電型エピタキシャル成長層に形成された、形成されるトランジスタのゲート幅方向に並んで配置された、その底部は前記第2導電型埋め込み層に達するトレンチと、ゲート絶縁膜を介して前記トレンチの内部及び上面と前記トレンチに隣接する第1導電型エピタキシャル成長層の表面部分に形成されたゲート電極と、前記ゲート電極の一方の側に形成された第2導電型のソース高濃度拡散層と、前記ゲート電極の他方の側に形成された第2導電型のドレイン高濃度拡散層と、を有する半導体装置とした。
(2)第1導電型半導体基板の所定の領域に第2導電型埋め込み層を形成する工程と、前記第2導電型埋め込み層および前記第1導電型半導体基板の上に第1導電型エピタキシャル成長層を形成する工程と、前記第1導電型エピタキシャル成長層に、形成されるトランジスタのゲート幅方向に並んで、その底部が前記第2導電型埋め込み層に達するようにトレンチを形成する工程と、ゲート絶縁膜を形成する工程と、前記ゲート絶縁膜を介して前記トレンチの内部及び上面と前記トレンチに隣接する第1導電型エピタキシャル成長層の表面部分にゲート電極を形成する工程と、前記ゲート電極の一方の側に第2導電型のソース高濃度拡散層、他方の側に第2導電型のドレイン高濃度拡散層とを形成する工程と、を含む半導体装置の製造方法とした。
2 第2導電型埋め込み層
3 第1導電型エピタキシャル成長層
4、12 LOCOS酸化膜
5 マスク
6、13 トレンチ
7、14 ゲート絶縁膜
8、15 ゲート電極
9、16 ソース高濃度拡散層
10、17 ドレイン高濃度拡散層
F 第2導電型埋め込み層の側面の端部
G トレンチ側面の端部
L、L' ゲート長
Claims (7)
- 第1導電型半導体基板と、
前記第1導電型半導体基板上の所定の領域に形成された第2導電型埋め込み層と、
前記第2導電型埋め込み層および前記第1導電型半導体基板の上に形成された第1導電型エピタキシャル成長層と、
前記第1導電型エピタキシャル成長層に形成された、形成されるトランジスタのゲート幅方向に並んで配置された、その底部は前記第2導電型埋め込み層に達するトレンチと、
ゲート絶縁膜を介して前記トレンチの内部及び上面と前記トレンチに隣接する第1導電型エピタキシャル成長層の表面部分に形成されたゲート電極と、
前記ゲート電極の一方の側に形成された第2導電型のソース高濃度拡散層と、
前記ゲート電極の他方の側に形成された第2導電型のドレイン高濃度拡散層と、
を有する半導体装置。 - 前記トレンチの深さは形成されるトランジスタのゲート長より短いか同じである請求項1に記載の半導体装置。
- 前記トレンチの位置は、前記第2導電型埋め込み層の側面の端部より内側である請求項2に記載の半導体装置。
- 前記トレンチの位置は、前記第2導電型埋め込み層の側面の端部と同一面である請求項2記載の半導体装置。
- 前記トレンチの位置は、前記第2導電型ソース高濃度拡散層下端あるいはドレイン高濃度拡散層下端から前記第2導電型埋め込み層までの距離がトランジスタのゲート長よりも短い場合、前記第2導電型埋め込み層の側面の端部より外側に形成される請求項2に記載の半導体装置の製造方法
- 前記第2導電型埋め込み層の濃度は1×1018atoms/cm3から1×1021atoms/cm3程度である請求項1ないし5のいずれか1項に記載の半導体装置。
- 第1導電型半導体基板の所定の領域に第2導電型埋め込み層を形成する工程と、
前記第2導電型埋め込み層および前記第1導電型半導体基板の上に第1導電型エピタキシャル成長層を形成する工程と、
前記第1導電型エピタキシャル成長層に、形成されるトランジスタのゲート幅方向に並んで、その底部が前記第2導電型埋め込み層に達するようにトレンチを形成する工程と、
ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜を介して前記トレンチの内部及び上面と前記トレンチに隣接する第1導電型エピタキシャル成長層の表面部分にゲート電極を形成する工程と、
前記ゲート電極の一方の側に第2導電型のソース高濃度拡散層、他方の側に第2導電型のドレイン高濃度拡散層とを形成する工程と、
を含む半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008044392A JP5159365B2 (ja) | 2008-02-26 | 2008-02-26 | 半導体装置およびその製造方法 |
TW098105461A TWI438899B (zh) | 2008-02-26 | 2009-02-20 | 半導體裝置及其製造方法 |
KR1020090014333A KR101543792B1 (ko) | 2008-02-26 | 2009-02-20 | 반도체 장치 및 그 제조 방법 |
US12/380,144 US8053820B2 (en) | 2008-02-26 | 2009-02-24 | Semiconductor device and method of manufacturing the same |
CN2009100081332A CN101521222B (zh) | 2008-02-26 | 2009-02-26 | 半导体器件及其制造方法 |
US13/200,252 US8598026B2 (en) | 2008-02-26 | 2011-09-21 | Semiconductor device and method of manufacturing the same |
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JP2008044392A JP5159365B2 (ja) | 2008-02-26 | 2008-02-26 | 半導体装置およびその製造方法 |
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JP2009206144A true JP2009206144A (ja) | 2009-09-10 |
JP5159365B2 JP5159365B2 (ja) | 2013-03-06 |
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US (2) | US8053820B2 (ja) |
JP (1) | JP5159365B2 (ja) |
KR (1) | KR101543792B1 (ja) |
CN (1) | CN101521222B (ja) |
TW (1) | TWI438899B (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011151320A (ja) * | 2010-01-25 | 2011-08-04 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2013206945A (ja) * | 2012-03-27 | 2013-10-07 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP2013206923A (ja) * | 2012-03-27 | 2013-10-07 | Renesas Electronics Corp | 半導体装置 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102157433A (zh) * | 2011-03-10 | 2011-08-17 | 杭州电子科技大学 | 具有p埋层的纵向沟道SOI nLDMOS器件单元的制作方法 |
KR102053354B1 (ko) * | 2013-07-17 | 2019-12-06 | 삼성전자주식회사 | 매립 채널 어레이를 갖는 반도체 소자 및 그 제조 방법 |
CN104795325A (zh) * | 2014-01-17 | 2015-07-22 | 北大方正集团有限公司 | 场效应管的制造方法 |
KR102219504B1 (ko) | 2015-03-18 | 2021-02-25 | 한국전자통신연구원 | 전계 효과 전력 전자 소자 및 그의 제조 방법 |
KR102510397B1 (ko) | 2017-09-01 | 2023-03-16 | 삼성디스플레이 주식회사 | 박막 트랜지스터 및 이를 포함하는 디스플레이 장치 |
CN109962068B (zh) * | 2017-12-14 | 2020-09-08 | 联华电子股份有限公司 | 存储器单元 |
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JPH11103057A (ja) * | 1997-03-17 | 1999-04-13 | Toshiba Corp | 半導体装置 |
JPH11103058A (ja) * | 1997-07-31 | 1999-04-13 | Toshiba Corp | 半導体装置 |
JP2006108514A (ja) * | 2004-10-07 | 2006-04-20 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
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JPH05110083A (ja) * | 1991-10-15 | 1993-04-30 | Oki Electric Ind Co Ltd | 電界効果トランジスタ |
AU3716000A (en) * | 1999-03-01 | 2000-09-21 | General Semiconductor, Inc. | Trench dmos transistor structure having a low resistance path to a drain contactlocated on an upper surface |
US6958513B2 (en) * | 2003-06-06 | 2005-10-25 | Chih-Hsin Wang | Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells |
JP5110776B2 (ja) * | 2004-07-01 | 2012-12-26 | セイコーインスツル株式会社 | 半導体装置の製造方法 |
CN100570890C (zh) * | 2004-07-01 | 2009-12-16 | 精工电子有限公司 | 使用沟槽结构的横向半导体器件及其制造方法 |
US7476932B2 (en) * | 2006-09-29 | 2009-01-13 | The Boeing Company | U-shape metal-oxide-semiconductor (UMOS) gate structure for high power MOS-based semiconductor devices |
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- 2009-02-20 TW TW098105461A patent/TWI438899B/zh not_active IP Right Cessation
- 2009-02-20 KR KR1020090014333A patent/KR101543792B1/ko active IP Right Grant
- 2009-02-24 US US12/380,144 patent/US8053820B2/en not_active Expired - Fee Related
- 2009-02-26 CN CN2009100081332A patent/CN101521222B/zh not_active Expired - Fee Related
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JPH11103057A (ja) * | 1997-03-17 | 1999-04-13 | Toshiba Corp | 半導体装置 |
JPH11103058A (ja) * | 1997-07-31 | 1999-04-13 | Toshiba Corp | 半導体装置 |
JP2006108514A (ja) * | 2004-10-07 | 2006-04-20 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
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JP2011151320A (ja) * | 2010-01-25 | 2011-08-04 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2013206945A (ja) * | 2012-03-27 | 2013-10-07 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP2013206923A (ja) * | 2012-03-27 | 2013-10-07 | Renesas Electronics Corp | 半導体装置 |
US8994100B2 (en) | 2012-03-27 | 2015-03-31 | Renesas Electronics Corporation | Semiconductor device including source and drain offset regions |
US9219145B2 (en) | 2012-03-27 | 2015-12-22 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9577090B2 (en) | 2012-03-27 | 2017-02-21 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
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US8598026B2 (en) | 2013-12-03 |
CN101521222A (zh) | 2009-09-02 |
CN101521222B (zh) | 2013-09-18 |
KR20090092231A (ko) | 2009-08-31 |
TW201001703A (en) | 2010-01-01 |
US20090224311A1 (en) | 2009-09-10 |
KR101543792B1 (ko) | 2015-08-11 |
US20120007174A1 (en) | 2012-01-12 |
US8053820B2 (en) | 2011-11-08 |
TWI438899B (zh) | 2014-05-21 |
JP5159365B2 (ja) | 2013-03-06 |
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