TWI419268B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI419268B
TWI419268B TW097119799A TW97119799A TWI419268B TW I419268 B TWI419268 B TW I419268B TW 097119799 A TW097119799 A TW 097119799A TW 97119799 A TW97119799 A TW 97119799A TW I419268 B TWI419268 B TW I419268B
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TW
Taiwan
Prior art keywords
film
semiconductor device
low dielectric
forming
wiring
Prior art date
Application number
TW097119799A
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English (en)
Chinese (zh)
Other versions
TW200915500A (en
Inventor
水澤愛子
岡田修
若林猛
三原一郎
Original Assignee
兆裝微股份有限公司
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Application filed by 兆裝微股份有限公司 filed Critical 兆裝微股份有限公司
Publication of TW200915500A publication Critical patent/TW200915500A/zh
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Publication of TWI419268B publication Critical patent/TWI419268B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
TW097119799A 2007-09-21 2008-05-29 半導體裝置及其製造方法 TWI419268B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007244977 2007-09-21
JP2008047090 2008-02-28

Publications (2)

Publication Number Publication Date
TW200915500A TW200915500A (en) 2009-04-01
TWI419268B true TWI419268B (zh) 2013-12-11

Family

ID=39686129

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097119799A TWI419268B (zh) 2007-09-21 2008-05-29 半導體裝置及其製造方法

Country Status (5)

Country Link
EP (1) EP2076922B1 (https=)
JP (2) JP4770893B2 (https=)
KR (1) KR101124898B1 (https=)
TW (1) TWI419268B (https=)
WO (1) WO2009037902A1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146678A (ja) * 2009-12-16 2011-07-28 Kyocera Corp 太陽電池素子の製造方法
US8507363B2 (en) * 2011-06-15 2013-08-13 Applied Materials, Inc. Laser and plasma etch wafer dicing using water-soluble die attach film
JP5888927B2 (ja) 2011-10-06 2016-03-22 株式会社ディスコ ダイアタッチフィルムのアブレーション加工方法
JP5839923B2 (ja) * 2011-10-06 2016-01-06 株式会社ディスコ パシベーション膜が積層された基板のアブレーション加工方法
US10141202B2 (en) 2013-05-20 2018-11-27 Qualcomm Incorporated Semiconductor device comprising mold for top side and sidewall protection
JP6315753B2 (ja) * 2013-10-01 2018-04-25 オリンパス株式会社 半導体装置の製造方法
US9312177B2 (en) * 2013-12-06 2016-04-12 Applied Materials, Inc. Screen print mask for laser scribe and plasma etch wafer dicing process
JP6346827B2 (ja) * 2014-08-13 2018-06-20 株式会社ディスコ 加工方法
JP6104352B2 (ja) * 2015-11-18 2017-03-29 株式会社ディスコ パシベーション膜が積層されたウエーハのアブレーション加工方法

Citations (6)

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TW200405496A (en) * 2002-08-09 2004-04-01 Casio Computer Co Ltd Semiconductor device and method of manufacturing the same
US20050017346A1 (en) * 2003-06-13 2005-01-27 Osamu Yamagata Semiconductor device, package structure thereof, and method for manufacturing the semiconductor device
US20050023689A1 (en) * 2003-07-28 2005-02-03 International Business Machines Corporation Chemical planarization performance for copper/low-k interconnect structures
US20050127512A1 (en) * 2003-12-12 2005-06-16 Sony Corporation Semiconductor device and the method of producing the same
US6939792B1 (en) * 2003-03-28 2005-09-06 Cypress Semiconductor Corporation Low-k dielectric layer with overlying adhesion layer
US7192867B1 (en) * 2002-06-26 2007-03-20 Cypress Semiconductor Corporation Protection of low-k dielectric in a passivation level

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TW444252B (en) * 1999-03-19 2001-07-01 Toshiba Corp Semiconductor apparatus and its fabricating method
JP2002057212A (ja) * 2000-08-09 2002-02-22 Mitsubishi Electric Corp 半導体装置、及び半導体装置の製造方法
JP4765143B2 (ja) * 2000-06-15 2011-09-07 住友ベークライト株式会社 絶縁膜用樹脂組成物およびこれを用いた絶縁膜
JP2002164428A (ja) * 2000-11-29 2002-06-07 Hitachi Ltd 半導体装置およびその製造方法
JP2002217198A (ja) * 2001-01-19 2002-08-02 Hitachi Ltd 半導体装置
JP2003100757A (ja) * 2001-09-27 2003-04-04 Toshiba Corp 半導体装置およびその製造方法
US7489032B2 (en) * 2003-12-25 2009-02-10 Casio Computer Co., Ltd. Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same
TW200527485A (en) * 2004-01-30 2005-08-16 Semiconductor Leading Edge Tec Multilayered wiring structure, method of forming buried wiring, semiconductor device, method of manufacturing semiconductor device, semiconductor mounted device, and method of manufacturing semiconductor mounted device
JP4398305B2 (ja) * 2004-06-02 2010-01-13 カシオ計算機株式会社 半導体装置およびその製造方法
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
JP2007161784A (ja) * 2005-12-09 2007-06-28 Fujifilm Corp 絶縁膜、化合物、膜形成用組成物及び電子デバイス

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7192867B1 (en) * 2002-06-26 2007-03-20 Cypress Semiconductor Corporation Protection of low-k dielectric in a passivation level
TW200405496A (en) * 2002-08-09 2004-04-01 Casio Computer Co Ltd Semiconductor device and method of manufacturing the same
US6939792B1 (en) * 2003-03-28 2005-09-06 Cypress Semiconductor Corporation Low-k dielectric layer with overlying adhesion layer
US20050017346A1 (en) * 2003-06-13 2005-01-27 Osamu Yamagata Semiconductor device, package structure thereof, and method for manufacturing the semiconductor device
US20050023689A1 (en) * 2003-07-28 2005-02-03 International Business Machines Corporation Chemical planarization performance for copper/low-k interconnect structures
US20050127512A1 (en) * 2003-12-12 2005-06-16 Sony Corporation Semiconductor device and the method of producing the same

Also Published As

Publication number Publication date
JP5393722B2 (ja) 2014-01-22
EP2076922B1 (en) 2012-09-05
JP2011176340A (ja) 2011-09-08
JP4770893B2 (ja) 2011-09-14
WO2009037902A1 (en) 2009-03-26
KR20090050088A (ko) 2009-05-19
JP2009231791A (ja) 2009-10-08
KR101124898B1 (ko) 2012-04-12
EP2076922A1 (en) 2009-07-08
TW200915500A (en) 2009-04-01

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