TWI416730B - 多閘極電晶體 - Google Patents

多閘極電晶體 Download PDF

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TWI416730B
TWI416730B TW099110083A TW99110083A TWI416730B TW I416730 B TWI416730 B TW I416730B TW 099110083 A TW099110083 A TW 099110083A TW 99110083 A TW99110083 A TW 99110083A TW I416730 B TWI416730 B TW I416730B
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semiconductor layer
fin
semiconductor
gate transistor
gate
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TW201114037A (en
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Chih Hsin Ko
Clement Hsingjen Wann
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Taiwan Semiconductor Mfg
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Description

多閘極電晶體
本發明係有關於積體電路裝置，且特別是有關於金氧半導體電晶體及其製造方法。
金氧半導體(MOS)電晶體之速度與金氧半導體電晶體之驅動電流密切相關，而驅動電流又與電荷遷移率有密切相關。例如，在N型金氧半導體電晶體之通道區域中之電子遷移率高時，N型金氧半導體電晶體即具有高驅動電流；在P型金氧半導體電晶體之通道區域中之電洞遷移率高時，P型金氧半導體電晶體即具有高驅動電流。
鍺係為常見的半導體材料，其電子遷移率及電洞遷移率皆較矽佳，矽為最常使用於積體電路製造之半導體材料。因此，鍺係為積體電路製造之絕佳材料。然而，過去矽卻較鍺更廣為使用，這是由於矽的氧化物(氧化矽)已可用於作為金氧半導體電晶體之閘極介電層，其可輕易的由矽基材加熱氧化形成。另一方面，鍺的氧化物溶於水，因此不適於形成閘極介電層。
然而，當金氧半導體電晶體之閘極介電層是使用高介電常數介電材料時，氧化矽所提供的便利性已不再是巨大的優勢，因此可重新檢視將鍺用於積體電路之可能。
除了鍺之外，由於第III族及第V族元素之化合物半導體材料(此後通稱為III-V化合物半導體)具有高電子遷移率，其也是製造金氧半導體裝置之良好選擇。
半導體工業所面臨之難題為，雖然由鍺及III-V化合物半導體所製造之金氧半導體電晶體具有高驅動電流，但同時也具有高漏電流(leakage current)。部分原因是由於鍺及III-V化合物半導體之高介電常數及較小的能帶間隙(bandgap)。例如，第1圖顯示為鍺及一些常用之III-V化合物半導體之能帶間隙及介電常數。第1圖顯示出鍺及常用之III-V化合物半導體之能帶間隙很小。因此，所對應之金氧半導體電晶體在其閘極及源/汲極之間會有能帶-能帶間的漏電流(band-to-band leakage currents)，且這些材料之高介電常數更會使漏電流之情況惡化。因此，這些金氧半導體電晶體之開關電流比(on/off current ratios；Ion/Ioff)相對較低。
本發明係提供一種多閘極電晶體，包括：一基材；一半導體鰭(semiconductor fin)位於此基材上，其包含：一中心鰭，由一第一半導體材料形成；及一半導體層，包含一第一部分及一第二部分，分別位於此中心鰭之兩側側壁上，其中此半導體層包含一與此第一半導體材料相異之第二半導體材料；一閘極電極，圍繞(wrapping around)此半導體鰭之側壁；以及一源極區及一汲極區，分別位於此半導體鰭之相對兩側，其中每個此中心鰭及此半導體層自此源極區延伸至此汲極區。
本發明亦提供另一種多閘極電晶體，包括：一基材；一半導體鰭位於此基材上，其包含：一中心鰭，由一第一材料形成；一半導體層，包含一第一部分及一第二部分，分別位於此中心鰭之兩側側壁上並鄰接此中心鰭，其中此半導體層包含一不同於此第一半導體材料之第二半導體材料，且其中此中心鰭及此半導體層形成一量子井；一閘極介電層，包含一第一部分位於此半導體層之此第一部分之外部側壁上，及一第二部分位於此半導體層之此第二部分之外部側壁上；一閘極電極，位於此閘極介電層上；以及一源極區及一汲極區，分別位於此中心鰭之及此半導體層之相對兩側且鄰接此中心鰭及此半導體層，其中此源極區及此汲極區係為n型區域。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明接下來將會提供許多不同的實施例以實施本發明中不同的特徵。值得注意的是，這些實施例提供許多可行之發明概念並可實施於各種特定情況。然而，在此所討論之這些特定實施例僅用於舉例說明本發明之製造及使用方法，但非用於限定本發明之範圍。
本發明在此係揭示一種新穎的鰭式場效電晶體(fin field-effect transistor;FinFET)及其製造方法，並將舉例本發明實施例之製造中間過程，也將討論這些實施例之變化及操作。在本發明之各種舉例之圖示及實施例中，相似元件符號表示為類似的元件。
第2圖顯示為鰭式場效電晶體(FinFET)100形成於基底材料10上之透視圖。基底材料10可由介電材料形成，例如氧化矽。或者，基底材料10可由半導體材料形成，其包含但不限於矽、鍺、砷化鍺及其類似物。在其他實施例中，基底材料10可包含部分的半導體基材及半導體基材中之隔離結構。鰭式場效電晶體100包含源極區4、汲極區6及位於其間之鰭20。鰭式場效電晶體100可為N型場效電晶體，因此源極區4及汲極區6為n型摻雜區域，其可由例如佈植製程形成。閘極介電層12可形成在鰭20之頂部及兩側側壁上。閘極電極8更形成於閘極介電層12上。在一實施例中，可省略閘極介電層12。
隨後圖示將顯示更詳盡之剖面圖，除非特別聲明，其係顯示沿著第2圖中線段3A-3A之垂直剖面。第3A圖顯示為雙閘極鰭式場效電晶體之剖面圖。鰭20包含由第一半導體材料形成之中央鰭22及由第二半導體材料形成之半導體層24，且第二半導體材料不同於第一半導體材料。半導體層24形成於中央鰭22之兩側側壁上。閘極介電層12形成在半導體層24之側壁上。閘極電極8形成在閘極介電層12上。
閘極介電層12可由常用之介電材料形成，例如氧化矽、氮化矽、氮氧化物、前述之多層材料或前述之組合。閘極介電層12也可由高介電常數材料形成。高介電常數介電材料可具有大於4之介電常數值，或甚至大於7。高介電常數介電材料也可包含含鋁之介電材料，例如Al2 O3 、HfAlO、HfAlON、AlZrO；含鉿材料，例如HfO2 、HfSiOx、HfAlO、HfZrSiOx、HfSiON；及其他材料，例如LaAlO3 及ZrO2 。閘極電極8可由摻雜之多晶矽、金屬、金屬氮化物、金屬矽化物及其類似物形成。
第3B圖顯示為第3A圖所示之雙閘極鰭式場效電晶體之導帶圖。在一實施例中，中央鰭22具有能帶間隙EgA，半導體層24具有能帶間隙EgB，且能帶間隙EgB較能帶間隙EgA大。在一較佳實施例中，能帶間隙EgA較能帶間隙EgB小0.1eV，或也可為較大或較小之能帶間隙差距(bandgap differences)。中央鰭22之導帶EcA也可低於半導體層24之導帶EcB。在一實施例中，中心鰭之導帶EcA也可低於半導體層之導帶EcB約0.05eV，或也可為較大或較小之導帶差距(conduct band differences)。藉由比較高電子遷移率之半導體材料之能帶間隙可選擇適當的中央鰭22及半導體層24材料，其可包含但不限於矽、鍺、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP及其類似物。在一實施例中，中央鰭22包含InGaAs，且半導體層24包含GaAs。在其他實施例中，中央鰭22包含InAs，且半導體層24包含InAlAs。
請重新參見第3A圖，當中央鰭22之能帶間隙EgA小於半導體層24之能帶間隙EgB時，則鰭20(包含中央鰭22及半導體層24)形成量子井。當施予不為零之閘極電壓至閘極電極8時，由於量子侷限效應(quantum confinement effect)，電子傾向於流經鰭20之中間部分，也就是中央鰭22。如此，由於中央鰭22之能帶間隙較小而具有高載子遷移率(carrier mobility)，因而使所對應之鰭式場效電晶體100具有高開電流(on-current；Ion)。另一方面，當閘極電壓為零而關閉鰭式場效電晶體100時，電子傾向流經鰭20之表面層，也就是半導體層24。如此，由於能帶間隙EgB較高而具有低載子遷移率，因而使所對應之鰭式場效電晶體100具有低閉路電流(漏電流；Ioff)。因此，鰭式場效電晶體100具有高的開關電流比。
為了改善鰭式場效電晶體100之效能，需加強量子井。因此，中央半導體鰭20之厚度T1最好較薄。在一實施例中，厚度T1小於約50nm，且可甚至小於約10nm。半導體層24之厚度T2可小於約50nm。
第3A圖更包含硬罩幕26於半導體鰭20上，其中硬罩幕26可由常用之介電材料形成，例如氮化矽、氧化矽、氮氧化矽及其類似物。第3A圖所示之鰭式場效電晶體100係為雙閘極鰭式場效電晶體。
在另一實施例中，如第4圖所示，未有硬罩幕位於鰭20上。反之，半導體層24位於中央鰭22之兩側側壁上，並與位在中央鰭頂部22的部分連接形成連續層。閘極介電層12亦形成連續層。如第4圖所示之鰭式場效電晶體100係為三閘極鰭式場效電晶體。
第5至8圖顯示為第3A圖所示之實施例之製造中間階段之剖面圖。參見第5圖，其係為提供基材200。基材200可為半導體，其可由常用之半導體材料形成，例如矽、鍺、砷化鍺或其類似物。絕緣區，例如淺溝槽隔離(STI)區30，形成於基材200中。相鄰淺溝槽隔離區30之間可具有小的間距S，例如小於約50nm，此間距可等於或大於如第3A圖所示之中央鰭22之厚度T1。
接著，如第6圖所示，使基材中相鄰淺溝槽隔離區30之間的部分200以形成凹陷32。凹陷深度D1可實質上等於或小於淺溝槽隔離區30之厚度D2。在第7圖中，中央鰭22係為在凹陷32中磊晶成長。硬罩幕26可為毯覆式形成及圖案化以覆蓋中央鰭22，如第7圖所示。
在另一實施例中，基材200包含第III族及第V族元素之化合物半導體材料(在此之後通稱III-V化合物半導體)，因此可省略凹陷32之形成及在凹陷32中之磊晶成長。如此，基材200中相鄰淺溝槽隔離區30之間的部分即為中央鰭22。
接著，如第8圖所示，選擇性蝕刻淺溝槽隔離區30之頂部部分，且底部部分則保留未受蝕刻。因此，中央鰭22具有一部份超出淺溝槽隔離區30。在形成硬罩幕26之後，進行等向性蝕刻，以使中央鰭22側向凹陷，而使硬罩幕26延伸超過剩餘的中央鰭22。接著，如第3A圖所示，磊晶成長半導體層24，並接著形成閘極介電層12。在隨後步驟中，形成閘極電極8，而形成如第3A圖所示之結構。
第9至11圖顯示為如第4圖所示之實施例之製造中間間段之剖面圖。初始步驟基本上如同第5至7圖，包含在基材200中形成淺溝槽隔離區30，並選擇性地使中央鰭22凹陷及磊晶成長。然而，如第9圖所示，其未有硬罩幕形成。第10圖顯示為經蝕刻之淺溝槽隔離區30，以使中央鰭22具有一突出部分超出淺溝槽隔離區30之剩餘部分。接著，如第11圖所示，磊晶成長半導體層24，接著形成閘極介電層12。在隨後步驟中，形成閘極電極8，因此形成如第4圖所示之結構。
第12A圖顯示另一種雙閘極鰭式場效電晶體。除未形成閘極介電層12外，此實施例近似於第3A圖所示之實施例。在此實施例中，可由金屬形成閘極電極8，因此形成肖特基(Schottky)屏障於閘極電極8及半導體層24之間，而形成空乏層40(depletion layer)，其可作為閘極介電層而電性絕緣閘極電極8及半導體層24。第12B圖顯示為能帶圖。中心鰭22及半導體層24之材料已於先前討論，故在此不重複贅述。同樣地，中心鰭22之能帶間隙EgA小於半導體層24之能帶間隙EgB，且中心鰭22之導帶EcA可低於半導體層EcB之導帶。
第13圖顯示為另一個三閘極鰭式場效電晶體之實施例。此實施例近似於第4圖所示之實施例，除了因肖特基(Schottky)屏障形成於閘極電極8及半導體層24之間，而將第4圖所示之閘極介電層替換成空乏層40。
第14及第15圖中顯示為其他多閘極鰭式場效電晶體，其中量子井係由多於兩種之半導體材料形成。在一實施例中，半導體層44之能帶間隙EgB大於中心鰭22之能帶間隙EgA，且小於半導體層24之能帶間隙EgB(參見第3B及13圖)。同時，半導體層44之導帶高於中心鰭22之導帶EcA，且低於半導體層24之導帶EcB(參見第3B及13圖)。在第14圖中，形成硬罩幕26，但在第15圖中未有硬罩幕形成。
此外，本發明之範圍不限定於本說明書所述之特定程序、機器、製造、物質之組合、功能、方法或步驟。熟知本領域技藝人士將可依照本發明所揭示之現有或未來所發展之特定程序、機器、製造、物質之組合、功能、方法或步驟達成相同的功能或相同的結果。因此本發明之保護範圍包含這些程序、機器、製造、物質之組合、功能、方法或步驟。雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
4．．．源極
6．．．汲極
8．．．閘極電極
10．．．基材
12．．．閘極介電層
20．．．鰭
22．．．中央鰭
24．．．半導體層
26．．．硬罩幕
30．．．淺溝槽隔離區
32．．．凹陷
40．．．消耗層
44．．．半導體層
100．．．鰭式場效電晶體
200．．．基材
第1圖顯示為一些半導體材料之能帶間隙及介電常數；
第2圖顯示為本發明一實施例之透視圖；
第3A圖顯示為一雙閘極鰭式場效電晶體之剖面圖；
第3B圖顯示為第3A圖所示之實施例之能帶圖；
第4圖顯示為一三閘極鰭式場效電晶體之剖面圖；
第5至8圖顯示為第3A圖所示之雙閘極鰭式場效電晶體之製造中間階段之剖面圖；
第9至11圖顯示為第4圖所示之三閘極鰭式場效電晶體之製造中間階段之剖面圖；
第12A圖顯示為未有閘極介電層形成之雙閘極鰭式場效電晶體之剖面圖；
第12B圖顯示為第12A圖所示之實施例之能帶圖；
第13圖顯示為未有閘極介電層形成之三閘極鰭式場效電晶體之剖面圖；
第14圖顯示為含三種半導體材料於鰭中之雙閘極鰭式場效電晶體；
第15圖顯示為含三種半導體材料於鰭中之三閘極鰭式場效電晶體。
8．．．閘極電極
10．．．基材
12．．．閘極介電層
20．．．鰭
22．．．中央鰭
24．．．半導體層
26．．．硬罩幕
30．．．淺溝槽隔離區
200．．．基材

Claims (13)

  1. 一種多閘極電晶體，包括：一基材；一半導體鰭(semiconductor fin)位於該基材上，其包含：一中心鰭，由一第一半導體材料形成；以及一半導體層，包含一第一部分及一第二部分，分別位於該中心鰭之兩側側壁上，其中該半導體層包含一與該第一半導體材料相異之第二半導體材料，且該第一半導體材料之能帶間隙小於該第二半導體材料之能帶間隙；一閘極電極，圍繞(wrapping around)該半導體鰭之側壁；以及一源極區及一汲極區，分別位於該半導體鰭之相對兩側，其中每個該中心鰭及該半導體層自該源極區延伸至該汲極區。
  2. 如申請專利範圍第1項所述之多閘極電晶體，其中該中心鰭及該半導體層形成一量子井(quantum well)。
  3. 如申請專利範圍第1項所述之多閘極電晶體，其中該第一半導體材料之導帶(conduction band)低於該第二半導體材料之導帶。
  4. 如申請專利範圍第1項所述之多閘極電晶體，更包含一閘極介電層，其含有一第一部分及一第二部分，分別位於該半導體層之該第一部分之外部側壁上及該半導體層之該第二部分之外部側壁上。
  5. 如申請專利範圍第1項所述之多閘極電晶體，其中該閘極電極與該半導體層之該第一部分及該第二部分相接觸。
  6. 如申請專利範圍第1項所述之多閘極電晶體，其中該半導體層更包含一第三部分位於該中心鰭之頂部表面上，並連接該半導體層之該第一部分及該半導體層之該第二部分。
  7. 如申請專利範圍第1項所述之多閘極電晶體，更包含一硬罩幕，位於該中心鰭之頂部表面上，並阻斷該半導體層之該第一部分及該半導體層之該第二部分之間的連接。
  8. 如申請專利範圍第7項所述之多閘極電晶體，其中該硬罩幕層直接延伸超過該半導體層之該第一部分及該半導體層之該第二部分。
  9. 如申請專利範圍第1項所述之多閘極電晶體，更包括一額外之半導體層，包含：一第一部分，位於該半導體層之該第一部分及該中心鰭之間；以及一第二部分，位於該半導體層之該第二部分及該中心鰭之間，其中該額外之半導體層之能帶間隙大於該中心鰭之能帶間隙且小於該半導體層之能帶間隙。
  10. 一種多閘極電晶體，包括：一基材；一半導體鰭位於該基材上，其包含：一中心鰭，由一第一材料形成； 一半導體層，包含一第一部分及一第二部分，分別位於該中心鰭之兩側側壁上並鄰接該中心鰭，其中該半導體層包含一不同於該第一半導體材料之第二半導體材料，且該第一半導體材料之能帶間隙小於該第二半導體材料之能帶間隙，且其中該中心鰭及該半導體層形成一量子井；一閘極介電層，包含一第一部分位於該半導體層之該第一部分之外部側壁上，及一第二部分位於該半導體層之該第二部分之外部側壁上；一閘極電極，位於該閘極介電層上；以及一源極區及一汲極區，分別位於該中心鰭之及該半導體層之相對兩側且鄰接該中心鰭及該半導體層，其中該源極區及該汲極區係為n型區域。
  11. 如申請專利範圍第10項所述之多閘極電晶體，其中該中心鰭向下延伸至該基材中，其中該基材包含一絕緣區，該絕緣區之一側與該中心鰭之側壁相接觸，且該絕緣區域之一頂部表面與該半導體層之底端相接觸。
  12. 如申請專利範圍第10項所述之多閘極電晶體，其中該第一半導體材料之導帶低於該第二半導體材料之導帶。
  13. 如申請專利範圍第10項所述之多閘極電晶體，其中該半導體層更包含一第三部分，位於該中心鰭之頂部表面上，並連接該半導體層之第一部分及該半導體層之第二部分。
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