TWI385790B - 相變化記憶體之多晶矽栓塞雙極性電晶體 - Google Patents
相變化記憶體之多晶矽栓塞雙極性電晶體 Download PDFInfo
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Description
本發明係關於一種使用相變化記憶材料的高密度記憶裝置及其製造方法,其中,相變化記憶材料可包括硫屬化物材料及其他可程式化電阻材料。
相變化記憶材料,如硫屬化物材料及其他類似材料,在施加強度適用於積體電路的電流時,可於非晶態與晶態之間進行相變化。大致非晶態的電阻較大致晶態來得高,而此特性正可用於資料的表示。由於具備此種特性,業界致力研究如何將可程式化電阻材料應用於可隨機讀寫存取的非揮發性記憶電路。
由非晶態轉變為晶態大致上屬於低電流操作,而由晶態轉變為非晶態(此處稱為重置)則大致上屬於高電流操作。重置過程係使用短暫的高電流密度脈衝來熔化或破壞晶體結構,之後相變化材料快速冷卻,將熔融狀態的相變化材料予以淬火,使至少部份相變化材料可穩定存在非晶態。
由於相變化是由加熱所引發,欲提高相變化材料的溫度並造成相變化,就必須提供相對高的電流。然而,因為場效電晶體是使用低電流來驅動,對於具有場效電晶體存取裝置的相變化記憶胞而言,如何取得需要的電流就成了問題。
雖然雙極性接面電晶體可提供較場效電晶體更大的電流驅動,但要將雙極性接面電晶體與CMOS周邊電路進行整合並不容易,且會讓設計及製程變得非常複雜。
因此,有必要提供一種相變化記憶胞,其具有與CMOS周邊電路相容之雙極性接面電晶體存取裝置,且其設計整合與製程相對容易。
此處所述之記憶裝置包括一單晶半導體基材及位於基材內之複數條字元線,其中單晶半導體基材具有第一導電性,且字元線具有與第一導電性相異之第二導電性。記憶裝置包括複數個記憶胞,其中某些記憶胞包括雙極性接面電晶體與記憶元件。雙極性接面電晶體包括射極、基極以及集極,其中,射極包括具有第一導電性之摻雜多晶矽,且與對應字元線連接以定義出pn接面。基極係利用位於射極下方的對應字元線一部分所形成,集極包括位於該基極下方之單晶半導體基材一部分。
此處所描述之記憶裝置製造方法包括形成一具有第一導電性之單晶半導體基材,以及於該單晶半導體基材內形成複數介電溝渠。複數條字元線乃形成於單晶半導體基材內,字元線係具有與第一導電性相異之第二導電性,且相鄰之字元線係由介電溝渠所分隔。該方法亦形成複數摻雜多晶矽栓塞、複數記憶元件、上電極以及複數條位元線,其中,摻雜多晶矽栓塞具有該第一導電性,且與字元線接觸;記憶元件係電性耦接至摻雜多晶矽栓塞;上電極係位於記憶元件上;位元線係位於上電極上,且耦接至上電極。
此處所描述之記憶裝置包括相變化記憶胞,其不但具有與CMOS周邊電路相容之雙極性接面電晶體存取裝置,且不需特別複雜之設計整合與製程即可生產。
本發明之其他特色與優點可配合圖式、實施方式及申請專利範圍來了解。
以下揭露之內容大多需配合參考特定結構實施例及方法,然而,揭露內容之範圍並不僅限於該些特定結構實施例及方法,且揭露內容亦可透過其他特徵、元件、方法及實例來實施。本發明所揭露之內容雖可透過較佳實施例來說明,但該些實施例不可用來限制本發明之範圍,本發明專利權之範圍須由申請專利範圍為準。本領域具有通常知識者於參考本發明揭露之內容後,應可了解其他可能的均等實施方式。此外,於後述之內容中,不同實施例之相同元件乃以相同元件符號表示。
第1圖係部分記憶胞陣列100之示意圖,其中記憶胞包括具有多晶矽射極之雙極性接面電晶體。
如第1圖所示,陣列100中的各記憶胞均包括雙極性接面電晶體存取裝置及電性串連之記憶元件,且記憶元件可被設置成多種電阻狀態之一,進而儲存一個以上的資料位元。
陣列100包括複數條字元線130,如字元線130a、130b、130c、130d,其係於第一方向上平行延伸,並與字元線解碼器與驅動器150形成電性連接。字元線130係耦接至陣列100之雙極性存取電晶體之基極端。
複數條位元線120,如位元線120a、120b、120c、120d,係於第二方向上平行延伸,並與位元線解碼器160形成電性連接。各雙極性接面電晶體之射極端係透過記憶元件耦接至一條對應之位元線120。
陣列100之記憶胞乃以共集極組態方式耦接,也就是說,記憶胞之集極端係耦接至參考電壓,且其輸入、輸出分別為基極與射極端。因此,在操作過程中,位元線120與字元線130之電壓,會誘發電流自位元線120經由射極端與記憶元件流至集極端或是反向亦然自集極端流至位元線120。
於第1圖中,集極端係接地。無庸置疑地,集極端不一定要接地,其亦可耦接至可提供參考電壓之電壓源,舉例來說,如第25圖之偏壓調整供應電壓、電流源2536。
以記憶胞陣列100中的記憶胞110為例,其包括雙極性接面電晶體115及電性連接之相變化記憶元件125。雙極性接面電晶體115之基極端耦接至字元線130b,而雙極性接面電晶體115之射極端則透過相變化記憶元件125耦接至位元線120b。
欲讀取或寫入記憶胞陣列100中的記憶胞110,可施加適當大小的電壓及/或電流至對應之字元線130b與位元線120b,以誘發流經特定記憶胞110之電流。電壓及/或電流的施加時間與強度係依所進行的操作而定,如讀取操作或寫入操作。
於記憶胞110之重置(抹除)操作中,施加至字元線130b與位元線120b之重置脈衝會誘發流經記憶元件125之電流,以使主動區域開始轉變成非晶相,而將相變化材料之電阻設定在與重置狀態相關的電阻值範圍內。前述之重置脈衝屬於相對高能量的脈衝,其至少可提高記憶元件125之主動區域的溫度,使之高於相變化材料的相變(結晶)溫度外,也高於熔融溫度,以至少讓主動區域成為液態。之後,快速終止重置脈衝,使主動區域在一短暫的淬火時間內快速冷卻至相變溫度以下,並穩定形成一大致非晶相。
於記憶胞110之設置(或程式化)操作中,乃於適當的時間內施加適當大小的程式化脈衝至字元線130b與位元線120b,以誘發流經記憶胞110之電流,其可將部分主動區域之溫度升高至相變溫度以上,並使該部分主動區域產生由非晶相轉變至結晶相之變化,而此變化會降低記憶元件125之電阻,並將記憶胞110設置在一特定狀態。
於記憶胞110內資料的讀取(或感應)操作中,乃於適當的時間內施加適當大小的讀取脈衝至字元線130b與位元線120b,以誘發不致使記憶元件125之電阻狀態發生改變的電流。由於流經記憶胞110的該電流,其大小端視記憶元件125的電阻與儲存在記憶胞110的資料而定。因此,可利用方塊165之感應放大器來比較位元線120b之電流與一穩定之參考電流,或以其他方式,來確定記憶胞的資料狀態。
第2A及2B圖為陣列100中記憶胞(包括記憶胞110)部分之剖面圖,前者係沿位元線120進行剖面而得,而後者係沿字元線130進行剖面而得。第2C圖則為陣列100之上視圖。
陣列包括基材200,其包括具有第一導電性之井202,且該井202包括第一摻雜區205與第二摻雜區210,第二摻雜區210的摻雜濃度係較第一摻雜區205高。基材200尚包括位於井202內之字元線130,字元線130係沿貫穿第2A圖之第一方向延伸,且其導電性與第一導電性不同之除了第一摻雜區205、第二摻雜區210以及字元線130外,基材200更包括單晶半導體基材。
記憶胞110包括經摻雜之多晶矽栓塞220,其具有第一導電性,且係作為雙極性接面電晶體115之射極。此外,經摻雜之多晶矽栓塞220與對應之字元線130b接觸,以定義pn接面222。
字元線130b位於栓塞220下的部分係作為雙極性接面電晶體115之基極,而井202位於字元線130b下的部分則作為雙極性接面電晶體115之集極。
字元線130係由位於井202內包含介電材料的介電溝渠230所分隔。導電接觸窗215、217將井202之第二摻雜區210耦接至與參考電壓耦接之導電材料140。
於本例示實施例中,經摻雜之多晶矽栓塞220包括濃摻雜之N型(N++)多晶矽,字元線130包括位於矽基材200內之P型材料摻雜區域,第一摻雜區205包括位於矽基材200內之N型材料摻雜區域,且第二摻雜區210包括位於矽基材200內之濃摻雜N型(N+)材料區域,據此以形成npn雙極性電晶體115。
於另一實施例中,經摻雜之多晶矽栓塞220包括濃摻雜之P型(P++)多晶矽,字元線130包括位於矽基材200內之N型材料摻雜區域,第一摻雜區205包括位於矽基材200內之P型材料摻雜區域,且第二摻雜區210包括位於矽基材200內之濃摻雜P型(P+)材料區域,據此以形成pnp雙極性電晶體115。
記憶胞110包括位於經摻雜之多晶矽栓塞220上之導電覆蓋層240,於本實施例中,導電覆蓋層240包括矽化物,如含有Ti、W、Co、Ni或Ta之矽化物。導電覆蓋層240可提供介於經摻雜之多晶矽栓塞220與下電極250之間的低電阻接觸,且經摻雜之多晶矽栓塞220與導電覆蓋層240係貫穿介電質260。於本實施例中,介電質260包括二氧化矽層262、位於二氧化矽層262上之氮化矽層264以及位於氮化矽層264上之硼磷矽玻璃(BPSG)層或磷矽玻璃(PSG)層。在某些實施例中,則可以不需要氮化矽層264。
下電極250位於導電覆蓋層240之上,且貫穿介電質270並與記憶元件125之下表面接觸,其中記憶元件125可包括一種以上選自下列群組之材料:鍺、銻、碲、硒、銦、鈦、鎵、铋、錫、銅、鈀、鉛、銀、硫、矽、氧、磷、砷、氮及金。
下電極250可以包括氮化鈦或氮化鉭,且不以此為限。氮化鈦不但可與GST(容後詳述)形成良好的接觸,且是半導體製程常用的材料,又能在GST相變的高溫(通常介於600至700℃)提供良好的擴散障壁,因此,當記憶元件125包括GST時,下電極的材料較佳為氮化鈦。此外,下電極250也可以包括氮化鋁鈦或氮化鋁鉭,或包括一種以上選自下列群組之材料:鈦、鎢、鉬、鋁、鉭、銅、鉑、銥、鑭、鎳、氮、氧、钌或以上元素之組合。
上電極280位於記憶元件125之上,且由導電接觸窗290電性耦接至位元線120b。上電極280與位元線120可包括前述任一種下電極250所包括的材料,且不以此為限。
介電質295環繞於記憶元件125、上電極280與導電接觸窗290之四周,且於本實施例中,介電質295包括二氧化矽,而介電質270包括氮化矽。
於操作時,位元線120b及字元線130b之電壓,會誘發電流自位元線120b經由射極端與記憶元件125流至基材200或是反向亦然自基材200流至位元線120b。
主動區域128屬於記憶元件125的一部分,且位於主動區域128中的記憶材料可被誘發而在至少兩個固態相間進行相變化。本領域具有通常知識者應可了解,主動區域128可以非常小,如第2A圖所示,並可藉此降低誘發相變化所需電流的大小。記憶元件125的厚度126可藉由薄膜沉積來建立,於某些實施例中,厚度126可小於100奈米,如介於10到100奈米之間。此外,記憶元件125之寬度127大於下電極250之寬度252,且下電極250之寬度252較佳係小於形成陣列100所採用製程的最小特徵尺寸,如微影製程。由於下電極250越小,就越能將其附近的部分記憶元件125之電流集中,因此較小的下電極250將可降低誘發主動區域128產生相變化所需電流的大小。此外,由於介電質270還可提供主動區域128額外的隔熱效果,產生相變化所需電流的大小亦可進一步降低。
如前所述,雙極性接面電晶體所能提供的電流驅動較場效電晶體來得大,此外,因為電晶體的射極包含摻雜多晶矽材料,而可以獲得相對較大的電流增益,以藉此降低字元線130所需使記憶元件產生相變化之電流。
第3A-3B圖為陣列100中第二實施例之記憶胞(包括記憶胞110)部分剖面圖,前者係沿位元線120進行剖面而得,而後者係沿字元線130進行剖面而得。
於此實施例中,記憶元件125包括第一部分323與第二部分324。介電質270環繞於第一部分323四周,且第一部分323貫穿介電質270並與導電覆蓋層240接觸。第二部分324係位於第一部分323之上,而記憶元件125將導電覆蓋層240耦接至上電極280。
本領域具有通常知識者應可了解,主動區域128可以非常小,如第3A-3B圖所示,並可藉此降低誘發相變化所需電流的大小。記憶元件125第一部分323之寬度300小於導電覆蓋層240之寬度,也小於記憶元件125第二部分324之寬度。於較佳實施例中,第一部分323之寬度300小於形成陣列100所採用製程的最小特徵尺寸,如微影製程。由於記憶元件125之第一部分323越小就越能將其電流集中,因此較小的第一部分323將可降低誘發主動區域128產生相變化所需電流的大小。此外,於較佳實施例中,介電質270可包括能提供主動區域128額外隔熱效果的材料,以進一步降低產生相變化所需電流的大小。除此之外,記憶元件125之第二部分324以及第一部分323的其他部分還可提供主動區域128一定的隔熱效果,以隔絕來自上電極280的熱能。
第4A-4B圖為陣列100中第三實施例之記憶胞(包括記憶胞110)部分剖面圖,前者係沿位元線120進行剖面而得,而後者係沿字元線130進行剖面而得。
於此實施例中,記憶元件125包括記憶材料柱,其貫穿介電質270並將導電覆蓋層240耦接至上電極280,而介電質270環繞於記憶元件125之四周。
本領域具有通常知識者應可了解,主動區域128可以非常小,以降低誘發相變化所需電流的大小。記憶元件125之寬度400小於上電極280與導電覆蓋層240的寬度,且較佳係小於形成陣列100所採用製程的最小特徵尺寸,如微影製程。由於寬度的不同,電流將集中於此微小之柱狀記憶元件125,並可藉此降低誘發主動區域128產生相變化所需電流的大小。此外,於較佳實施例中,介電質270可包括能提供主動區域128隔熱效果的材料,以進一步降低產生相變化所需電流的大小。同時,可將主動區域128從導電覆蓋層240及上電極280區隔開,讓記憶元件125的其他部分也可提供主動區域128一定的隔熱效果。
第5A-5B圖為陣列100中第四實施例之記憶胞(包括記憶胞110)部分剖面圖,前者係沿位元線120進行剖面而得,而後者係沿字元線130進行剖面而得。
第5A-5B圖所示之實施例與第2A-2C圖所示者相似,在字元線130的側壁表面上有側壁導體510。於此實施例中,側壁導體510包括自我對準的矽化物(金屬矽化物),且其包括鈦、鎢、鈷、鎳、鉭,但並不以此為限。側壁導體510可增加字元線130的導電性,進而降低其負載,並提升陣列之一致性。
記憶胞的實施例包括了使用相變化記憶材料(包含硫屬化物材料與其他材料)的記憶元件。硫屬化物包括下列四元素之任一者:氧(O)、硫(S)、硒(Se)、以及碲(Te),其位於元素週期表的第VI族。硫屬化物包括將一硫屬元素與一更具正電性之元素或自由基結合而得。硫屬化物合金包括將硫屬化物與其他物質如過渡金屬等結合。硫屬化物合金通常包括一個以上選自元素週期表第六欄的元素,例如鍺(Ge)以及錫(Sn)。通常,硫屬化物合金包括下列元素中一個以上的複合物:銻(Sb)、鎵(Ga)、銦(In)以及銀(Ag)。許多以相變化為基礎之記憶材料已經被描述於技術文件中,包括下列合金:鎵/銻、銦/銻、銦/硒、銻/碲、鍺/碲、鍺/銻/碲、銦/銻/碲、鎵/硒/碲、錫/銻/碲、銦/銻/鍺、銀/銦/銻/碲、鍺/錫/銻/碲、鍺/銻/硒/碲以及碲/鍺/銻/硫。在鍺/銻/碲合金家族中,可以嘗試大範圍的合金成分。此成分可以下列特徵式表示:Tea
Geb
Sb100-(a+b)
。曾有研究員指出,最有用的合金是在沈積材料中所包含之平均碲濃度係遠低於70%,典型地係低於60%,並在一般型態合金中的碲含量範圍從最低23%至最高58%,且最佳係介於48%至58%之碲含量。鍺的濃度係高於約5%,且其在材料中的平均範圍係從最低8%至最高30%,一般係低於50%,最佳地,鍺的濃度範圍係介於8%至40%。在此成分中所剩下的主要成分則為銻。其中百分比代表所組成元素的原子總數為100%時,各原子的百分比,請參考Ovshinky 5,687,112專利第10~11欄。由另一研究者所評估的特殊合金包括Ge2
Sb2
Te5
、GeSb2
Te4
以及GeSb4
Te7
,請參考Noboru Yamada的文章”Potential of Ge-Sb-Te Phase-Change Optical Disks for High-Data-Rate Recording”,SPIE v.3109,pp.28-37(1997)。更一般地,過渡金屬如鉻(Cr)、鐵(Fe)、鎳(Ni)、鈮(Nb)、鈀(Pd)、鉑(Pt)以及上述之混合物或合金,可與鍺/銻/碲結合以形成一有可程式化的電阻之相變化合金。可使用的記憶材料之範例,係如Ovshinsky ‘112專利中第11-13欄所述,其範例在此係列入參考。
在某些實施例中,硫屬化物以及其他相變化材料係摻雜有雜質,以修正其導電性、相變化溫度、熔化溫度以及其他使用摻雜硫屬化物的記憶元件的性質。用以摻雜硫屬化物的代表性雜質包括氮、矽、氧、二氧化矽、氮化矽、銅、銀、金、鋁、氧化鋁、鉭、氧化鉭、氮化鉭、鈦以及鈦氧化物,請參見美國專利6800504號以及美國專利公開號2005/0029502號。
相變化合金可在此記憶胞主動通道區域內,依其位置順序於大致非晶態之第一結構狀態與為大致結晶態之第二結構狀態之間切換。這些合金至少為雙穩定態。「非晶」係指相對較無次序之結構,其較單晶更無次序性,而帶有可偵測之特徵,如較結晶態更高之電阻值。「結晶態」係指相對較有次序之結構,其較非晶態更有次序,因此包括可偵測的特徵例,如比非晶態更低的電阻值。典型地,相變化材料可電性切換至完全結晶態與完全非晶態之間所有可偵測的不同狀態。其他受到非晶態與結晶態之改變而影響之材料特徵包括原子次序、自由電子密度以及活化能。此材料可切換為不同的固態或可切換成為由兩種以上固態所形成之混合物,提供從非晶態至結晶態之間的灰階部分。此材料中的電性質亦可能隨之改變。
相變化合金可藉由電脈衝而從一種相態切換至另一相態。曾有研究人員指出,一較短、較大幅度的脈衝傾向於將相變化材料的相態改變成大致非晶態。一較長、較低幅度的脈衝傾向於將相變化合金的相態改變成大致結晶態。由於較短、較大幅度脈衝中的能量夠大,其足以破壞結晶結構的鍵結,同時時間夠短,因此可以防止原子再次排列成結晶態。在無須過度實驗的情形下,可利用實驗方法決定適合特定相變化合金的適當脈衝量變曲線。在本說明書的後續部份,相變化材料乃以GST指稱。此外,應了解的是,也可以使用其他類型的相變化材料。適用於PCRAM中的材料係為Ge2
Sb2
Te5
。
其他可以使用於本發明其他實施例的可程式化電阻記憶材料包括利用不同晶體變化來決定電阻者,或是利用電脈衝來改變電阻狀態者。舉例來說,可使用電阻隨機存取記憶體(RRAM)之金屬氧化物材料,如鎢氧化物(WOx
)、氧化鎳、五氧化二鈮、二氧化銅、五氧化二鉭、三氧化二鋁、氧化鈷、三氧化二鐵、二氧化鉿、二氧化鈦、鈦酸鍶、鋯酸鍶、鈦酸鍶鋇。其他實施例則可包括用於磁阻隨機存取記憶體(MRAM)之材料,而磁阻隨機存取記憶體可以是旋轉力矩轉移隨機存取記憶體(STT MRAM)。舉例來說,這些材料可以是以下群組至少一種:鈷鐵硼、鐵、鈷、鎳、釓、鏑、鈷鐵、鎳鐵、錳砷、錳鉍、錳銻、二氧化鉻、氧化錳三氧化二鐵、氧化鐵五氧化二鐵、氧化鎳三氧化二鐵、氧化鎂二鐵、氧化銪及鐵磁性氧化物釔鐵石榴石(Y3
Fe5
O12
)。此可參考美國專利公開號第2007/0176251號,其發明名稱為”Magnetic Memory Device and Method of Fabricating the Same”,其中之內容乃併入本文作為參考。其他的例子還包括用於可程式化金屬記憶胞(PMC)之固態電解質材料,或用於奈米離子記憶胞的材料,如銀摻雜之鍺硫化物解質或銅摻雜之鍺硫化物解質。此部分請參考N. E. Gilbert等人發表的文章”A macro model of programmable metallization cell devices”,Solid-State Electronics,49(2005),1813-1819,且其內容乃併入本文作為參考。
用以形成硫屬化物材料的例示方法係利用PVD濺鍍或磁控濺鍍方式,其反應氣體為氬氣、氮氣及/或氦氣,壓力為1mTorr至100mTorr。此沈積步驟一般係於室溫下進行。一長寬比為1~5之準直器可用以改良其填充表現。為了改善其填充表現,亦可使用數十至數百伏特之直流偏壓。另一方面,亦可同時合併使用直流偏壓以及準直器。
有時需要在真空中或氮氣環境中進行一沈積後退火處理,以改良硫屬化物材料之結晶態。此退火處理的溫度典型地係介於100℃至400℃,而退火時間則少於30分鐘。
第6-20圖依序為製造記憶胞陣列之各步驟。
第6A、6B圖分別為剖面圖與上視圖,其顯示形成基材200之第一步驟。基材200包括井202,其具有第一摻雜區205、第二摻雜區210以及介電溝渠230,且井202以垂直圖面的方向延伸。第一摻雜區205與第二摻雜區210可利用佈植法及活化退火的方式形成,該些方法均為具有通常知識者所熟知。於本實施例中,第一摻雜區205包括位於矽基材200內之N型材料摻雜區域,第二摻雜區210包括位於矽基材200內之濃摻雜N型(N+)材料區域。於另一實施例中,第一摻雜區205包括位於矽基材200內之P型材料摻雜區域,且第二摻雜區210包括位於矽基材200內之濃摻雜P型(P+)材料區域。
接著,進行離子佈植以於井202內第一摻雜區205形成字元線130,其中字元線130之導電性與第一摻雜區205及第二摻雜區210相異。此外,如本實施例所示,於基材內再進行第二次離子佈植,以形成由基材上表面延伸至第二摻雜區210之濃摻雜區域,以得到如第7A、7B圖所示之結構。於本實施例中,字元線130包括位於矽基材200內之P型材料摻雜區域,於其他實施例中,字元線130可包括位於矽基材200內之N型材料摻雜區域。
接著,介電質260乃形成於第7A、7B圖所示之結構上,以產生如第8A、8B圖所示之結構。於本實施例中,形成介電質260的步驟於基材200上沉積包括二氧化矽之層262、於層262上沉積包括氮化矽之層264以及於層264上沉積包括BPSG或PSG的層266,且在某些實施例中可以不需要層264。
接著,形成貫穿介電質260之開口900,以暴露出字元線130並形成第9A、9B圖所示之結構。欲形成開口900,可先利用層264作為蝕刻停止層來選擇性蝕刻層266,再選擇性蝕刻層264以露出層262,最後再利用如濕式蝕刻之方式蝕刻層262以露出字元線130。欲在操作過程中產生較大之電流,必須在字元線130與之後形成的經摻雜之多晶矽栓塞220之間形成未受損害的介面,因此,濕式蝕刻比較適合用來蝕刻層262,並避免損害到射極-基極間介面。此外,在其他實施例中,濕式蝕刻並不會移除全部的蝕刻層262。在字元線130與之後形成的經摻雜之多晶矽栓塞220之間形成品質較佳的介面,可以選擇性進行重新氧化步驟及/或高溫退火步驟。
接著,經摻雜之多晶矽栓塞220乃形成於開口900內,以產生如第10A、10B圖所示之結構。經摻雜之多晶矽栓塞220具有和字元線130不同之導電性,且其與對應之字元線130接觸於兩者間定義pn接面222。欲形成經摻雜之多晶矽栓塞220,可先對第9A、9B圖所示之結構進行沉積多晶矽材料,再進行如化學機械研磨CMP之平面化步驟。
之後,形成複數貫穿介電質260而與第二摻雜區210接觸之導電接觸窗215,以產生如第11A、11B圖所示之結構,而於本實施例中,導電接觸窗215包括鎢。
接著,導電覆蓋層240乃形成於經摻雜之多晶矽栓塞220上,如第12A、12B圖所示。導電覆蓋層240包括矽化物,且該矽化物可包含鈦、鎢、鈷、鎳、鉭,且不以此為限。於某實施例中,導電覆蓋層240包括鈷的矽化物(CoSi),且其形成方式是先沉積一層鈷,再進行快速熱處理製程(RTP),以使鈷與栓塞220的矽反應,而形成導電覆蓋層240。應了解的是,其他矽化物也可藉由沉積鈦、砷、經摻雜之鎳或其合金,並透過類似前述的方法形成。
接著形成介電質270,而產生如第13A、13B圖所示之結構。於本實施例中,介電質270包括氮化矽。
之後,形成貫穿介電質270的開口1400以暴露出導電覆蓋層240的上表面,並產生如第14A、14B圖所示之結構,且開口1400之寬度1410較佳係屬於次微影等級。於本實施例中,開口1400具有圓形剖面,所以寬度1410正好等於圓形剖面的直徑。然而,在其他實施例中,開口1400的剖面也可以是正方形、橢圓形、長方形或其他不規則形狀,端視形成開口1400的方法而定。
具有次微影等級寬度1410之開口1400可利用美國專利申請案第11/855979號所揭露之方法、材料、步驟,該申請案之發明名稱為”Phase Change Memory Cell in Via Array with Self-Aligned,Self-Converged Bottom Electrode and Method for Manufacturing”,申請日為2007年9月14日,其內容乃併入本文作參考。舉例來說,隔離層先形成於介電質270上,而犧牲層再形成於隔離層上。之後,在犧牲層上形成具有大小約略等於遮罩製程最小特徵尺寸之開口的遮罩,而該些開口正好覆蓋於開口1400上。之後以遮罩選擇性蝕刻隔離層與犧牲層,以於隔離層與犧牲層內形成通孔,並暴露出介電質270的上表面。於移除遮罩後,對通孔進行選擇性下切蝕刻,而在不影響犧牲層與介電質270的情形下蝕刻隔離層。之後,在通孔內形成填充材料。由於採用了選擇性下切蝕刻製程,通孔內的填充材料將會形成自我對準孔洞。接著,非等向性蝕刻填充材料以暴露出孔洞,並繼續蝕刻以使介電質270暴露於孔洞以下的區域,進而在各通孔內形成包括有填充材料之側壁間隔物。由於側壁間隔物具有大致由孔洞大小所決定的開口尺寸,因此其可小於微影製程的最小特徵尺寸。之後,以側壁間隔物為遮罩對介電質270進行蝕刻,以形成寬度1410小於最小特徵尺寸之開口1400。隔離層與犧牲層可利用如CMP之平面化製程移除,以產生如第14A、14B圖所示之結構。此外,隔離層與犧牲層也可在材料(如電極材料)形成於開口1400後再以平面化製程移除。
接著在開口1400內形成,以產生如第15A、15B圖所示之結構。於本實施例中,下電極250包括氮化鈦,且下電極250的形成是先將下電極材料以CVD沉積於第14A、14B圖所示之結構上,再進行如CMP之平面化步驟。於其他實施例中,如第14A、14B圖或第5A、5B圖所示者,可將相變化材料沉積於開口1400內。
之後,記憶元件125乃形成於下電極250之上,而上電極280乃形成於之上,以產生如第16A、16B圖所示之結構。欲形成記憶元件125與上電極280,可將一層記憶材料沉積於第15A、15B圖所示之結構上,再將一層上電極材料沉積於上,並將一層圖案化光阻形成於上電極材料層上,再蝕刻記憶材料層與上電極材料層。於此種實施例中,記憶元件與對應之上電極可形成多層堆疊。
於第14A、14B圖某些開口1400填充有記憶材料之實施例中,可以不需形成記憶材料層。
於本實施例中,記憶元件125與上電極280具有大致正方形的剖面。然而,在其他實施例中,記憶元件125與上電極280的剖面也可以是圓形、橢圓形、長方形或其他不規則形狀,端視形成記憶元件125與上電極280的方法而定。
之後,介電質295乃形成於第16A、16B圖所示之結構上,並形成暴露上電極280的開口1700與暴露接觸窗215的開口1750,以產生如第17A、17B圖所示之結構。
接著再將導電接觸窗217形成於開口1750內,並將導電接觸窗290形成於開口1700內,以產生如第18A、18B圖所示之結構。
之後再形成與參考電壓耦接之導電材料140及位元線120,以產生如第19A、19B圖所示之結構。
位元線120延伸至包括CMOS裝置之周邊電路2000,如第20A、20B圖所示。
第21-24圖為第7A-7B圖所示製造字元線130a步驟之另一實施例。
如第21A與21B圖所示,第6A-6B圖中介電溝渠230內的部分介電材料乃利用蝕刻方式移除,並暴露出介電溝渠230之間的井之第一摻雜區205的側壁表面2100。
接著在側壁表面2100上形成側壁導體510,以產生如第22A、22B圖所示之結構。側壁導體510包括矽化物,其包含鈦、鎢、鈷、鎳、鉭,但並不以此為限。於某實施例中,側壁導體510包括鈷的矽化物(CoSi),且其形成方式是先沉積一層鈷,再進行快速熱處理製程(RTP),以使鈷與第一摻雜區205的矽反應,而形成側壁導體510。應了解的是,其他矽化物也可藉由沉積鈦、砷、經摻雜之鎳或其合金,並透過類似前述的方法形成。
之後乃形成介電材料,以填充介電溝渠230,並產生如第23A、23B圖所示之結構。
接著,再進行離子佈植來植入摻雜物,以形成字元線130,並產生如第24A、24B圖所示之結構,其中字元線130之導電性與第一摻雜區205及第二摻雜區210相異。於本實施例中,字元線130包括基材200之經摻雜之P型材料。
第25圖係可應用本發明之積體電路2510之簡化方塊圖。積體電路2510內之記憶體陣列100的記憶胞具有多晶矽射極之雙極性接面電晶體。具有讀取、設置與重設功能之字元線解碼器2514係耦接至複數條字元線2516,其間並形成電性連接,且該字元線解碼器與驅動器2514係沿著記憶體陣列100之列排列。位元線(行)解碼器2518係耦接並電性連接至複數條沿著記憶體陣列100之行排列之位元線2520,以讀取、設置或重設陣列100內之相變化記憶胞(圖未示)。位址係透過匯流排2522提供至字元線解碼器與驅動器2514及位元線解碼器2518。方塊2524中的感應放大器與資料輸入結構包括讀取、設置與抹除模式之電壓及/或電流來源,係透過資料匯流排2526耦接至位元線解碼器2518。資料係由積體電路2510上的輸入/輸出埠或其他內部或外部之資料來源,透過資料輸入線2528傳送至方塊2524之資料輸入結構。積體電路2500亦可包括其他電路2530,如一般用途之處理器、特定用途的應用電路或是可提供此陣列100所支持之系統單晶片功能之複數模組的組合。資料係由方塊2524中的感應放大器,透過資料輸出線2532,傳送至積體電路2510上的輸入/輸出埠或其他積體電路2510內或外之資料目的地。
於本實施例中,控制器2534係以偏壓調整狀態機構來控制偏壓調整供應電壓、電流源2536,如讀取、程式化、抹除、抹除驗證及程式化驗證電壓及/或電流。此外,控制器2534亦可利用技術領域中已知的特殊目的邏輯電路來實作。於其他實施方式中,控制器2534可包括一般用途之處理器以執行電腦程式來控制元件的操作,而該處理器可以實作於相同的積體電路上。於另外的實施方式中,控制器2534可利用特殊目的邏輯電路與一般用途之處理器的組合來實作。
雖然本發明係已參照實施例來加以描述,然本發明創作並未受限於其詳細描述內容。替換方式及修改樣式係已於先前描述中所建議,且其他替換方式及修改樣式將為熟習此項技藝之人士所思及。特別是,所有具有實質上相同於本發明之構件結合而達成與本發明實質上相同結果者,皆不脫離本發明之精神範疇。因此,所有此等替換方式及修改樣式係意欲落在本發明於隨附申請專利範圍及其均等物所界定的範疇之中。
100...記憶胞陣列
110...記憶胞
115...雙極性接面電晶體
120、120a、120b、120c、120d、2520...位元線
125...記憶元件
126、400...記憶元件厚度
127...記憶元件寬度
128...主動區域
130、130a、130b、130c、130d、2516...字元線
140...導電材料
150、2514...字元線解碼器與驅動器
160、2518...位元線解碼器
165...感應放大器
200...基材
202...井
205...第一摻雜區
210...第二摻雜區
215、217、290...導電接觸窗
220...摻雜多晶矽栓塞
222...pn接面
230...介電溝渠
240...導電覆蓋層
250...下電極
252...下電極寬度
260、270、295...介電質
262...二氧化矽層
264...氮化矽層
266...BPSG或PSG層
280...上電極
300...第一部分寬度
323...第一部分
324...第二部分
510...側壁導體
900、1400...介電質開口
1410...開口寬度
1700...上電極開口
1750...接觸窗開口
2000...周邊電路
2100...側壁表面
2510...積體電路
2522、2526...匯流排
2524...感應放大器與資料輸入結構
2528...資料輸入線
2530...其他電路
2532...資料輸出線
2534...控制器
2536...偏壓調整供應電壓與電流來源
第1圖係部分記憶胞陣列之示意圖,其中記憶胞包括具有多晶矽射極之雙極性接面電晶體。
第2A-2B圖為陣列中第一實施例之記憶胞部分剖面圖。
第2C圖為陣列中第一實施例之記憶胞之上視圖。
第3A-3B圖為陣列中第二實施例之記憶胞部分剖面圖。
第4A-4B圖為陣列中第三實施例之記憶胞部分剖面圖。
第5A-5B圖為陣列中第四實施例之記憶胞部分剖面圖。
第6-20圖依序為製造記憶胞陣列之各步驟。
第21-24圖為第7A-7B圖所示製造字元線步驟之另一實施例。
第25圖為積體電路之簡化方塊圖,該積體電路之記憶胞陣列內之記憶胞包括前述具有多晶矽射極之雙極性接面電晶體。
100...記憶胞陣列
110...記憶胞
115...雙極性接面電晶體
120b...位元線
125...記憶元件
126...記憶元件厚度
127...記憶元件寬度
128...主動區域
130a~130d...字元線
140...導電材料
200...基材
202...井
205...第一摻雜區
210...第二摻雜區
215、217、290...導電接觸窗
220...摻雜多晶矽栓塞
222...pn接面
240...導電覆蓋層
250...下電極
252...下電極寬度
260、270、295...介電質
262...二氧化矽層
264...氮化矽層
266...BPSG或PSG層
280...上電極
Claims (26)
- 一種記憶裝置,包括:一單晶半導體基材,具有一第一導電性;複數條字元線,位於該單晶半導體基材內,具有一與該第一導電性相異之第二導電性;複數個記憶胞,每個記憶胞包括雙極性接面電晶體與記憶元件,該雙極性接面電晶體係以共集極組態方式耦接,且該雙極性接面電晶體包括:一射極,包括具有該第一導電性之摻雜多晶矽,該射極與一條對應字元線連接以定義出一pn接面;一基極,係利用位於該射極下方的該條對應字元線一部分所形成;以及一集極,包括位於該基極下方的該單晶半導體基材一部分。
- 如申請專利範圍第1項所述之記憶裝置,其中該單晶半導體基材包括一第一摻雜區與一位於該第一摻雜區下方之第二摻雜區,該第二摻雜區的摻雜濃度係較該第一摻雜區更高。
- 如申請專利範圍第1項所述之記憶裝置,更包括導電接觸窗,該導電接觸窗與該單晶半導體基材接觸,並耦接至一參考電壓。
- 如申請專利範圍第1項所述之記憶裝置,更包括具有矽化物之側壁導體,該側壁導體係位於該些字元線之側壁表面上。
- 如申請專利範圍第1項所述之記憶裝置,其中,該單晶半導體基材包括n型摻雜之半導體材料;該些字元線包括p型摻雜之半導體材料;且每個記憶胞之射極包括n型摻雜之多晶矽。
- 如申請專利範圍第1項所述之記憶裝置,其中,該單晶半導體基材包括p型摻雜之半導體材料;該些字元線包括n型摻雜之半導體材料;且每個記憶胞之射極包括p型摻雜之多晶矽。
- 如申請專利範圍第1項所述之記憶裝置,其中該記憶胞更包括:一導電覆蓋層,包括矽化物,位於對應之雙極性接面電晶體上;一下電極,位於該導電覆蓋層與該記憶元件之間,該下電極之寬度係小於該記憶元件之寬度;以及一上電極,位於該記憶元件之上。
- 如申請專利範圍第1項所述之記憶裝置,其中該記憶胞更包括:一導電覆蓋層,包括矽化物,位於對應之雙極性接面電晶體上;以及一上電極,透過該記憶元件與該導電覆蓋層電性耦接。
- 如申請專利範圍第8項所述之記憶裝置,其中該記憶元件包括一記憶材料柱,該記憶材料柱係由一介電質所環繞,且該記憶材料柱之寬度係小於該導電覆蓋層與該上電極之寬度。
- 如申請專利範圍第8項所述之記憶裝置,其中該記憶元件包括:一第一部分,位於該導電覆蓋層之上,且由一介電質所環繞;一第二部分,位於該第一部分之上,其中該第一部分之寬度係小於該第二部分、該導電覆蓋層以及該上電極之寬度。
- 一種製造一記憶裝置之方法,包括:形成一具有一第一導電性之單晶半導體基材;於該單晶半導體基材內形成複數條字元線,該些字元線具有一與該第一導電性相異之第二導電性;形成複數個記憶胞,並使各記憶胞包括雙極性接面電晶體與記憶元件,該雙極性接面電晶體係以共集組態方式耦接,且該雙極性接面電晶體包括:一射極,包括具有該第一導電性之經摻雜多晶矽,該射極與一條對應字元線接觸以定義一pn接面;一基極,係利用位於該射極下方的該條對應字元線一部分所形成;以及一集極,包括位於該基極下方的該單晶半導體基材一部分。
- 如申請專利範圍第11所述之方法,其中該單晶半導體基材包括一第一摻雜區與一位於該第一摻雜區下方之第二摻雜區,該第二摻雜區的摻雜濃度係較該第一摻雜區更高。
- 如申請專利範圍第11所述之方法,更包括形成導電接觸窗,該導電接觸窗與該單晶半導體基材接觸,並耦接至一參考電壓。
- 如申請專利範圍第11所述之方法,更包括形成具有矽化物之側壁導體,該側壁導體係位於該些字元線之側壁表面上。
- 如申請專利範圍第11所述之方法,其中,該單晶半導體基材包括n型摻雜之半導體材料;該些字元線包括p型摻雜之半導體材料;且每個記憶胞之射極包括n型摻雜之多晶矽。
- 如申請專利範圍第11所述之方法,其中,該單晶半導體基材包括p型摻雜之半導體材料;該些字元線包括n型摻雜之半導體材料;且每個記憶胞之射極包括p型摻雜之多晶矽。
- 如申請專利範圍第11所述之方法,其中該形成複數個記憶胞之步驟更包括:形成一導電覆蓋層,包括矽化物,該導電覆蓋層位於對應之雙極性接面電晶體上;形成一下電極,該下電極位於該導電覆蓋層與該記憶元件之間,且該下電極之寬度係小於該記憶元件之寬度;以及形成一上電極,該上電極位於該記憶元件上。
- 如申請專利範圍第11所述之方法,其中該形成複數個記憶胞之步驟更包括:形成一導電覆蓋層,包括矽化物,該導電覆蓋層位於對應之雙極性接面電晶體上;以及形成一上電極,該上電極透過該記憶元件與該導電覆蓋層電性耦接。
- 如申請專利範圍第18所述之方法,其中該記憶元件包括一記憶材料柱,該記憶材料柱係由一介電質所環繞,且該記憶材料柱之寬度係小於該導電覆蓋層與該上電極之寬度。
- 如申請專利範圍第18所述之方法,其中該記憶元件包括:一第一部分,位於該導電覆蓋層上,且由一介電質所環繞;一第二部分,位於該第一部分上,其中該第一部分之寬度係小於該第二部分、該導電覆蓋層以及該上電極之寬度。
- 一種製造一記憶裝置之方法,包括:形成一具有一第一導電性之單晶半導體基材;於該單晶半導體基材內形成複數介電溝渠;於該單晶半導體基材內形成複數條字元線,該些字元線具有一與該第一導電性相異之第二導電性,且相鄰之字元線係由該介電溝渠所分隔;形成複數經摻雜之多晶矽栓塞,其具有該第一導電性,且與該些字元線接觸;形成複數記憶元件,其電性耦接至該經摻雜之多晶矽栓塞;於該記憶元件上形成上電極;於上電極之上形成複數條位元線,該些位元線耦接至該上電極。
- 如申請專利範圍第21所述之方法,其中該形成單晶半導體基材與該形成複數條字元線之步驟包括:形成該單晶半導體基材;於該單晶半導體基材內形成該介電溝渠;由該介電溝渠移除一部分材料,以暴露該單晶半導體基材之側壁表面;於該單晶半導體基材之側壁表面上形成側壁導體,該側壁導體包括矽化物;以介電材料填充該介電溝渠;以及佈植雜質於該介電溝渠之間的該單晶半導體基材內,以形成該些字元線。
- 如申請專利範圍第21所述之方法,其中該形成複數經摻雜之多晶矽栓塞之步驟包括:於該單晶半導體基材上形成介電質,並形成複數貫穿該介電質之開口以暴露該些字元線;以及於該開口內形成經摻雜之多晶矽栓塞。
- 如申請專利範圍第21所述之方法,其中該形成複數記憶元件以及該形成上電極之步驟包括:於該經摻雜之多晶矽栓塞之上形成導電覆蓋層,該導電覆蓋層包括矽化物;於該導電覆蓋層之上形成下電極,該下電極之寬度小於該導電覆蓋層之寬度;於該下電極之上形成一層記憶材料,並於該層記憶材料之上形成一層上電極材料;以及圖案化該層記憶材料與該層上電極材料。
- 如申請專利範圍第24所述之方法,其中該於該導電覆蓋層之上形成下電極之步驟包括:於該導電覆蓋層之上形成一介電層;形成貫穿該介電層之開口以暴露該導電覆蓋層之上表面;以及於該開口內形成該下電極。
- 如申請專利範圍第21所述之方法,其中該形成複數記憶元件與該形成上電極之步驟包括:於該經摻雜之多晶矽栓塞之上形成導電覆蓋層,該導電覆蓋層包括矽化物;形成與該導電覆蓋層接觸之該記憶元件;以及於該記憶元件之上形成該上電極。
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US12/353,219 US8030635B2 (en) | 2009-01-13 | 2009-01-13 | Polysilicon plug bipolar transistor for phase change memory |
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Country Status (3)
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Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101510776B1 (ko) * | 2009-01-05 | 2015-04-10 | 삼성전자주식회사 | 반도체 상변화 메모리 소자 |
TWI416697B (zh) * | 2009-10-21 | 2013-11-21 | Silicon Motion Inc | 靜電放電保護裝置 |
KR101781624B1 (ko) * | 2010-12-08 | 2017-09-25 | 삼성전자주식회사 | 가변 저항 메모리 소자 및 그 제조 방법 |
US8912517B2 (en) | 2012-09-24 | 2014-12-16 | Adesto Technologies Corporation | Resistive switching memory |
US9231205B2 (en) * | 2013-03-13 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low form voltage resistive random access memory (RRAM) |
WO2016195664A1 (en) * | 2015-06-02 | 2016-12-08 | Intel Corporation | High density memory architecture using back side metal layers |
CN107154458B (zh) * | 2016-03-04 | 2019-07-26 | 华邦电子股份有限公司 | 电阻式随机存取存储器结构及其制造方法 |
US10706921B2 (en) | 2016-04-01 | 2020-07-07 | Intel Corporation | Integrated 1T1R RRAM memory cell |
US9659998B1 (en) | 2016-06-07 | 2017-05-23 | Macronix International Co., Ltd. | Memory having an interlayer insulating structure with different thermal resistance |
CN107591335A (zh) * | 2016-07-08 | 2018-01-16 | 北大方正集团有限公司 | 电连接结构的制备方法和集成电路芯片 |
US10833267B2 (en) * | 2018-10-26 | 2020-11-10 | International Business Machines Corporation | Structure and method to form phase change memory cell with self- align top electrode contact |
US11107979B2 (en) * | 2018-12-28 | 2021-08-31 | Spin Memory, Inc. | Patterned silicide structures and methods of manufacture |
US11171177B2 (en) * | 2019-01-09 | 2021-11-09 | Intel Corporation | Phase change memory devices with enhanced vias |
US10658583B1 (en) * | 2019-05-29 | 2020-05-19 | International Business Machines Corporation | Forming RRAM cell structure with filament confinement |
US11957069B2 (en) | 2021-10-22 | 2024-04-09 | International Business Machines Corporation | Contact resistance of a metal liner in a phase change memory cell |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200532693A (en) * | 2003-12-05 | 2005-10-01 | Renesas Tech Corp | Semiconductor integrated circuit device |
US20080311722A1 (en) * | 2007-06-15 | 2008-12-18 | Sandisk 3D Llc | Method for forming polycrystalline thin film bipolar transistors |
Family Cites Families (315)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US648710A (en) * | 1899-10-10 | 1900-05-01 | George C Quelch | Fuse-block. |
US3271591A (en) | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3530441A (en) | 1969-01-15 | 1970-09-22 | Energy Conversion Devices Inc | Method and apparatus for storing and retrieving information |
IL61678A (en) | 1979-12-13 | 1984-04-30 | Energy Conversion Devices Inc | Programmable cell and programmable electronic arrays comprising such cells |
US4452592A (en) | 1982-06-01 | 1984-06-05 | General Motors Corporation | Cyclic phase change coupling |
JPS60137070A (ja) | 1983-12-26 | 1985-07-20 | Toshiba Corp | 半導体装置の製造方法 |
US4719594A (en) * | 1984-11-01 | 1988-01-12 | Energy Conversion Devices, Inc. | Grooved optical data storage device including a chalcogenide memory layer |
US4876220A (en) | 1986-05-16 | 1989-10-24 | Actel Corporation | Method of making programmable low impedance interconnect diode element |
JP2685770B2 (ja) | 1987-12-28 | 1997-12-03 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2606857B2 (ja) * | 1987-12-10 | 1997-05-07 | 株式会社日立製作所 | 半導体記憶装置の製造方法 |
US5166758A (en) | 1991-01-18 | 1992-11-24 | Energy Conversion Devices, Inc. | Electrically erasable phase change memory |
US5534712A (en) | 1991-01-18 | 1996-07-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements characterized by reduced current and improved thermal stability |
US5177567A (en) * | 1991-07-19 | 1993-01-05 | Energy Conversion Devices, Inc. | Thin-film structure for chalcogenide electrical switching devices and process therefor |
JP2825031B2 (ja) | 1991-08-06 | 1998-11-18 | 日本電気株式会社 | 半導体メモリ装置 |
US5166096A (en) | 1991-10-29 | 1992-11-24 | International Business Machines Corporation | Process for fabricating self-aligned contact studs for semiconductor structures |
JPH05206394A (ja) | 1992-01-24 | 1993-08-13 | Mitsubishi Electric Corp | 電界効果トランジスタおよびその製造方法 |
US5958358A (en) | 1992-07-08 | 1999-09-28 | Yeda Research And Development Co., Ltd. | Oriented polycrystalline thin films of transition metal chalcogenides |
JP2884962B2 (ja) * | 1992-10-30 | 1999-04-19 | 日本電気株式会社 | 半導体メモリ |
US5515488A (en) * | 1994-08-30 | 1996-05-07 | Xerox Corporation | Method and apparatus for concurrent graphical visualization of a database search and its search history |
US5785828A (en) | 1994-12-13 | 1998-07-28 | Ricoh Company, Ltd. | Sputtering target for producing optical recording medium |
US5869843A (en) * | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
US5879955A (en) | 1995-06-07 | 1999-03-09 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US5831276A (en) | 1995-06-07 | 1998-11-03 | Micron Technology, Inc. | Three-dimensional container diode for use with multi-state material in a non-volatile memory cell |
US6420725B1 (en) * | 1995-06-07 | 2002-07-16 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
JP3363154B2 (ja) | 1995-06-07 | 2003-01-08 | ミクロン テクノロジー、インコーポレイテッド | 不揮発性メモリセル内のマルチステート材料と共に使用するスタック/トレンチダイオード |
US5789758A (en) | 1995-06-07 | 1998-08-04 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US5837564A (en) | 1995-11-01 | 1998-11-17 | Micron Technology, Inc. | Method for optimal crystallization to obtain high electrical performance from chalcogenides |
KR0182866B1 (ko) * | 1995-12-27 | 1999-04-15 | 김주용 | 플래쉬 메모리 장치 |
US5687112A (en) | 1996-04-19 | 1997-11-11 | Energy Conversion Devices, Inc. | Multibit single cell memory element having tapered contact |
US6025220A (en) | 1996-06-18 | 2000-02-15 | Micron Technology, Inc. | Method of forming a polysilicon diode and devices incorporating such diode |
US5866928A (en) | 1996-07-16 | 1999-02-02 | Micron Technology, Inc. | Single digit line with cell contact interconnect |
US5789277A (en) | 1996-07-22 | 1998-08-04 | Micron Technology, Inc. | Method of making chalogenide memory device |
US5814527A (en) | 1996-07-22 | 1998-09-29 | Micron Technology, Inc. | Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories |
US6337266B1 (en) * | 1996-07-22 | 2002-01-08 | Micron Technology, Inc. | Small electrode for chalcogenide memories |
US5985698A (en) | 1996-07-22 | 1999-11-16 | Micron Technology, Inc. | Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell |
US5998244A (en) | 1996-08-22 | 1999-12-07 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
US5688713A (en) | 1996-08-26 | 1997-11-18 | Vanguard International Semiconductor Corporation | Method of manufacturing a DRAM cell having a double-crown capacitor using polysilicon and nitride spacers |
US6147395A (en) | 1996-10-02 | 2000-11-14 | Micron Technology, Inc. | Method for fabricating a small area of contact between electrodes |
US6087674A (en) | 1996-10-28 | 2000-07-11 | Energy Conversion Devices, Inc. | Memory element with memory material comprising phase-change material and dielectric material |
US5716883A (en) * | 1996-11-06 | 1998-02-10 | Vanguard International Semiconductor Corporation | Method of making increased surface area, storage node electrode, with narrow spaces between polysilicon columns |
US6015977A (en) | 1997-01-28 | 2000-01-18 | Micron Technology, Inc. | Integrated circuit memory cell having a small active area and method of forming same |
US5952671A (en) | 1997-05-09 | 1999-09-14 | Micron Technology, Inc. | Small electrode for a chalcogenide switching device and method for fabricating same |
US6031287A (en) * | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US5933365A (en) | 1997-06-19 | 1999-08-03 | Energy Conversion Devices, Inc. | Memory element with energy control mechanism |
US5902704A (en) | 1997-07-02 | 1999-05-11 | Lsi Logic Corporation | Process for forming photoresist mask over integrated circuit structures with critical dimension control |
US6768165B1 (en) * | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US7023009B2 (en) * | 1997-10-01 | 2006-04-04 | Ovonyx, Inc. | Electrically programmable memory element with improved contacts |
US6969866B1 (en) | 1997-10-01 | 2005-11-29 | Ovonyx, Inc. | Electrically programmable memory element with improved contacts |
US6617192B1 (en) | 1997-10-01 | 2003-09-09 | Ovonyx, Inc. | Electrically programmable memory element with multi-regioned contact |
FR2774209B1 (fr) * | 1998-01-23 | 2001-09-14 | St Microelectronics Sa | Procede de controle du circuit de lecture d'un plan memoire et dispositif de memoire correspondant |
US6087269A (en) | 1998-04-20 | 2000-07-11 | Advanced Micro Devices, Inc. | Method of making an interconnect using a tungsten hard mask |
US6091094A (en) * | 1998-06-11 | 2000-07-18 | Siemens Aktiengesellschaft | Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips |
US6372651B1 (en) * | 1998-07-17 | 2002-04-16 | Advanced Micro Devices, Inc. | Method for trimming a photoresist pattern line for memory gate etching |
US6141260A (en) * | 1998-08-27 | 2000-10-31 | Micron Technology, Inc. | Single electron resistor memory device and method for use thereof |
US6351406B1 (en) * | 1998-11-16 | 2002-02-26 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6483736B2 (en) | 1998-11-16 | 2002-11-19 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6034882A (en) * | 1998-11-16 | 2000-03-07 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
JP2000164830A (ja) * | 1998-11-27 | 2000-06-16 | Mitsubishi Electric Corp | 半導体記憶装置の製造方法 |
US6487106B1 (en) | 1999-01-12 | 2002-11-26 | Arizona Board Of Regents | Programmable microelectronic devices and method of forming and programming same |
US6291137B1 (en) | 1999-01-20 | 2001-09-18 | Advanced Micro Devices, Inc. | Sidewall formation for sidewall patterning of sub 100 nm structures |
US6245669B1 (en) | 1999-02-05 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | High selectivity Si-rich SiON etch-stop layer |
US6750079B2 (en) | 1999-03-25 | 2004-06-15 | Ovonyx, Inc. | Method for making programmable resistance memory element |
KR100441692B1 (ko) | 1999-03-25 | 2004-07-27 | 오보닉스, 아이엔씨. | 개선된 접점을 갖는 전기적으로 프로그램가능한 메모리 소자 |
US6943365B2 (en) | 1999-03-25 | 2005-09-13 | Ovonyx, Inc. | Electrically programmable memory element with reduced area of contact and method for making same |
US6177317B1 (en) * | 1999-04-14 | 2001-01-23 | Macronix International Co., Ltd. | Method of making nonvolatile memory devices having reduced resistance diffusion regions |
US6075719A (en) | 1999-06-22 | 2000-06-13 | Energy Conversion Devices, Inc. | Method of programming phase-change memory element |
US6077674A (en) | 1999-10-27 | 2000-06-20 | Agilent Technologies Inc. | Method of producing oligonucleotide arrays with features of high purity |
US6326307B1 (en) | 1999-11-15 | 2001-12-04 | Appllied Materials, Inc. | Plasma pretreatment of photoresist in an oxide etch process |
US6314014B1 (en) | 1999-12-16 | 2001-11-06 | Ovonyx, Inc. | Programmable resistance memory arrays with reference cells |
US6576546B2 (en) | 1999-12-22 | 2003-06-10 | Texas Instruments Incorporated | Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications |
TW586154B (en) * | 2001-01-05 | 2004-05-01 | Macronix Int Co Ltd | Planarization method for semiconductor device |
US6927411B2 (en) * | 2000-02-11 | 2005-08-09 | Axon Technologies Corporation | Programmable structure, an array including the structure, and methods of forming the same |
GB0003302D0 (en) | 2000-02-15 | 2000-04-05 | Koninkl Philips Electronics Nv | Semiconductor devices |
US6444557B1 (en) * | 2000-03-14 | 2002-09-03 | International Business Machines Corporation | Method of forming a damascene structure using a sacrificial conductive layer |
US6420216B1 (en) | 2000-03-14 | 2002-07-16 | International Business Machines Corporation | Fuse processing using dielectric planarization pillars |
US6420215B1 (en) | 2000-04-28 | 2002-07-16 | Matrix Semiconductor, Inc. | Three-dimensional memory array and method of fabrication |
US6888750B2 (en) | 2000-04-28 | 2005-05-03 | Matrix Semiconductor, Inc. | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication |
US6501111B1 (en) | 2000-06-30 | 2002-12-31 | Intel Corporation | Three-dimensional (3D) programmable device |
US6563156B2 (en) | 2001-03-15 | 2003-05-13 | Micron Technology, Inc. | Memory elements and methods for making same |
US6440837B1 (en) | 2000-07-14 | 2002-08-27 | Micron Technology, Inc. | Method of forming a contact structure in a semiconductor device |
US6512263B1 (en) * | 2000-09-22 | 2003-01-28 | Sandisk Corporation | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming |
US6339544B1 (en) | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
US6429064B1 (en) | 2000-09-29 | 2002-08-06 | Intel Corporation | Reduced contact area of sidewall conductor |
US6555860B2 (en) * | 2000-09-29 | 2003-04-29 | Intel Corporation | Compositionally modified resistive electrode |
US6567293B1 (en) | 2000-09-29 | 2003-05-20 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
KR100382729B1 (ko) | 2000-12-09 | 2003-05-09 | 삼성전자주식회사 | 반도체 소자의 금속 컨택 구조체 및 그 형성방법 |
US20020074658A1 (en) | 2000-12-20 | 2002-06-20 | Chien Chiang | High-resistivity metal in a phase-change memory cell |
US6569705B2 (en) | 2000-12-21 | 2003-05-27 | Intel Corporation | Metal structure for a phase-change memory device |
TW490675B (en) | 2000-12-22 | 2002-06-11 | Macronix Int Co Ltd | Control method of multi-stated NROM |
US6271090B1 (en) | 2000-12-22 | 2001-08-07 | Macronix International Co., Ltd. | Method for manufacturing flash memory device with dual floating gates and two bits per cell |
US6627530B2 (en) | 2000-12-22 | 2003-09-30 | Matrix Semiconductor, Inc. | Patterning three dimensional structures |
US6534781B2 (en) * | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
KR100625129B1 (ko) | 2001-01-30 | 2006-09-18 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 집적 회로 장치의 제조 방법 |
KR100400037B1 (ko) | 2001-02-22 | 2003-09-29 | 삼성전자주식회사 | 콘택 플러그를 구비하는 반도체 소자 및 그의 제조 방법 |
US6487114B2 (en) | 2001-02-28 | 2002-11-26 | Macronix International Co., Ltd. | Method of reading two-bit memories of NROM cell |
US6473332B1 (en) | 2001-04-04 | 2002-10-29 | The University Of Houston System | Electrically variable multi-state resistance computing |
US6596589B2 (en) | 2001-04-30 | 2003-07-22 | Vanguard International Semiconductor Corporation | Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer |
US6730928B2 (en) | 2001-05-09 | 2004-05-04 | Science Applications International Corporation | Phase change switches and circuits coupling to electromagnetic waves containing phase change switches |
US6514788B2 (en) * | 2001-05-29 | 2003-02-04 | Bae Systems Information And Electronic Systems Integration Inc. | Method for manufacturing contacts for a Chalcogenide memory device |
DE10128482A1 (de) * | 2001-06-12 | 2003-01-02 | Infineon Technologies Ag | Halbleiterspeichereinrichtung sowie Verfahren zu deren Herstellung |
US6613604B2 (en) | 2001-08-02 | 2003-09-02 | Ovonyx, Inc. | Method for making small pore for use in programmable resistance memory element |
US6774387B2 (en) | 2001-06-26 | 2004-08-10 | Ovonyx, Inc. | Programmable resistance memory element |
US6589714B2 (en) | 2001-06-26 | 2003-07-08 | Ovonyx, Inc. | Method for making programmable resistance memory element using silylated photoresist |
US6605527B2 (en) | 2001-06-30 | 2003-08-12 | Intel Corporation | Reduced area intersection between electrode and programming element |
US6673700B2 (en) * | 2001-06-30 | 2004-01-06 | Ovonyx, Inc. | Reduced area intersection between electrode and programming element |
US6511867B2 (en) * | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Utilizing atomic layer deposition for programmable device |
US6643165B2 (en) * | 2001-07-25 | 2003-11-04 | Nantero, Inc. | Electromechanical memory having cell selection circuitry constructed with nanotube technology |
US6737312B2 (en) | 2001-08-27 | 2004-05-18 | Micron Technology, Inc. | Method of fabricating dual PCRAM cells sharing a common electrode |
US6709958B2 (en) | 2001-08-30 | 2004-03-23 | Micron Technology, Inc. | Integrated circuit device and fabrication using metal-doped chalcogenide materials |
US6507061B1 (en) * | 2001-08-31 | 2003-01-14 | Intel Corporation | Multiple layer phase-change memory |
US6586761B2 (en) | 2001-09-07 | 2003-07-01 | Intel Corporation | Phase change material memory device |
US6861267B2 (en) * | 2001-09-17 | 2005-03-01 | Intel Corporation | Reducing shunts in memories with phase-change material |
US7045383B2 (en) | 2001-09-19 | 2006-05-16 | BAE Systems Information and Ovonyx, Inc | Method for making tapered opening for programmable resistance memory element |
US6800563B2 (en) | 2001-10-11 | 2004-10-05 | Ovonyx, Inc. | Forming tapered lower electrode phase-change memories |
US6566700B2 (en) | 2001-10-11 | 2003-05-20 | Ovonyx, Inc. | Carbon-containing interfacial layer for phase-change memory |
US6791859B2 (en) | 2001-11-20 | 2004-09-14 | Micron Technology, Inc. | Complementary bit PCRAM sense amplifier and method of operation |
US6545903B1 (en) * | 2001-12-17 | 2003-04-08 | Texas Instruments Incorporated | Self-aligned resistive plugs for forming memory cell with phase change material |
US6512241B1 (en) * | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
US6867638B2 (en) * | 2002-01-10 | 2005-03-15 | Silicon Storage Technology, Inc. | High voltage generation and regulation system for digital multilevel nonvolatile memory |
JP3948292B2 (ja) | 2002-02-01 | 2007-07-25 | 株式会社日立製作所 | 半導体記憶装置及びその製造方法 |
US7116593B2 (en) | 2002-02-01 | 2006-10-03 | Hitachi, Ltd. | Storage device |
US7151273B2 (en) | 2002-02-20 | 2006-12-19 | Micron Technology, Inc. | Silver-selenide/chalcogenide glass stack for resistance variable memory |
US6972430B2 (en) | 2002-02-20 | 2005-12-06 | Stmicroelectronics S.R.L. | Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof |
US7122281B2 (en) | 2002-02-26 | 2006-10-17 | Synopsys, Inc. | Critical dimension control using full phase and trim masks |
JP3796457B2 (ja) | 2002-02-28 | 2006-07-12 | 富士通株式会社 | 不揮発性半導体記憶装置 |
US6579760B1 (en) | 2002-03-28 | 2003-06-17 | Macronix International Co., Ltd. | Self-aligned, programmable phase change memory |
US7623370B2 (en) | 2002-04-04 | 2009-11-24 | Kabushiki Kaisha Toshiba | Resistance change memory device |
CN1639868A (zh) | 2002-04-09 | 2005-07-13 | 松下电器产业株式会社 | 非易失性存储器及其制造方法 |
US6864500B2 (en) * | 2002-04-10 | 2005-03-08 | Micron Technology, Inc. | Programmable conductor memory cell structure |
US6605821B1 (en) | 2002-05-10 | 2003-08-12 | Hewlett-Packard Development Company, L.P. | Phase change material electronic memory structure and method for forming |
US6864503B2 (en) | 2002-08-09 | 2005-03-08 | Macronix International Co., Ltd. | Spacer chalcogenide memory method and device |
US6850432B2 (en) * | 2002-08-20 | 2005-02-01 | Macronix International Co., Ltd. | Laser programmable electrically readable phase-change memory method and device |
JP4190238B2 (ja) * | 2002-09-13 | 2008-12-03 | 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置 |
KR20050053750A (ko) | 2002-10-11 | 2005-06-08 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 상변환 물질을 포함하는 전기 장치 |
US6992932B2 (en) * | 2002-10-29 | 2006-01-31 | Saifun Semiconductors Ltd | Method circuit and system for read error detection in a non-volatile memory array |
JP4928045B2 (ja) * | 2002-10-31 | 2012-05-09 | 大日本印刷株式会社 | 相変化型メモリ素子およびその製造方法 |
US6940744B2 (en) | 2002-10-31 | 2005-09-06 | Unity Semiconductor Corporation | Adaptive programming technique for a re-writable conductive memory device |
US7589343B2 (en) | 2002-12-13 | 2009-09-15 | Intel Corporation | Memory and access device and method therefor |
US6791102B2 (en) | 2002-12-13 | 2004-09-14 | Intel Corporation | Phase change memory |
US6744088B1 (en) | 2002-12-13 | 2004-06-01 | Intel Corporation | Phase change memory device on a planar composite layer |
US6815266B2 (en) | 2002-12-30 | 2004-11-09 | Bae Systems Information And Electronic Systems Integration, Inc. | Method for manufacturing sidewall contacts for a chalcogenide memory device |
EP1439583B1 (en) | 2003-01-15 | 2013-04-10 | STMicroelectronics Srl | Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof |
KR100476690B1 (ko) | 2003-01-17 | 2005-03-18 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
US7277317B2 (en) | 2003-01-31 | 2007-10-02 | Nxp B.V. | MRAM architecture for low power consumption and high selectivity |
US7115927B2 (en) | 2003-02-24 | 2006-10-03 | Samsung Electronics Co., Ltd. | Phase changeable memory devices |
KR100486306B1 (ko) | 2003-02-24 | 2005-04-29 | 삼성전자주식회사 | 셀프 히터 구조를 가지는 상변화 메모리 소자 |
US7323734B2 (en) * | 2003-02-25 | 2008-01-29 | Samsung Electronics Co., Ltd. | Phase changeable memory cells |
US6936544B2 (en) | 2003-03-11 | 2005-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of removing metal etching residues following a metal etchback process to improve a CMP process |
US7400522B2 (en) | 2003-03-18 | 2008-07-15 | Kabushiki Kaisha Toshiba | Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation |
KR100504698B1 (ko) | 2003-04-02 | 2005-08-02 | 삼성전자주식회사 | 상변화 기억 소자 및 그 형성 방법 |
KR100979710B1 (ko) * | 2003-05-23 | 2010-09-02 | 삼성전자주식회사 | 반도체 메모리 소자 및 제조방법 |
US20060006472A1 (en) * | 2003-06-03 | 2006-01-12 | Hai Jiang | Phase change memory with extra-small resistors |
US7067865B2 (en) | 2003-06-06 | 2006-06-27 | Macronix International Co., Ltd. | High density chalcogenide memory cells |
US6838692B1 (en) * | 2003-06-23 | 2005-01-04 | Macronix International Co., Ltd. | Chalcogenide memory device with multiple bits per cell |
US20050018526A1 (en) * | 2003-07-21 | 2005-01-27 | Heon Lee | Phase-change memory device and manufacturing method thereof |
US7132350B2 (en) * | 2003-07-21 | 2006-11-07 | Macronix International Co., Ltd. | Method for manufacturing a programmable eraseless memory |
KR100615586B1 (ko) * | 2003-07-23 | 2006-08-25 | 삼성전자주식회사 | 다공성 유전막 내에 국부적인 상전이 영역을 구비하는상전이 메모리 소자 및 그 제조 방법 |
US7893419B2 (en) * | 2003-08-04 | 2011-02-22 | Intel Corporation | Processing phase change material to improve programming speed |
DE102004039977B4 (de) | 2003-08-13 | 2008-09-11 | Samsung Electronics Co., Ltd., Suwon | Programmierverfahren und Treiberschaltung für eine Phasenwechselspeicherzelle |
US6815704B1 (en) | 2003-09-04 | 2004-11-09 | Silicon Storage Technology, Inc. | Phase change memory device employing thermally insulating voids |
US6927410B2 (en) | 2003-09-04 | 2005-08-09 | Silicon Storage Technology, Inc. | Memory device with discrete layers of phase change memory material |
KR100505709B1 (ko) * | 2003-09-08 | 2005-08-03 | 삼성전자주식회사 | 상 변화 메모리 장치의 파이어링 방법 및 효율적인파이어링을 수행할 수 있는 상 변화 메모리 장치 |
US20050062087A1 (en) * | 2003-09-19 | 2005-03-24 | Yi-Chou Chen | Chalcogenide phase-change non-volatile memory, memory device and method for fabricating the same |
DE10345455A1 (de) | 2003-09-30 | 2005-05-04 | Infineon Technologies Ag | Verfahren zum Erzeugen einer Hartmaske und Hartmasken-Anordnung |
US6910907B2 (en) | 2003-11-18 | 2005-06-28 | Agere Systems Inc. | Contact for use in an integrated circuit and a method of manufacture therefor |
US7485891B2 (en) * | 2003-11-20 | 2009-02-03 | International Business Machines Corporation | Multi-bit phase change memory cell and multi-bit phase change memory including the same, method of forming a multi-bit phase change memory, and method of programming a multi-bit phase change memory |
KR100568109B1 (ko) | 2003-11-24 | 2006-04-05 | 삼성전자주식회사 | 상변화 기억 소자 및 그 형성 방법 |
KR100558548B1 (ko) | 2003-11-27 | 2006-03-10 | 삼성전자주식회사 | 상변화 메모리 소자에서의 라이트 드라이버 회로 및라이트 전류 인가방법 |
US6937507B2 (en) | 2003-12-05 | 2005-08-30 | Silicon Storage Technology, Inc. | Memory device and method of operating same |
US7928420B2 (en) | 2003-12-10 | 2011-04-19 | International Business Machines Corporation | Phase change tip storage cell |
US7291556B2 (en) | 2003-12-12 | 2007-11-06 | Samsung Electronics Co., Ltd. | Method for forming small features in microelectronic devices using sacrificial layers |
KR100569549B1 (ko) | 2003-12-13 | 2006-04-10 | 주식회사 하이닉스반도체 | 상 변화 저항 셀 및 이를 이용한 불휘발성 메모리 장치 |
KR100564602B1 (ko) | 2003-12-30 | 2006-03-29 | 삼성전자주식회사 | 상 변화 메모리 어레이의 셋 프로그래밍 방법 및 기입드라이버 회로 |
US7038230B2 (en) | 2004-01-06 | 2006-05-02 | Macronix Internation Co., Ltd. | Horizontal chalcogenide element defined by a pad for use in solid-state memories |
JP4124743B2 (ja) | 2004-01-21 | 2008-07-23 | 株式会社ルネサステクノロジ | 相変化メモリ |
KR100564608B1 (ko) | 2004-01-29 | 2006-03-28 | 삼성전자주식회사 | 상변화 메모리 소자 |
US6936840B2 (en) | 2004-01-30 | 2005-08-30 | International Business Machines Corporation | Phase-change memory cell and method of fabricating the phase-change memory cell |
US7858980B2 (en) | 2004-03-01 | 2010-12-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reduced active area in a phase change memory structure |
KR100574975B1 (ko) | 2004-03-05 | 2006-05-02 | 삼성전자주식회사 | 상 변화 메모리 어레이의 셋 프로그래밍 방법 및 기입드라이버 회로 |
JP4529493B2 (ja) | 2004-03-12 | 2010-08-25 | 株式会社日立製作所 | 半導体装置 |
US7005665B2 (en) * | 2004-03-18 | 2006-02-28 | International Business Machines Corporation | Phase change memory cell on silicon-on insulator substrate |
KR100598100B1 (ko) | 2004-03-19 | 2006-07-07 | 삼성전자주식회사 | 상변환 기억 소자의 제조방법 |
DE102004014487A1 (de) | 2004-03-24 | 2005-11-17 | Infineon Technologies Ag | Speicherbauelement mit in isolierendes Material eingebettetem, aktiven Material |
KR100532509B1 (ko) | 2004-03-26 | 2005-11-30 | 삼성전자주식회사 | SiGe를 이용한 트렌치 커패시터 및 그 형성방법 |
US7158411B2 (en) * | 2004-04-01 | 2007-01-02 | Macronix International Co., Ltd. | Integrated code and data flash memory |
US7482616B2 (en) | 2004-05-27 | 2009-01-27 | Samsung Electronics Co., Ltd. | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same |
KR100647218B1 (ko) | 2004-06-04 | 2006-11-23 | 비욘드마이크로 주식회사 | 고집적 상변화 메모리 셀 어레이 및 이를 포함하는 상변화메모리 소자 |
US6977181B1 (en) | 2004-06-17 | 2005-12-20 | Infincon Technologies Ag | MTJ stack with crystallization inhibiting layer |
US7359231B2 (en) * | 2004-06-30 | 2008-04-15 | Intel Corporation | Providing current for phase change memories |
KR100657897B1 (ko) * | 2004-08-21 | 2006-12-14 | 삼성전자주식회사 | 전압 제어층을 포함하는 메모리 소자 |
US7365385B2 (en) * | 2004-08-30 | 2008-04-29 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
KR100610014B1 (ko) | 2004-09-06 | 2006-08-09 | 삼성전자주식회사 | 리키지 전류 보상 가능한 반도체 메모리 장치 |
US7443062B2 (en) * | 2004-09-30 | 2008-10-28 | Reliance Electric Technologies Llc | Motor rotor cooling with rotation heat pipes |
TWI277207B (en) | 2004-10-08 | 2007-03-21 | Ind Tech Res Inst | Multilevel phase-change memory, operating method and manufacture method thereof |
KR100626388B1 (ko) | 2004-10-19 | 2006-09-20 | 삼성전자주식회사 | 상변환 메모리 소자 및 그 형성 방법 |
JP2006127583A (ja) * | 2004-10-26 | 2006-05-18 | Elpida Memory Inc | 不揮発性半導体記憶装置及び相変化メモリ |
DE102004052611A1 (de) | 2004-10-29 | 2006-05-04 | Infineon Technologies Ag | Verfahren zur Herstellung einer mit einem Füllmaterial mindestens teilweise gefüllten Öffnung, Verfahren zur Herstellung einer Speicherzelle und Speicherzelle |
US7364935B2 (en) | 2004-10-29 | 2008-04-29 | Macronix International Co., Ltd. | Common word line edge contact phase-change memory |
US7238959B2 (en) | 2004-11-01 | 2007-07-03 | Silicon Storage Technology, Inc. | Phase change memory device employing thermally insulating voids and sloped trench, and a method of making same |
US20060108667A1 (en) | 2004-11-22 | 2006-05-25 | Macronix International Co., Ltd. | Method for manufacturing a small pin on integrated circuits or other devices |
US7202493B2 (en) * | 2004-11-30 | 2007-04-10 | Macronix International Co., Inc. | Chalcogenide memory having a small active region |
JP2006156886A (ja) | 2004-12-01 | 2006-06-15 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
KR100827653B1 (ko) | 2004-12-06 | 2008-05-07 | 삼성전자주식회사 | 상변화 기억 셀들 및 그 제조방법들 |
US7220983B2 (en) | 2004-12-09 | 2007-05-22 | Macronix International Co., Ltd. | Self-aligned small contact phase-change memory method and device |
TWI260764B (en) | 2004-12-10 | 2006-08-21 | Macronix Int Co Ltd | Non-volatile memory cell and operating method thereof |
US20060131555A1 (en) | 2004-12-22 | 2006-06-22 | Micron Technology, Inc. | Resistance variable devices with controllable channels |
US20060138467A1 (en) | 2004-12-29 | 2006-06-29 | Hsiang-Lan Lung | Method of forming a small contact in phase-change memory and a memory cell produced by the method |
JP4646634B2 (ja) * | 2005-01-05 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7419771B2 (en) | 2005-01-11 | 2008-09-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a finely patterned resist |
US20060172067A1 (en) | 2005-01-28 | 2006-08-03 | Energy Conversion Devices, Inc | Chemical vapor deposition of chalcogenide materials |
US7214958B2 (en) | 2005-02-10 | 2007-05-08 | Infineon Technologies Ag | Phase change memory cell with high read margin at low power operation |
US7099180B1 (en) | 2005-02-15 | 2006-08-29 | Intel Corporation | Phase change memory bits reset through a series of pulses of increasing amplitude |
KR100707182B1 (ko) * | 2005-02-18 | 2007-04-13 | 삼성전자주식회사 | 상전이 메모리 소자 및 제조방법 |
US7229883B2 (en) | 2005-02-23 | 2007-06-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Phase change memory device and method of manufacture thereof |
KR100663358B1 (ko) | 2005-02-24 | 2007-01-02 | 삼성전자주식회사 | 셀 다이오드들을 채택하는 상변이 기억소자들 및 그 제조방법들 |
US7365382B2 (en) * | 2005-02-28 | 2008-04-29 | Infineon Technologies Ag | Semiconductor memory having charge trapping memory cells and fabrication method thereof |
JP2006244561A (ja) | 2005-03-01 | 2006-09-14 | Renesas Technology Corp | 半導体装置 |
US7154774B2 (en) | 2005-03-30 | 2006-12-26 | Ovonyx, Inc. | Detecting switching of access elements of phase change memory cells |
US7488967B2 (en) | 2005-04-06 | 2009-02-10 | International Business Machines Corporation | Structure for confining the switching current in phase memory (PCM) cells |
US7166533B2 (en) * | 2005-04-08 | 2007-01-23 | Infineon Technologies, Ag | Phase change memory cell defined by a pattern shrink material process |
KR100675279B1 (ko) | 2005-04-20 | 2007-01-26 | 삼성전자주식회사 | 셀 다이오드들을 채택하는 상변이 기억소자들 및 그제조방법들 |
US7408240B2 (en) | 2005-05-02 | 2008-08-05 | Infineon Technologies Ag | Memory device |
KR100682946B1 (ko) | 2005-05-31 | 2007-02-15 | 삼성전자주식회사 | 상전이 램 및 그 동작 방법 |
US20060273298A1 (en) | 2005-06-02 | 2006-12-07 | Matrix Semiconductor, Inc. | Rewriteable memory cell comprising a transistor and resistance-switching material in series |
KR100668846B1 (ko) * | 2005-06-10 | 2007-01-16 | 주식회사 하이닉스반도체 | 상변환 기억 소자의 제조방법 |
US7388273B2 (en) | 2005-06-14 | 2008-06-17 | International Business Machines Corporation | Reprogrammable fuse structure and method |
US8237140B2 (en) | 2005-06-17 | 2012-08-07 | Macronix International Co., Ltd. | Self-aligned, embedded phase change RAM |
US7238994B2 (en) * | 2005-06-17 | 2007-07-03 | Macronix International Co., Ltd. | Thin film plate phase change ram circuit and manufacturing method |
US7514288B2 (en) | 2005-06-17 | 2009-04-07 | Macronix International Co., Ltd. | Manufacturing methods for thin film fuse phase change ram |
US7598512B2 (en) | 2005-06-17 | 2009-10-06 | Macronix International Co., Ltd. | Thin film fuse phase change cell with thermal isolation layer and manufacturing method |
US7534647B2 (en) | 2005-06-17 | 2009-05-19 | Macronix International Co., Ltd. | Damascene phase change RAM and manufacturing method |
US7514367B2 (en) | 2005-06-17 | 2009-04-07 | Macronix International Co., Ltd. | Method for manufacturing a narrow structure on an integrated circuit |
US7696503B2 (en) | 2005-06-17 | 2010-04-13 | Macronix International Co., Ltd. | Multi-level memory cell having phase change element and asymmetrical thermal boundary |
US7321130B2 (en) * | 2005-06-17 | 2008-01-22 | Macronix International Co., Ltd. | Thin film fuse phase change RAM and manufacturing method |
US7651906B2 (en) | 2005-06-20 | 2010-01-26 | Samsung Electronics Co., Ltd. | Integrated circuit devices having a stress buffer spacer and methods of fabricating the same |
US20060289847A1 (en) | 2005-06-28 | 2006-12-28 | Richard Dodge | Reducing the time to program a phase change memory to the set state |
US20060289848A1 (en) | 2005-06-28 | 2006-12-28 | Dennison Charles H | Reducing oxidation of phase change memory electrodes |
TWI290369B (en) * | 2005-07-08 | 2007-11-21 | Ind Tech Res Inst | Phase change memory with adjustable resistance ratio and fabricating method thereof |
US7309630B2 (en) | 2005-07-08 | 2007-12-18 | Nanochip, Inc. | Method for forming patterned media for a high density data storage device |
US7345907B2 (en) * | 2005-07-11 | 2008-03-18 | Sandisk 3D Llc | Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements |
US20070037101A1 (en) * | 2005-08-15 | 2007-02-15 | Fujitsu Limited | Manufacture method for micro structure |
TWI273703B (en) * | 2005-08-19 | 2007-02-11 | Ind Tech Res Inst | A manufacture method and structure for improving the characteristics of phase change memory |
KR100655443B1 (ko) | 2005-09-05 | 2006-12-08 | 삼성전자주식회사 | 상변화 메모리 장치 및 그 동작 방법 |
US7615770B2 (en) | 2005-10-27 | 2009-11-10 | Infineon Technologies Ag | Integrated circuit having an insulated memory |
US7417245B2 (en) | 2005-11-02 | 2008-08-26 | Infineon Technologies Ag | Phase change memory having multilayer thermal insulation |
KR100695164B1 (ko) | 2005-11-09 | 2007-03-14 | 삼성전자주식회사 | 스위칭 소자로서 트랜지스터 및 다이오드를 포함하는하이브리드 타입의 비휘발성 메모리 소자 |
US20070111429A1 (en) | 2005-11-14 | 2007-05-17 | Macronix International Co., Ltd. | Method of manufacturing a pipe shaped phase change memory |
US7397060B2 (en) | 2005-11-14 | 2008-07-08 | Macronix International Co., Ltd. | Pipe shaped phase change memory |
US7450411B2 (en) | 2005-11-15 | 2008-11-11 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7786460B2 (en) | 2005-11-15 | 2010-08-31 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7394088B2 (en) | 2005-11-15 | 2008-07-01 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method (combined) |
US7635855B2 (en) | 2005-11-15 | 2009-12-22 | Macronix International Co., Ltd. | I-shaped phase change memory cell |
US7414258B2 (en) | 2005-11-16 | 2008-08-19 | Macronix International Co., Ltd. | Spacer electrode small pin phase change memory RAM and manufacturing method |
US7829876B2 (en) | 2005-11-21 | 2010-11-09 | Macronix International Co., Ltd. | Vacuum cell thermal isolation for a phase change memory device |
US7449710B2 (en) | 2005-11-21 | 2008-11-11 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US7479649B2 (en) * | 2005-11-21 | 2009-01-20 | Macronix International Co., Ltd. | Vacuum jacketed electrode for phase change memory element |
US7507986B2 (en) * | 2005-11-21 | 2009-03-24 | Macronix International Co., Ltd. | Thermal isolation for an active-sidewall phase change memory cell |
US7599217B2 (en) | 2005-11-22 | 2009-10-06 | Macronix International Co., Ltd. | Memory cell device and manufacturing method |
US7688619B2 (en) | 2005-11-28 | 2010-03-30 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US7459717B2 (en) * | 2005-11-28 | 2008-12-02 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US7233054B1 (en) | 2005-11-29 | 2007-06-19 | Korea Institute Of Science And Technology | Phase change material and non-volatile memory device using the same |
US7605079B2 (en) | 2005-12-05 | 2009-10-20 | Macronix International Co., Ltd. | Manufacturing method for phase change RAM with electrode layer process |
US7642539B2 (en) | 2005-12-13 | 2010-01-05 | Macronix International Co., Ltd. | Thin film fuse phase change cell with thermal isolation pad and manufacturing method |
US7531825B2 (en) | 2005-12-27 | 2009-05-12 | Macronix International Co., Ltd. | Method for forming self-aligned thermal isolation cell for a variable resistance memory array |
US8062833B2 (en) | 2005-12-30 | 2011-11-22 | Macronix International Co., Ltd. | Chalcogenide layer etching method |
US20070156949A1 (en) | 2005-12-30 | 2007-07-05 | Rudelic John C | Method and apparatus for single chip system boot |
US7292466B2 (en) | 2006-01-03 | 2007-11-06 | Infineon Technologies Ag | Integrated circuit having a resistive memory |
KR100763908B1 (ko) | 2006-01-05 | 2007-10-05 | 삼성전자주식회사 | 상전이 물질, 이를 포함하는 상전이 메모리와 이의 동작방법 |
US20070158632A1 (en) | 2006-01-09 | 2007-07-12 | Macronix International Co., Ltd. | Method for Fabricating a Pillar-Shaped Phase Change Memory Element |
US7595218B2 (en) | 2006-01-09 | 2009-09-29 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7560337B2 (en) | 2006-01-09 | 2009-07-14 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7741636B2 (en) | 2006-01-09 | 2010-06-22 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7825396B2 (en) | 2006-01-11 | 2010-11-02 | Macronix International Co., Ltd. | Self-align planerized bottom electrode phase change memory and manufacturing method |
US7351648B2 (en) * | 2006-01-19 | 2008-04-01 | International Business Machines Corporation | Methods for forming uniform lithographic features |
US7432206B2 (en) | 2006-01-24 | 2008-10-07 | Macronix International Co., Ltd. | Self-aligned manufacturing method, and manufacturing method for thin film fuse phase change ram |
US7456421B2 (en) * | 2006-01-30 | 2008-11-25 | Macronix International Co., Ltd. | Vertical side wall active pin structures in a phase change memory and manufacturing methods |
US7956358B2 (en) * | 2006-02-07 | 2011-06-07 | Macronix International Co., Ltd. | I-shaped phase change memory cell with thermal isolation |
US7426134B2 (en) | 2006-02-24 | 2008-09-16 | Infineon Technologies North America | Sense circuit for resistive memory |
US7910907B2 (en) | 2006-03-15 | 2011-03-22 | Macronix International Co., Ltd. | Manufacturing method for pipe-shaped electrode phase change memory |
US20070235811A1 (en) | 2006-04-07 | 2007-10-11 | International Business Machines Corporation | Simultaneous conditioning of a plurality of memory cells through series resistors |
US7928421B2 (en) | 2006-04-21 | 2011-04-19 | Macronix International Co., Ltd. | Phase change memory cell with vacuum spacer |
US20070249090A1 (en) | 2006-04-24 | 2007-10-25 | Philipp Jan B | Phase-change memory cell adapted to prevent over-etching or under-etching |
US7514705B2 (en) * | 2006-04-25 | 2009-04-07 | International Business Machines Corporation | Phase change memory cell with limited switchable volume |
US8129706B2 (en) | 2006-05-05 | 2012-03-06 | Macronix International Co., Ltd. | Structures and methods of a bistable resistive random access memory |
US7608848B2 (en) | 2006-05-09 | 2009-10-27 | Macronix International Co., Ltd. | Bridge resistance random access memory device with a singular contact structure |
US20070267618A1 (en) | 2006-05-17 | 2007-11-22 | Shoaib Zaidi | Memory device |
US7423300B2 (en) | 2006-05-24 | 2008-09-09 | Macronix International Co., Ltd. | Single-mask phase change memory element |
US7696506B2 (en) | 2006-06-27 | 2010-04-13 | Macronix International Co., Ltd. | Memory cell with memory material insulation and manufacturing method |
US7663909B2 (en) * | 2006-07-10 | 2010-02-16 | Qimonda North America Corp. | Integrated circuit having a phase change memory cell including a narrow active region width |
US7785920B2 (en) * | 2006-07-12 | 2010-08-31 | Macronix International Co., Ltd. | Method for making a pillar-type phase change memory element |
US7542338B2 (en) * | 2006-07-31 | 2009-06-02 | Sandisk 3D Llc | Method for reading a multi-level passive element memory cell array |
US7684225B2 (en) * | 2006-10-13 | 2010-03-23 | Ovonyx, Inc. | Sequential and video access for non-volatile memory arrays |
US20080225489A1 (en) | 2006-10-23 | 2008-09-18 | Teledyne Licensing, Llc | Heat spreader with high heat flux and high thermal conductivity |
US20080101110A1 (en) | 2006-10-25 | 2008-05-01 | Thomas Happ | Combined read/write circuit for memory |
US7473576B2 (en) * | 2006-12-06 | 2009-01-06 | Macronix International Co., Ltd. | Method for making a self-converged void and bottom electrode for memory cell |
US7476587B2 (en) | 2006-12-06 | 2009-01-13 | Macronix International Co., Ltd. | Method for making a self-converged memory material element for memory cell |
US7682868B2 (en) | 2006-12-06 | 2010-03-23 | Macronix International Co., Ltd. | Method for making a keyhole opening during the manufacture of a memory cell |
US20080137400A1 (en) | 2006-12-06 | 2008-06-12 | Macronix International Co., Ltd. | Phase Change Memory Cell with Thermal Barrier and Method for Fabricating the Same |
US20080165569A1 (en) | 2007-01-04 | 2008-07-10 | Chieh-Fang Chen | Resistance Limited Phase Change Memory Material |
US7515461B2 (en) * | 2007-01-05 | 2009-04-07 | Macronix International Co., Ltd. | Current compliant sensing architecture for multilevel phase change memory |
US20080164453A1 (en) | 2007-01-07 | 2008-07-10 | Breitwisch Matthew J | Uniform critical dimension size pore for pcram application |
US7440315B2 (en) | 2007-01-09 | 2008-10-21 | Macronix International Co., Ltd. | Method, apparatus and computer program product for stepped reset programming process on programmable resistive memory cell |
US7456460B2 (en) | 2007-01-29 | 2008-11-25 | International Business Machines Corporation | Phase change memory element and method of making the same |
US7535756B2 (en) | 2007-01-31 | 2009-05-19 | Macronix International Co., Ltd. | Method to tighten set distribution for PCRAM |
US7701759B2 (en) | 2007-02-05 | 2010-04-20 | Macronix International Co., Ltd. | Memory cell device and programming methods |
US7463512B2 (en) | 2007-02-08 | 2008-12-09 | Macronix International Co., Ltd. | Memory element with reduced-current phase change element |
US8138028B2 (en) | 2007-02-12 | 2012-03-20 | Macronix International Co., Ltd | Method for manufacturing a phase change memory device with pillar bottom electrode |
US8008643B2 (en) | 2007-02-21 | 2011-08-30 | Macronix International Co., Ltd. | Phase change memory cell with heater and method for fabricating the same |
US7447062B2 (en) | 2007-03-15 | 2008-11-04 | International Business Machines Corproation | Method and structure for increasing effective transistor width in memory arrays with dual bitlines |
US20080265234A1 (en) | 2007-04-30 | 2008-10-30 | Breitwisch Matthew J | Method of Forming Phase Change Memory Cell With Reduced Switchable Volume |
US7906368B2 (en) * | 2007-06-29 | 2011-03-15 | International Business Machines Corporation | Phase change memory with tapered heater |
US7745807B2 (en) * | 2007-07-11 | 2010-06-29 | International Business Machines Corporation | Current constricting phase change memory element structure |
US7755935B2 (en) * | 2007-07-26 | 2010-07-13 | International Business Machines Corporation | Block erase for phase change memory |
US7551473B2 (en) | 2007-10-12 | 2009-06-23 | Macronix International Co., Ltd. | Programmable resistive memory with diode structure |
CN101262004B (zh) * | 2008-04-11 | 2011-04-20 | 中国科学院上海微系统与信息技术研究所 | 双浅沟道隔离的双极型晶体管选通的相变存储单元及方法 |
-
2009
- 2009-01-13 US US12/353,219 patent/US8030635B2/en active Active
- 2009-04-16 TW TW098112675A patent/TWI385790B/zh active
-
2010
- 2010-01-12 CN CN2010100035021A patent/CN101814521B/zh active Active
-
2011
- 2011-10-03 US US13/252,152 patent/US8237144B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200532693A (en) * | 2003-12-05 | 2005-10-01 | Renesas Tech Corp | Semiconductor integrated circuit device |
US20080311722A1 (en) * | 2007-06-15 | 2008-12-18 | Sandisk 3D Llc | Method for forming polycrystalline thin film bipolar transistors |
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US8030635B2 (en) | 2011-10-04 |
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