TWI380422B - - Google Patents

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Publication number
TWI380422B
TWI380422B TW097123918A TW97123918A TWI380422B TW I380422 B TWI380422 B TW I380422B TW 097123918 A TW097123918 A TW 097123918A TW 97123918 A TW97123918 A TW 97123918A TW I380422 B TWI380422 B TW I380422B
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TW
Taiwan
Prior art keywords
layer
package substrate
substrate
present
sectional
Prior art date
Application number
TW097123918A
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English (en)
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TW200921876A (en
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Publication of TW200921876A publication Critical patent/TW200921876A/zh
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Publication of TWI380422B publication Critical patent/TWI380422B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Description

九、發明說明： 【發明所屬之技術領域】 本發：係有關於一種無核層多層封褒.基板之製作
Tilt一種以銅核基板為基礎，開始製作之多層封 2板，製作方法’於其中，該多層封裝基板之結構係 包括具球側柱狀電性接腳接塾與至少—增層線路。 【先前技術】 在y般多層封裝基板之製作上，其製作方式通常係 基板開始’經過鑽孔、電鍍金屬、塞孔及雙面 線路製作等方式，完成—雙面結構之内層核心板，之後 再經由一線路增層製程完成一多層封裝基板。如第2 3 ，所示’其係為一有核層封裝基板之剖面示意圖。首 f’準備一核心基板6〇,其中，該核心基板60係由 一具預定厚度之芯層6 〇工及形成於此芯層6 〇工表 面之線路層602所構成’且該芯層601中係形成有 複數個電料軌6Q3m接該 面之線路層6 〇 2。 接著如第2 4圖〜第2 7圖所示’對該核心基板6 0實施線路增層製程。首先，係於該核心基板6 〇表面 形成-第-介電層6 !，且該第一介電層6工表面並形 成有複數個第一開口 6 2，以露出該線路層㈣2 ;之 後以無電電鑛與電鑛等方式於該第一介電層61外露 之表面形成—晶種層6 3，並於該晶種層6 3上形成-圖案化阻層6 4 ’且其圖案化阻層6 4令並有複數個第 一開口 6 5 ,以露出部份欲形成圖案化線路之晶種層6 1380422 3 ;接著’利用電鍍之方式於該第二開口 6 5中形成一 第一圖案化線路層6 6及複數個導電盲孔6 7，並使其 第圖案化線路層6 6得以透過該複數個導電盲孔6 7與該核心基板6 〇之線路層6 0 2做電性導通，然後 再進行移除該圖案化阻層6 4與蝕刻’待完成後係形成 一第一線路增層結構6 a。同樣地，該法係可於該第一 線路增層結構6a之最外層表面再運用相同之方式形成 一第二介電層6 8及一第二圖案化線路層6 9之第二 線路增層結構6b，以逐步增層方式形成一多層封裝基 板。然而，此種製作方法有佈線密度低、層數多及流程 複雜等缺點。 另外，亦有利用厚銅金屬板當核心材料之方法，可 於經過蝕刻及塞孔等方式完成一内層核心板後，再經由 一線路增層製程以完成一多層封襄基板。如第2 8圖〜 第3 0圖所示，其係為另一有核層封裝基板之剖面示意 圖。首先，準備一核心基板7 〇，該核心基板7 〇係2 一具預定厚度之金屬層利用蝕刻與樹脂塞孔7 〇 1以 及鑽孔與電鍍通孔7 〇 2等方式形成之單層銅核心基 板7 ◦;之後，利用上述線路增層方式，於該核心基板 70表面形成一第-介電層71及-第-圖案化線路 層7 2，藉此構成一具第一線路增層結構7a。該法亦 與上述方法相同，係、可再湘—次線路增層方式於 -線路增層結構73之最外層表面形成—第二介電層7 3及-第二圖案化線路層7 4 ’藉此構成一具第；路 增層結構7b，以逐步增層方式形成一多層封裝基板。 1380422 ::此種製作方法不僅其鋼核心基板製作不易，且亦 [方法相同，具有料密度低及流程㈣等缺點。 需。般1用者係無法符合使用者於實際使用時之所 【發明内容】 增層主要目的係在於，使用本發明具高密度之 基板方法所製造之無核層多層封裝基 μ係可有效達到改善超薄核層基板板勒問題、及簡 統增層線路板製作流程，進而達到提高封裝體組裝 時之可靠度（Board Level Reliability )。 發明之次要目的係在於’從—銅核基板為基礎， =·作之多層封裝基板^其結構係包括具球側柱狀電 性接㈣墊與至少—增層線路。於其中，各增 置晶側與球側連接之方式係以複數個電鍍盲:：孔所導 通。 ^發明之另-目的係在於，具有高密度增層線路以 k供電子元件相連時所需之繞線，同時，並含有具保護 作用之柱狀接腳可提高封裝體組裝時之可靠度。 為達以上之目的’本發明係一種無核層多又層封裝基 板之製作方法，減以光學微影及_之方式於一銅核 基板之第-面上形成複數個第—凹槽，藉以突顯複數接 腳之一部分。並以此複數接腳之I面作為與增層線路 之電性連接整。之後於該複數接腳第—面上形成複數個 電鍵盲孔以連接至卜增層線路，並在增層線路之置晶 7 1380.422 側形成電性接墊；而接腳側則利用該銅核基板之第二面 形成球側圖案阻層，並於之後移除該鋼核基板，以形成 柱狀電性接腳接塾。 【實施方式】 土凊參閱『第1圖』所示’係為本發明之製作流程示 思圖。如圖所示：本發明係一種無核層多層封裝基板之 製作方法，其至少包括下列步驟： • ( A )提供銅核基板11 :提供一銅核基板； (B)形成第一'二阻層及複數個第一開口12: Z於該銅核基板之第—面上形成一第—阻層，以及於 層…二？板之第二面上形成一完全覆蓋狀之第二阻 ::其令’並以曝光及顯影之方式 成稷數個第一開口，以s ^ 乂 貝路其下泫銅核基板之第一面； 第ϋ槽13:以_之方式於複數個 第開口下方形成複數個第一凹槽； _ (D)移除第一、-P日S1/1 該第一阻層及該第：_層14 ··以剝離之方式移除 基板丨 θ，形成具有接腳第一面之銅核 (Ε )形成第一電性 .^ 刷之方式於複數個第一凹":乂、5·:乂直㈣合或印 (F)形成第一介電電性阻絕層，· 核基板之第-面與該第:屬層16 :··於該鋼 —介電層及一第一公届生阻絕層上直接屋合一第 電層後，再形成該第4屬=或係先採取貼合該第一介 8 1380.422 (G )形成複數個第二開口丄7 :以雷射鑽孔之方 式於該第一金屬層與該第一介電層上形成複數個第二 開口，並顯露其下之鋼核基板第一面，其中，複數個第 一開口係可先做開銅窗（c〇nformai Mask )後，再經由 雷射鑽孔之方式形成，亦或係以直接雷射鑽孔（
Direct)之方式形成； (H)形成第二金屬層18:以無電電鍍與電鍍之 方式於複數個第二開口中及該第一金屬層上形成一第 一金屬層，其令，該第二金屬層係作為與該銅核基板第 一面之電性連接用； (I )形成第二、四阻層及複數個第三開口 1 9 : 分別於該第二金屬層上形成—第三阻層，以及於該銅核 基板之第二面上形成一完全覆蓋狀之第四阻層，於其 中，並以曝光及顯影之方式在該第三阻層上形成複數個 第三開口，以顯露其下之第二金屬層； 一（J )形成第一線路層2 〇 :以蝕刻之方式移除該 第一開口下方之第二金屬層及第一金屬層，並形成一第 一線路層； (K)元成具有銅核基板支撑並具電性連接之單層 增層線路基板2 1 :以㈣之方式移除該第三阻層及該 第四：層。至此’完成一具有銅核基板支撐並具電性連 接之單層增層線路基板，並可選擇直接進行步驟（L ) 或步驟（Μ); ,(L )進行置晶側線路層與球側柱狀電性接腳接墊 之^•作2 2 .於遠單層增層線路基板上進行一置晶側線 1380422
料與球側柱狀電性接腳接塾之製作，於其中，在該第 線路層表面形成-第—防痒層，並以曝光及顯影之方 式在該第一防焊層上形成複數個第四開口，以顯露線路 ^層結構作為電性連㈣之部分，接著再分職該銅核 ，板之第一面上形成一第五阻層’並且在該第五阻層上 以曝光及顯影之方式形成複數個第五開σ，以及於該第 -防焊層上形成一完全覆蓋狀之第六阻層。之後移除複 數個第五開口下方之銅核基板，以形成複數個柱狀接 腳’並以剝離之方式移除該第五阻層與該第六阻層，最 後再分別於複數個第四開口上形成一第一阻障層，以及 於複數個柱狀接腳上形成一第二阻障層。至此，完成一 具有完整圖案化之置晶側線路層與;求側複數柱狀接 腳’其中’該第―、二阻障層係可為電鍍錄金、無電鑛 鎳金、電鍍銀或電鍍錫中擇其一；以及 .(Μ)進行線路增層結構製作2 3 :於該單層增層 線路基板上進行一線路增層結構之製作，於其中丨^言^ 第一線路層與該第一介電層表面形成一第二介電層，並 以雷射鑽孔之方式在該第二介電層上形成複數個第六 開口’以顯露其下之第一線路層，接著以無電電鍍與電 鍍之方式於該第二介電層與複數個第六開口表面形成 -第-晶種層’再分別於該第一晶種層上形成一第七阻 層，以及於該銅核基板之第二面上形成一完全覆蓋狀之 第八阻層’並利用曝光及顯影之方式於該第七阻層上形 成複數個第七開口，以顯露其下之第一晶種層，^後再 以電鍍之方式於該第七開口中已顯露之第一晶種層上 1380422 形成一第三金屬層，最後以剝離之方式移除該第七阻層 與該第八阻層’並以蝕刻之方式移除該第一晶種層，以 在該第二介電層上形成一第二線路層。.至此，又再增加 • 一層之線路增層結構’完成一具有銅核基板支撐並具電 性連接之雙層增層線路基板。並可繼續本步驟增 加線路增層結構，形成具更多層之封裝基板，亦或直接 至s玄步驟（L)進行置晶側線路層與球側柱狀電性接腳 φ接墊之製作’其中，複數個第六開口係可先做開銅窗 後，再經由雷射鑽孔之方式形成，亦或係以直接雷射鑽 孔之方式形成》 於其中，上述該第一〜八阻層係以貼合、印刷或旋 轉塗佈所為之乾膜或溼膜之高感光性光阻；該第一電性 阻絕層及該第一、二介電層係可為防焊綠漆、環氧樹脂 絕緣膜（Ajinomoto Build-up Film, ABF)、笨環丁稀 (Benzocyclo-buthene，BCB)、雙馬來亞醯胺-三氮雜笨 鲁樹脂（Bismaleimide Triazine，BT)、環氧樹脂板（FR4、 FR5 )、聚醯亞胺（Polyimide，PI )、聚四氟乙稀 (Poly(tetra-flor〇ethylene)，PTFE )或環氧樹脂及玻璃纖 維所組成之一者。 請參閱『第2圖〜第1 2圖』所示’係分別為本發 • 明一實施例之多層封裝基板（一）剖面剖面示意圖、本 • 發明一實施例之多層封裝基板（二）剖面示意圖、本發 .明一實施例之多層封裝基板（三）剖面示意圖、本發明 一實施例之多層封裝基板（四）剖面示意圖、本發明一 實施例之多層封裝基板（五）剖面示意圖、本發明一實 Ϊ380422 施例之多層封裝基板（六）剖面示意圖'本發明一實施 例之多層封裝基板（七）剖面示意圖、本發明一實施例 之多層封裝基板（人）剖面示意圖、本發明—實施例之 多層封裝基板（九）剖面示意圖、本發明一實施例之多 層封裝基板（十）剖面示意圖、及本發明一實施例之多 層封裝基板（十一）剖面示意圖。如圖所示：本發明於 一較佳實施例中，係先提供一銅核基板3 0，並分別於 鲁。亥銅核基板3 0之第一面上貼合一高感光性高分子材 料之第一阻層3 1，以及於該銅核基板3 〇之第二面上 貼合一高感光性高分子材料之第二阻層3 2，並以曝光 及顯衫之方式在該第一阻層3 1上形成複數個第一開 3 3 ’以顯露其下該銅核基板3 〇之第一面，而其第 二面上之第二阻層3 2則為完全覆蓋狀。接著以蝕刻之 方式製作一蝕刻凹槽，其中’該銅核基板3 〇係為一不 含介電層材料之銅板；該第一、二阻層3丄、3 2係為 _ 乾骐光阻層。 接著，移除該第一、二阻層，以形成具有接腳第一 面之鋼核基板3 0。之後係印刷一第一電性阻絕層3 4 於該凹槽中，並在該銅核基板3 〇之第一面上壓合一第 ’丨電層3 5及一第一金屬層3 6 ’再以雷射鑽孔之方 式於該第一金屬層3 6與該第一介電層3 5上形成複 數個第二開口 3 7，之後係以無電電鍍與電鍍之方式於 複數個第二開口 3 7及該第一金屬層3 6表面形成一 第二金屬層38，其中，該第一、二金屬層36、38 皆為鋼’且該第二金屬層3 8係作為與該銅核基板3 〇 12 1380422 第一面之電性連接用。 一 接著’分別於該第二金屬層3 8上貼合一高感光性 ，分子材料之第三阻層3 9，以及於該銅核基板3 〇之 第一面上貼合一高感光性高分子材料之第四阻層4 0 ’並以曝光及顯影之方式於該第三阻層3 9上形成複 數個第三開口 4 1 ,以顯露其下之第二金屬層3 8。之 後係以姓刻之方式移除該第三開口 4 1下之第一、二金 屬層，以形成一第一線路層4 2，最後並移除該第三、
四阻層。至此，完成一具有圖案化線雖並與該銅核基板 3 0之接腳第一面連接之單層增層線路基板3。 。月參閱『第1 3圖〜第1 7圖』所示，係分別為本 發明一實施例之多層封裝基板（十二）剖面示意圓、本 發明一實施例之多層封裝基板（十三）剖面示意圖、本 發明一實施例之多層封裝基板（十四）剖面示意圖、本 發明一實施例之多層封裝基板（十五）剖面示意圖、及 本發明一實施例之多層封裝基板（十六）剖面示意圖。 如圖所示：在本發明較佳實施例中，係先行進行線路增 層結構之製作。首先於該第一線路層4 2與該第一介電 層3 5上貼壓合一為環氧樹脂絕緣膜材料之第二介電 層4 3，之後並以雷射鑽孔之方式於該第二介電層4 3 上形成複數個第四開口 4 4 ,以顯露其下之第一線路層 42,並在該第二介電層43與該第四開口44表面以 無電電鍍與電鍍方式形成一第一晶種層4 5。之後分別 於該第一晶種層4 5上貼合一高感光性高分子材料之 第五阻層4 6，以及於該銅核基板3 〇之第二面上貼合 13 1380422 一南感光性高分子材料之第六阻層4 7，接著利用曝光 及顯备之方式於該第五阻層4 6上形成複數個第五開 口 4 8，然後再於複數第五開口48中電鍍一第三金屬 層4 9，最後移除該第五、六阻層，並再以蝕刻之方式 移除顯露之第—晶種層，以形成-第二線路層5〇。至 此，又再增加一層之線路增層結構，完成一具有銅核基 板支撐並具電性連接之雙層增層線路基板4，於其中， 該第-晶種層4 5與該第三金屬層4 9皆為金屬銅。 請參閱『第1 8圖〜第2 2圖』所示，係分別為本 發明一實施例之多層封裂基板（十七）剖面示意圖、本 發明-實施例之多層封裝基板（十八）剖面示意圖、本 發明一實施例之多層封裝基板（十九）剖面示意圖、本 發明-實施例之多層封裝絲（二十）杳!面示意圖、及 本發明一實施例之多層封裝基板（二十一）剖面示意 圖。如圖所示：之後，在本發明較佳實施例中係接著進 行置晶側線路層與球側柱狀電性接腳接墊之製作。首先 於該第二線路層5 〇表面塗覆一層絕緣保護用之第一 防焊層5 1，並以曝光及顯影之方式於該第一防焊層5 1上形成複數個第六開口 5 2，以顯露線路增層結構作 為電性連接墊。接著分別於該銅核基板3 〇之第二面上 貼合一高感光性高分子材料之第七阻層5 3，以及於該 第一防焊層5 1上貼合一高感光高分子材料之第八阻 層5 4，且該第七阻層5 3上並形成有複數個第七開口 5 5。之後係移除複數個第七開口 5 5下方之銅核基板 3 0，以形成複數個柱狀接腳5 6，並再移除該第七' 1380422 八阻層。最後’分別於複數個第六開口 5 2上形成一第 一阻障層5 7，以及於複數個柱狀接腳5 6上形成一第 二阻障層58。至此，完成一無核層多層封裝基板5， 其中，該第一、二阻障層57、58皆為鎳金層。 由上述可知，本發明係從銅核基板為基礎，開始製 作之夕層封裝基板，其結構係包括具球側柱狀電性接腳 接墊與至少一增層線路。於其中，各增層線路及置晶側 -、求側連接之方式係以複數個電鑛盲、埋孔所導通。因 此，本發明封裝基板之特色係在於具有高密度增層線路 以提供電子元件相連時所需之繞線，同時，並含有具保 護作用之柱狀接腳。藉此，使用本發明具高密度之增層 線路封裝基板方法所製造之無核層多層封裝基板，係可 有效達到改善超薄核層基板板彎翹問題、及簡化傳統增 層線路板製作流程，進而達到提高封裝體組裝時之可靠 度（Board Level Reliability)。 紅上所述，本發明係一種無核層多層封裝基板之製 作方法，可有效改善習用之種種缺點，以具有高密度增 層線路提供電子元件相連時所需之繞線，同時，並含有 具保護作用之柱狀接腳。藉此，使用本發明具高密度之 增層線路封裝基板方法所製造之無核層多層封裝基 板，係可有效達到改善超薄核層基板板彎翹問題、及簡 化傳統增層線路板製作流程，以達到提高封裝體組裝時 之可罪度，進而使本發明之産生能更進步、更實用、更 付合使用者之所須，確已符合發明專利申請之要件爰 依法提出專利申請。 15 1380422 惟以上所述者’僅為本發明之較佳實施例而已杏 不能以此限定本發明實施之範圍；故，凡依本發二 ^範圍及發明說明書内容所作之簡單的等效變二 乜飾，皆應仍屬本發明專利涵蓋之範圍内。 、 【圖式簡單說明】 第1圖，係本發明之製作流程示意圖。
第2圖，係本發明一實施例之多層封裝基板（一）剖 面示意圖 第3圖，係本發明一實施例之多層封裝基板（二）剖 面示意圖。 第4圖’係本發明一實施例之多層封裝基板（三）剖 面示意圖。 第5圖，係本發明一實施例之多層封裝基板（四）剖 面示意圖。 第6圖，係本發明一實施例之多層封裝基板（五）剖 面示意圖。 第7圖’係本發明一實施例之多層封裝基板（六）剖 面示意圖。 第8圖，係本發明.一實施例之多層封裝基板（七）剖 面示意圖。 第9圖，係本發明一實施例之多層封裝基板（八）剖 面示意圖。 第1 〇圖，係本發明一實施例之多層封裝基板（九） 剖面示意圖。 1380422 第1 1圖，係本發明一實施例之多層封裝基板（十） 剖面示意圖。 第1 2圖，係本發明一實施例之多層封裝基板（十一） 剖面示意圖。 第1 3圖，係本發明一實施例之多層封装基板（十二） 剖面示意圖。 第1 4圖，係本發明一實施例之多層封裝基板（十三） 剖面示意圖。 第1 5圖，係本發明一實施例之多層封裝基板（十四） 剖面示意圖。 第1 6圖，係本發明一實施例之多層封裝基板（十五） 剖面示意圖。 第1 7圖，係本發明一實施例之多層封裝基板（十六） 剖面示意圖。 第1 8圖，係本發明一實施例之多層封裝基板（十七） 剖面示意圖。 第1 9圖，係本發明一實施例之多層封裝基板（十八） 剖面示意圖。 第2 0圖，係本發明一實施例之多層封裝基板（十九） 剖面示意圖。 第2 1圖，係本發明一實施例之多層封裝基板（二十） 剖面示意圖。 第2 2圖，係本發明一實施例之多層封裴基板（二十 一）剖面示意圖。 第2 3圖’係、習用有核層封裝基板之剖面示意圖。 17 1380422 第24圖’係習用實施線路増；一 第2 6圖 第2 7圖 第2 8圖 第2 9圖 第2 5圖，係習用實施線路増；：面示f圖。 係習用實施線路;；：:面示f圖。 係習用實施線路：ΐ二剖面示意圖。 , 吟增層（四）剖面示意圖。 係另一習用有核層封裝基板之剖面示意圖。 係另-習用之第—線路增層結構剖面示意 圖。 第3 〇圖’係另m二路增層結構剖面示意圖。 【主要元件符號說明】 (本發明部分） 步驟（A)〜（M) 11〜23 單層增層線路基板3 雙層增層線路基板4 無核層多層封裝基板5 銅核基板3 0 第一、二阻層31、3 2 第一開口 3 3 第一電性阻絕層3 4 第一介電層3 5 第一金屬層3 6 第二開口 3 7 第二金屬層3 8 第三阻層3 9 第四阻層4 0 1380422 第三開口 4 1 第一線路層4 2 第二介電層4 3 第四開口 4 4 第一晶種層4 5 第五阻層4 6 第六阻層4 7 第五開口 4 8 第三金屬層4 9 第二線路層5 0 第一防焊層5 1 第六開口 5 2 第七阻層5 3 第八阻層5 4 第七開口 5 5 柱狀接腳5 6 第一、二阻障層57、58 (習用部分） 第一、二線路增層結構6 a、6 b 第一、二線路增層結構7 a、7 b 核心基板6 0 芯層6 Ο 1 線路層6 0 2 電鍍導通孔6 0 3 第一介電層6 1 19 1380422 第一開口 6 2 該晶種層6 3 圖案化阻層6 4 第二開口 6 5 第一圖案化線路層6 6 導電盲孔6 7 第二介電層6 8 第二圖案化線路層6 9 核心基板7 0 樹脂塞孔7 Ο 1 電鍍通孔7 0 2 第一介電層7 1 第一圖案化線路層7 2 第二介電層7 3 第二圖案化線路層7 4
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Claims (1)

  1. 五及七開 板之製作方法，其中，複數個第一、三 口係以曝光及顯影之方式形成。 5 專利範圍第1項所述之無核層多層封裝基 作以，其中，該㈣（c)形成複數個第 一凹槽、該步驟（；）移除該第―、二金屬層及該 步驟（Μ )移除該卜晶種層之方法係可為钱刻: 6依據申4專利範圍第i項所述之無核層多層封裝基 板之製作方法’其中’該第--人阻層之移除方法 係可為剝離。 7 .依據申請專利範圍第1項所述之無核層多層封裝基 板之製作方法，其中，該第一電性阻絕層係以直接 壓合或印刷之方式形成。 8 ·依據申請專利範圍第1項所述之無核層多層封裝基 板之製作方法，其中，該第一電性阻絕層及該第 一、二介電層係可為防焊綠漆、環氧樹脂絕緣膜 (Ajinomoto Build-up Film, ABF )、笨環丁稀 (Benzocyclo-buthene，BCB )、雙馬來亞酿胺·三氮 雜笨樹脂（Bismaleimide Triazine，BT)、環氧樹脂 板（FR4、FR5 )、聚酿亞胺（p〇iyimide，PI )、聚 四氟乙烯（Poly(tetra-floroethylene)，PTFE )或環氧 樹脂及玻璃纖維所組成之一者。 9 .依據申請專利範圍第1項所述之無核層多層封裝基 板之製作方法’其中，該步驟（F )係以直接壓合 1380422 i 〇·依據申請專利範圍第1項所述之無核層多層封裝 基板之製作方法，其中，複數個第二、六開:係^ 先做開銅窗（C0nf0rmai Mask)後，再經由雷射鑽 孔之方式形成，亦或係以直接雷射鑽孔dASER Direct)之方式形成。 .依據申請專利範圍第1項所述之無核層多層封裴 基板之製作方法，其中，該第二、三金屬層及該第 一晶種層之形成方式係可為無電電鍍與電鍍。 •依據申請專利範圍第1項所述之無核層多層封裝 基板之製作方法，其中，該第一、二阻障層係可為 電鑛錄金、無電鍍鎳金、電鍍銀或電鍍錫中擇其一。
    25
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