TWI260960B - Method for forming high density bi-layer circuit board - Google Patents

Abstract

A method for forming high density bi-layer circuit board is proposed. An organic insulating layer is formed with at least a blind via therethrough, wherein the bottom end of the blind via is connected to a second conductive layer formed on a second surface of the circuit board. A seed layer is applied over a first surface of the circuit board and fully or partially covers the blind via. Then a patterned resist layer is applied over the seed layer and formed with at least an opening corresponding in position to the blind via. After a first conductive layer is formed within the blind via by an electrically chemical method, the resist layer and the seed layer underneath the resist layer are removed to form a high density bi-layer circuit board.

Description

1260960 r - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ A method for fabricating a core circuit board of a multi-layered multi-addition circuit board, the double-layer circuit board being formed by using an organic insulating layer and having at least one conductive layer or circuit layer on one surface thereof on the other surface The circuit layer is formed by a semi-additive process (SAP), and an electrically conductive via hole is formed on the insulating layer of the double-layer circuit board to provide electrical connection of the conductive layer. [Prior Art] The number of assistants 3 is therefore required for the circuit boards and electronic components of these electronic products. Therefore, for the application of electronic products, the embarrassing sin and the high wiring density are increased by a layering technique in a core stack, a plurality of insulating layers and v 1 a ho 1 es) to provide a circuit board $η _ The number of you can be used up to now, the increase in the number of electronic components of electronic components has long been the use of mobile phones, laptops, portable video recorders or personal digital assistants. Smaller and thinner parts than before, and with this trend of miniaturization, various mountings on a circuit board have a higher density and require a thinner and higher wiring density multi-layer circuit board in the process of the road board. And design will face higher challenges in the board manufacturing industry, low cost, high has always been the goal pursued. In order to achieve the goal, then surgery (bui ld-up). The so-called core circuit b〇ard has alternating conductive layers on the surface, and then electrical vias are formed in the insulating layer (for electrical connection between the conductive layers. However, the actual situation of the layer is required. The technology of stacking more than 丨〇 or 2 电路 layer boards has produced a number of loads of various types of 1260960 ____137826__U β U 曰 修正 修正 修正 五 五 五 五 五 五 五 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Usually, the manufacture of a build-up board requires the use of a single, double-panel or multi-layer board as the core substrate, which is the core circuit board. In Figures 1 and 2, the conventional build-up layer is shown. Schematic diagram of a multi-layer circuit board. Referring to FIG. 1, a multi-layered multi-layer circuit board 100 includes a core circuit board 1 and two build-up structures 1 〇 2. The core circuit board 101 includes a plurality of patterned patterns. The circuit layer 1〇3, and the insulating layer ι4 between any two circuit layers 103. A conductive via ι〇5 acts as an electrical interconnection between the circuit layers 103. The build-up structure 1 〇2 Also includes circuit layer 1 〇 6 The insulating layer 10 7 is a plurality of layers, however, the circuit layer 1 〇 6 of the build-up structure 1 〇 2 and the insulating layer 107 are generally thinner than the circuit layer 1 〇 3 and the insulating layer 1 〇 4 of the core circuit board 1 The circuit layer 1 〇 6 of the build-up structure 1 〇 2 is electrically connected by a conductive via 1 〇 8 ( v 1 as). In the first figure, the core circuit board 1 〇i is a Multi-layer circuit board (ie, six layers), and the build-up structure 1 〇 2 has two layers on the top and bottom. See Figure 2 for another schematic of the conventional layered multi-layer circuit board ^ /, medium & The multi-layer circuit board 200 includes a circuit board 20 1 as a core $ way board and two build-up structures 2 〇 2. The core circuit board 2 〇 1 includes two patterned circuit layers 203 and an insulating layer 2 〇 4 therebetween. The conductive vias 20 5 are electrically connected between the circuit layers 2 0 3 , and the build-up structure 2 〇 2 also includes the circuit layers 2 〇 6 and the insulating layer 2 0 7 , however, the build-up structure 2 〇 2 The circuit layer 2 〇6 and the insulation, the circuit layer 2 〇3 and the insulating layer 205 of the circuit board 2 〇1 are generally much thinner. The circuit layer 2 0 6 of the build-up structure 2 0 2 Through hole 2〇8 (Electrically connected. In the second figure, the board 2 is a multi-layer (ie, two layers), and the build-up structure 2〇2 is on the lower side of the board 201.

17100 懋 ptc Page 6 1260960 Case No. 91137826 a Amendment 5, invention description (3) Each has two layers, so a six-layer circuit board structure is formed. To achieve a more reliable via design for multi-layer boards, Figure 3 shows three common via processes commonly found in the industry. Figure 3A shows a schematic diagram of a commonly known plated-through hole (PTH). The opening of the through hole extends through the insulating layer 310 and the circuit layers 3 0 2 and 3 0 3 covering the surface thereof, and the conductive layer composed of the plated metal 300 is formed on the sidewall of the via hole. After the electroplating is completed, a conductive or non-conductive filling material 305 is filled to fill the residual space to ensure the reliability of the via hole. Figure 3B shows another form of via, a so-called blind via (b 1 i nd v i a), in which the opening of the blind via extends into the interior of the insulating layer 306 but does not penetrate the circuit layer 307. After the plating layer 30 8 is deposited, a conductive or non-conductive material is filled in the recesses to provide proper flatness for subsequent processes. Figure 3C shows a third form of via in which the opening of the blind via extends through the insulating layer 310, but does not penetrate the circuit layer 31. After the via holes are filled with the conductive material 3 1 3, the circuit layer 3 1 2 is formed. The first and third conventional techniques described above need to be filled with a filler material in the gap of the through hole (thr 〇ughh ο 1 e ), but when the effective through hole diameter is less than 0.05 mm, the process will change. It is difficult to implement. Therefore, in the general manufacturing industry, the above first and third conventional processes must be carried out when the through hole diameter is 0.75 mm or more, which makes the manufacturing feasibility much easier. Under such circumstances, the core circuit board cannot meet the requirements of higher wiring density due to the limitation of the process technology of the through hole. Compared with the traditional substractive #刻法, the current industry adopts the additive method for making finer lines, in order to respond to higher density boards, this method can be further divided into complete additions. to make

17100 全懋.ptc Page 7 1260960 - ^ f〆... Case No. 91138826 M7 on July 7 - __ V. Description of invention (4) (fully-additive) and semi-additive (semi- Additive) two processes. A typical semi-additive method is to form a seed layer on an insulating circuit board with electroless copper, and then directly form a circuit layer on the seed layer. A typical process for customizing the semi-additive method of finer circuits is shown in Figure 4. First, referring to FIG. 4A, a core circuit board 40 1 includes a patterned circuit layer 420, an insulating layer 403 between the two circuit layers 406, and an electrical connection between the circuit layers. An internally connected conductive-through hole 404. And two organic insulating layers 40 5 are vacuum-bonded to the surface of the core circuit board 410, as shown in FIG. 4B. Next, referring to FIG. 4C, a plurality of blind vias 060 are formed on the organic insulating layer 405, and an electroless copper thin layer 407 is formed on the surface of the organic insulating layer 405, and the electric clock is A patterned resist layer 408 is disposed on the copper 40 7 . The circuit layer 4 0 9 is formed by the electric ore method in the resist layer opening ( o p e n i n g ) 4 1 0 as shown in FIG. 4D. After the resist layer 40 8 and a portion of the electroless copper thin layer 407 are removed, a four-layer circuit board 400 is formed. As shown in FIG. 4E, the four-layer circuit board is completed. The system includes a core circuit board 410 and two build-up structures 4 1 1 , and the build-up structure 4 1 1 includes an organic insulating layer 405 and a circuit layer 409, and the circuit layer 4 The 0 9 system is produced by a conventional circuit formation semi-additive method. Accordingly, the problem to be solved by the present invention is to provide a core board having a higher wiring density by a semi-additive method to form a layered multi-layer circuit board having a thinner and higher wiring density. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the main object of the present invention is to provide a method for manufacturing a high-density double-layer circuit board, the process of which includes

17100 懋.ptc Page 8 1260960 〆 _ Case No. 91138826 邙年Θ月5曰 Amendment _ V. Invention Description (5) Use the semi-additive method to make a double-layer circuit board with high line density. Another object of the present invention is to provide a method of fabricating a high-density double-layer circuit board using the two-layer circuit board as a core circuit board to produce a thin-layered multi-layer circuit board having a thin and high wiring density. Still another object of the present invention is to provide a method of fabricating a high-density double-layer circuit board in which an insulating via is formed in an insulating layer of the two-layer circuit board to electrically connect the two circuit layers. In order to achieve the above object, the present invention provides a method for fabricating a two-layer circuit board, the preferred embodiment comprising: providing an organic insulating layer having a first surface and a corresponding second surface, and Forming at least one blind hole in the organic insulating layer to communicate with the predetermined first conductive layer on the first surface of the insulating layer; then, providing a seed layer on the second surface of the insulating layer And covering the blind hole; further providing a resist layer (resist 1 ay er) on the seed layer, and patterning the resist layer to form a plurality of openings to expose the crystal to be deposited with a circuit layer and a conductive blind hole a layer portion; forming a circuit layer and a conductive via hole on the seed layer in the opening of the resist layer by an electrochemical method; thereafter, removing the resist layer and the seed layer covered thereby, and completing A high line density double layer circuit board. At the same time, the two-layer circuit board can be used as a core circuit board to fabricate a build-up multilayer circuit board. [Embodiment] In order to make the objects, features and effects of the present invention further understand and recognize, the detailed disclosure and the drawings are described in detail below. Of course, the present invention can be implemented in various forms, and the following is merely a preferred embodiment of the present invention.

17] 00 懋 pt pt pt pt pt pt pt pt pt pt pt pt pt pt pt pt pt 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 All are within the scope of the invention. The invention provides a method for manufacturing a high-density double-layer circuit board, which uses the double-layer circuit board as a core circuit board to produce a multi-layer circuit board with light and thin wiring density. The drawing of the present invention is only simple = clear, not drawn according to the actual size, that is, the actual size of the 1 layer in the multilayer circuit board is not reflected, which is described first. . Referring to FIG. 5, a circuit board manufacturing method according to an embodiment of the present invention is a circuit board having two circuit layers, and the circuit board is designed with an electrical conduction blind hole. As shown in Fig. 5A, first, an organic insulating layer 5?2 is provided, and a conductive layer 5? is formed on the first surface 502a. The organic insulating layer 5 〇 2 is made of an organic material, a fiber-reinf 〇rced organic material, or a particle-reinforced organic material, such as an epoxy resin or a polyacetamide. (p〇ly imide), a compound of a bismaleimide triazine (BT) resin, a cyanate ester or a glass fiber thereof; of course, The organic insulating layer 502 can also be formed by laminating different organic materials, and the thickness of the insulating layer can be designed to be less than 5 mm if necessary. The conductive layer 510 may be a metal material or a polymer material filled with a conductive material, such as copper, aluminum, carbon powder-filled epoxy resin, or the like.

17100 懋.ptc page 10 as shown in FIG. 5B, next, the conductive layer 501 is patterned, and a material of the conductive layer 5〇1 is left at a position where the blind hole 50 3 is to be formed, 俾The blind hole 50 3 to be formed is connected to the conductive layer 5 0 1, and then laser blasting, chemical etching or plasma (p 1 asma) money engraving, etc. 1260960 __________91137826 d month C day correction _ V. DESCRIPTION OF THE INVENTION (7) A blind hole 503 is formed on the second surface 5 0 2 b of the insulating layer 502. However, if the material of the insulating layer 502 is a light developing resin (ph 〇t 〇imageab 1 eresi η ), the process preferably exposes, develops, and bakes to form a blind via 503, and then patterns the conductive layer 501. . As shown in Fig. 5C, a circuit layer is formed by a semi-additive method (s e m i - a d d i t i v e ) on the second surface 5 0 2 b of the insulating layer 502. Initially, a seed layer 504 is formed on the insulating layer 502, and the seed layer 504 can be chemical precipitation, electroless plating, physical vapor deposition (physical vapor deposition). Deposition, or chemical vapor deposition, sputtering, etc., wherein electroless copper plating is a preferred choice under the cost of implementation of the present invention. Of course, the seed layer 504 may also be a palladium catalytic particle applied to the electroless plating process or a plurality of metal layers, and in the step of forming the seed layer 504, the formation of the crystal should be avoided as much as possible. The material of the seed layer 504 is also formed on the first surface 5 0 2 a of the insulating layer 502 including the conductive layer 510. Further, a patterned resist layer 505 is disposed on the seed layer 504, which may be a photoresist material or the like. As shown in Fig. 5D, a circuit layer 506 is formed on the seed layer 50 4 by an electrochemical method such as electrowinning or/and electroless plating. The material of the circuit layer 506 is preferably copper. As shown in FIG. 5E, after removing the resist layer 505 and the seed layer 504 covered thereby, a high-density double-layer circuit board using the present invention is completed. In the above-described semi-additive process, the seed layer 5 0 4 is formed.

17100 全懋.ptc Page 11 1260960 MM 91137826^_ L] Φ Year ^ month ( 曰修五五, invention description (8), the surface of the insulating layer 502 can also be roughened first W surface e : = H Increasing the surface of the insulating layer 50 2 and the seed layer 504 or the circuit layer "force. When the thickness of the circuit layer 506 is too thick, if it is necessary, the grinding or etching method may be used to reduce its thick production. - - The second embodiment of the Ϊ ! ! ' ' ' ' 前述 前述 前述 前述 前述 前述 前述 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 一 一 一 一 一 一 一 一 一 一 一 一 一 一 , , , , , , Providing an insulating layer... and forming a patterned conductive sound, 50b 501a, respectively, on the surface of the 曰 电 电 一 5 5 and the second surface 502b, while leaving a conductive place at a position where the blind hole 5 〇 3 is to be formed ^ 501 ' 50 la material, so that the blind hole to be formed to the conductive layer 50 501a. The file is not shown in Figure 6B, and the semi-additive method is used for the insulating layer 502 The first surface 5〇2a and the second surface 50 2b are formed into a seed layer 5〇4 and a barrier sheet 5 0 5° 9 as shown in FIG. 6C, via an electrochemical method such as electroplating or electroless plating. Forming the circuit layer 5 0 6 , 5 0 7 on the first surface 5 〇 2 a and the second surface % of the insulating layer 502 respectively to remove the resist layer 5 0 5 and the crystal covered thereby The layer 5 0 4, that is, the high-density double-layer circuit board of the present invention is completed. In the third embodiment of the present invention, the first surface of the insulating layer 5〇2 may also be used. And the second surface 50b has a patterned circuit layer 501 and a thin conductive layer 5〇1b. As shown in FIG. 7A, the thin conductive layer 5〇\b is preferably a copper junction (copper f0i 1). The thinner the thickness, the better, the thickness is preferably 5 micrometers thick, and a blind hole 5 〇 3X is formed at the thin conductive layer 501b, and the blind hole 503 formed by the 盲 吏 is connected to the conductive layer 5 〇ι.

17100 全懋.ptc Page 12 1260960 . -91137826—Standard Orthodox 5, Invention Description (9) As shown in Figure 7B, the circuit layer is fabricated by semi-additive method, first containing the thin conductive layer 501 b The second surface of the insulating layer 5 0 2 bJi forms a tooth weight 504, and a patterned resist layer 505 is disposed. As shown in FIG. 7C, the circuit layer 5 〇8 is formed on the second surface 5 0 2 b of the insulating layer 502 via an electrochemical method such as an electric ore or a non-electricity method, and the resist layer 5 0 is removed. 5 and its seed layer 504 and the thin conductive stomach layer 5 〇 lb complete another application of the high line density double layer circuit board 7 本 of the present invention. In the four-part embodiment of the present invention, the material of the circuit layer 5 〇6, 507, 508, which is described in %, may not need to completely fill the blind hole 5 〇 3, but only a cover layer. can. As shown in FIG. 8A, a circuit board 500 having a seed layer 5 〇 4 and a resist layer 505 is prepared (please read the 5C picture), and then fabricated by an electrochemical method such as an electric key or an electric clockless method. The circuit layer 509 is on the seed layer 504, and the circuit layer 509 does not fill the blind hole 503. As shown in Fig. 8B, the resist layer 505 and the seed layer 504 covered thereby are removed, i.e., another high-density double-layer circuit board 800 to which the present invention is applied is completed. In the semiconductor package process, the aforementioned two-layer circuit boards 500, 600, 700, and 800 can be applied to flip chip package technology. As shown in FIG. 9A, in a typical flip chip package, a semiconductor wafer 90 provided with a pad 902 is placed on the thin double-layer circuit board 500, and solder bump is used. A solder bump 9 0 3 is electrically connected to the circuit layer 510 of the thin double-layer circuit board 500, and the other side of the chip 910 is oppositely connected to the circuit board 500. A solder ball 905 is implanted on the surface, and a solder mask layer 904 is disposed on the surface of the circuit board 50 to protect the circuit board 500.

17100 Full 懋.ptc Page 13 1260960 Amendment __ Case No. _ 91137826 V. The circuit lines of the invention (10). Furthermore, as shown in FIG. 9B, the circuit layer 510 can also be removed from the circuit board 500 to form another thin double-layer circuit board 500, and, similarly, As shown in FIG. 9C, the wafer 901 is placed on the circuit board 500 π to electrically connect the circuit layer 50 6 on the surface of the circuit board 500 ′ by the bright tin bumps 903. At the same time, solder balls 905 are implanted on the other surface of the circuit board 500' to form another flip chip package. In addition, the above-mentioned double-layer circuit boards 500, 600, 700, 80 0 can also be used as Core circuit board to make a layered (bui Id-up) multi-layer circuit board. Please refer to Figure 1 for the use of the above-mentioned two-layer circuit 500, 800 as the core circuit board. A schematic diagram of a build-up multilayer circuit board produced as shown in FIG. 10A, which is a schematic diagram of a multi-layered four-layer circuit board 1000, which includes a circuit The plate 5 〇〇 and the two-layer structure 1 0 0 1 ; the build-up structure 1 〇〇 1 includes the circuit layer 丨〇〇 2 and the insulating layer 1 0 0 3 , and the circuit of the build-up structure 1 〇〇 1丨〇〇2 is electrically connected to the circuit layer 506 of the core circuit board 500 by the via hole 1 0 0 4. At the same time, as shown in the figure 10B, the double-layer circuit board 8 〇示意图A schematic diagram of a layered six-layer circuit board fabricated as a core circuit board. The six-layer circuit board 100B includes a core circuit board 8 〇〇 and two build-up structures 1; The structure 1 0 0 5 includes the circuit layer 1 〇〇 6 and the insulating layer 1 〇〇 7 , and the circuit layer 1 〇〇 6 of the build-up structure 1 0 0 5 is electrically connected via the via hole 1 〇〇 8 Of course, the above-mentioned multi-layered multi-layer circuit board is not limited to four-layer and six-layer circuit boards, and the high-density double-layer circuit board of the present invention can be used as a core circuit board to manufacture various types of build-up layers. Multilayer circuit board. In summary, the present invention discloses a semi-additive system using line forming.

17100 全懋.ptc Page 14 1260960, _ Case No. 91138826 Howling April 4 < Day __ V. Invention Description (11) As a thin double-layer circuit board process, the thin circuit board can also be used as the core The circuit board is applied to the fabrication of a multi-layered multi-layer circuit board, whereby a multi-layered multi-layer circuit board with a thin and high wiring density can be provided, which also has good reliability. In the meantime, the specific embodiments described above are merely used to exemplify the features and functions of the present invention, and are not intended to limit the scope of the present invention, without departing from the spirit and scope of the present invention. Equivalent changes and modifications made by the disclosure of the present invention should still be covered by the scope of the following claims.

17100 全懋.ptc Page 15 1260960 / _ Case No. 91138826 ι丨月S日修正 _ Simple description of the drawing [Simple description of the drawing] Figure 1 is a schematic diagram of the structure of the multi-layer circuit board in the conventional technology; 2 is a schematic diagram showing the structure of a multi-layer circuit board which is layered in another conventional technique, and FIG. 3A is a schematic diagram of a conventional electroplated via hole structure; FIG. 3B is a conventional technique in which a plating layer is deposited in a depression Schematic diagram of a blind hole structure filled with a filler; FIG. 3C is a schematic diagram of a blind hole structure completely filled with a conductive material in the prior art; FIGS. 4A to 4E are a half of a conventional circuit for making a finer circuit. Schematic diagram of the process of forming a process; FIG. 5A to FIG. 5E are schematic diagrams showing the first embodiment of the method for manufacturing a high-density double-layer circuit board of the present invention; FIGS. 6A to 6C are diagrams showing the high-density double-layer circuit of the present invention. A schematic diagram of a second embodiment of a method for manufacturing a board; FIGS. 7A to 7C are diagrams showing a third embodiment of a method for manufacturing a high-density double-layer circuit board of the present invention; FIGS. 8A and 8B are diagrams showing a high line density of the present invention. The fourth embodiment of the method for manufacturing a layer circuit board 9A is a schematic view showing the structure of a high-density double-layer circuit board of the present invention applied to a flip chip package; FIG. 9B is a schematic view showing another embodiment of the high-density double-layer circuit board of the present invention; The utility model utilizes the two-layer circuit board shown in FIG. 9B to apply to the structural diagram of the flip chip package;

17100 全懋.ptc Page 16 1260960 _ Case No. 91138826 M + Year of the Moon ~ ^ Correction _ Schematic diagram of the 10th diagram of the present invention, the high line density double-layer circuit board is applied to the layered four-layer circuit The schematic diagram of the structure of the board; and the 10th drawing is a schematic diagram of the structure of the high-density double-layer circuit board of the present invention applied to the layered six-layer circuit board. [Major component symbol description] 100, 2 0 0, 400 build-up multilayer circuit board 101, 401 core circuit board 102, 2 0 2, 411, 1001, 1005 build-up structure 103, 106, 2 0 3, 2 0 6, 3 0 2, 3 0 3, 3 0 7, 3] 3 1 2, 40 2, 4 0 9, 5 0 6, 50 7, 5 0 8, 5 0 9, 1 0 0 2, 1 0 0 6 Circuit Layers 104, 107, 2 04, 207, 301, 306, 310, 4 0 5, 5 0 2 insulating layers 105, 108, 2 0 5, 404, 1004, 1008 conductive vias 201, 500, circuit board 208 vias 3 0 5, 309 filler 308 plating 313 conductive material 40 3, 5 0 2, 1003 , 1007 insulating layer 4 0 6, 503 blind hole 407 electroless copper thin layer 408, 505 resistive layer 410 open V 501 conductive layer / circuit layer 5 0 2a first surface 5 0 2b first — surface

17100 全懋.ptc Page 17 1260960 Case No. 91138826 Month C. Corrective Schematic Description 504 5 0 0,6 0 0,7 0 0,8 0 0,5 0 0,, 501a, 501b 901 902 903 904 905

1 0 0 0 A 1 0 0 0 B seed layer double-layer circuit board conductive layer semiconductor wafer pad solder bump bump insulation layer tin ball board board road electric layer layer four

17100 懋.ptc第18页

Claims (1)

1260960 _ Case No. 91138826 6th month k-day correction _ VI. Patent application scope 1. A method for manufacturing a high-density double-layer circuit board, the steps of which include: providing an organic insulating layer having a first surface and corresponding a second surface, and at least one blind hole is formed in the organic insulating layer to communicate with a predetermined first conductive layer on the first surface of the insulating layer; a seed layer is disposed on the insulating layer a second surface of the layer and covering the blind via; a resist layer is disposed on the seed layer, and the resist layer is patterned to form a plurality of openings to expose a circuit layer to be deposited and conductive blind a portion of the seed layer of the hole; forming a circuit layer and a conductive via hole on the seed layer in the opening of the resist layer by an electrochemical method; and removing the resist layer and the seed layer covered thereby. 2. The method of claim 1, wherein the second surface of the organic insulating layer is roughened before the seed layer is disposed. 3. The method of claim 1, wherein the blind vias are respectively formed on the first surface and the second surface of the organic insulating layer, and the germanium is electrically connected to the opposite surface. Conductive layer on top. 4. The method of claim 1, wherein the surface of the insulating layer may have a thin conductive layer. 5. The method of claim 1, wherein the conductive layer in the blind via fills the blind via. 6. The system for high-density double-layer circuit boards as claimed in item 1 of the patent application 17]00 Full 懋.ptc Page 19 1260960 / ____ Case No. 91138826 ^: Month V Day Amendment _ 6. Patent application scope method, in which the conductive layer in the blind hole covers only the surface of the blind hole. 7. The method of claim 1, wherein the double-layer circuit board can be used as a core circuit board to form a build-up multilayer circuit board. . 8. The method of claim 1, wherein the conductive layer is a metal conductive layer. 9. The method of claim 1, wherein the seed layer can cover all of the blind vias and the remaining non-blind via regions. 1 0. The method of claim 1, wherein the seed layer can partially cover the blind hole and the remaining non-blind hole regions. 1 1. The method of claim 1, wherein the seed layer is electroless copper. 1 2 . The method of claim 1, wherein the seed layer is a s p u 11 e r copper. The method of claim 1, wherein the seed layer is formed by metal particles (p a r t i c 1 e ). 1 . The method of claim 1, wherein the electrochemical method is any one of electroless plating and electroplating. 1 5 . The method of claim 1 , wherein the electrochemical method is an electroless plating method and an electroplating method. 17100 全懋.ptc Page 20 1260960 〆 _ Case No. 9Π37826" Month s day Amendment Six's patent application scope Use each other. 17100 全懋.ptc Page 21 1260960 -一_fjmjl7826 44 years of the month 5曰 Amendment__ IV, Chinese invention summary (invention name: high line density double-layer circuit board method) A high line density double-layer circuit board The method mainly comprises providing an organic insulating layer having a first surface having at least one blind hole, and a bottom of the blind hole communicating with a predetermined first conductive layer on the first surface of the insulating layer; a seed layer is disposed on the surface, and the seed layer covers the blind hole in whole or in part; then, a resist layer is disposed on the seed layer, and The resist layer includes at least one opening in the blind hole; electrochemically forming a circuit layer in the resist layer opening; thereafter, removing the resist layer and the seed layer covered thereby, and completing a high line density Double layer circuit board. At the same time, a remote double-layer circuit board can be used as a core circuit board for making a build-up multilayer circuit board. Representative diagram of the case: Figure 5E Figure 500 Double-layer circuit board 50 1 Circuit layer 5 0 2 Insulation layer 5 0 6 Circuit layer + six, English hair ^^~~ (Invention name: METHOD FOR FORMING HIGH DENSITY BI-LAYER CIRCUIT^ BOARD An organic insulating layer is formed with at least a blind via therethrough, the bottom end of the blind via is connected to a second conductive layer formed on a second surface of The circuit board. A seed layer is applied over a first surface of the circuit board and fully or partial 1y covers the 17100 懋.ptc Page 2