TW200412219A - Method for forming high density bi-layer circuit board - Google Patents

Abstract

A method for forming high density bi-layer circuit board is proposed. An organic insulating layer is formed with at least a blind via therethrough, wherein the bottom end of the blind via is connected to a second conductive layer formed on a second surface of the circuit board. A seed layer is applied over a first surface of the circuit board and fully or partially covers the blind via. Then a patterned resist layer is applied over the seed layer and formed with at least an opening corresponding in position to the blind via. After a first conductive layer is formed within the blind via by an electrically chemical method, the resist layer and the seed layer underneath the resist layer are removed to form a high density bi-layer circuit board.

Description

200412219 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a high-line-density double-layer circuit board, and also relates to a core circuit board for manufacturing a multi-layer multi-layer circuit board. In the manufacturing method, the double-layer circuit board is formed by using an organic insulating layer and including at least a conductive layer or a circuit layer on one surface, and a semi-additive process (SAP) on the other surface. ) Forming a circuit layer, and forming an electrically conductive blind hole in the insulating layer of the double-layer circuit board to provide electrical connection of the conductive layer. [Previous technology] The miniaturization of electronic products has been a well-known trend for a long time, such as mobile phones, laptops, portable video recorders or personal digital assistants. Therefore, the production of these electronic products requires the use of smaller and thinner circuit boards and electronic components than before. With this trend of miniaturization, semiconductor components with various functions are mounted on a circuit board. The need for density. Therefore, for the application of the above-mentioned thinner and higher wiring density multi-layer circuit boards to electronic products, the process and design of circuit boards will face higher challenges. In the circuit board manufacturing industry, low cost, high reliability and high wiring density have always been the goals pursued. To achieve this goal, a layering technology (bu i 1 d-up) was developed. The so-called build-up technology basically refers to stacking multiple insulating layers and conductive layers alternately on the surface of a core circuit board, and then manufacturing electrical vias (via ο 1 es) on the insulating layer to provide between conductive layers. Electrical connection. However, the number of layered circuit boards can be stacked more than 10 or 20 layers depending on the actual industry situation. To date

Page 5 17100.ptd 200412219 V. INTRODUCTION TO THE INVENTION (2) The technology of electronic boards has produced many multi-layer circuit boards with various types of electronic components' to be used in various commercial products. In general, a single-layer, double-panel, or multi-layer board is used as the core substrate for manufacturing the build-up circuit board, that is, the core circuit board. Schematic diagrams of a conventional multi-layer circuit board are shown in Figs. 1 and 2. Please refer to the figure. A layered multi-layer circuit board 100 includes a core circuit board 101 and two layered structures. 27 The two-core circuit board 101 includes a number of patterned circuit layers, and Bit I serves as the insulating layer 104 between the circuit layers 103. A conductive via 105 is used as electrical interconnection between the circuit layers 1 ·. The build-up structure 10 also includes multiple layers of the circuit layer 10 and the insulating layer 107. However, the circuit layer of the build-up structure 10 is 0; the circuit layer 6 is more than the circuit of the core circuit board 1Q1 The layer 1Q3 and the insulating layer m are usually in the evening. The circuit layers 106 of the build-up structure 102 are electrically connected through conductive vias overnight. Take Figure 1 as an example, the core circuit board 1 〇 1 ::] circuit board (that is, six layers), and the layer-increasing structure 102 has two valleys. = See Figure 2 'for another conventional multi-layer circuit board: : One increase: Multi-layer circuit board 2 0 0 contains-circuit board 201 as the core Pan # The core circuit board 201 contains two patterned ft edge layers 2 0 4. -The conductive vias 205 are used as electrical connections between the electrical f layers 203. The circuit layer of the build-up structure 20 is a circuit layer of the build-up structure 200, and the via layer 206 is a through-hole 208 (vi as).

17100. ptd page 6 200412219 V. Description of the invention (3) Electrical connection. In the second figure, the circuit board 201 is a multi-layer circuit board (that is, two layers), and the layer-increasing structure 2 02 is above and below the circuit board 2 01, and each has two layers. In this way, a six-layer circuit board structure is formed. In order to achieve a more reliable process of designing vias in a multilayer circuit board, Figure 3 shows three types of via processes commonly used in the industry. Figure 3A is a schematic diagram of a commonly known as plated-through hole (PTH). The opening of the through hole extends through the insulating layer 3 0 1 and the circuit layers 3 2 and 3 3 covering the surface, and a conductive layer composed of electroplated metal 3 0 4 is formed on the side wall of the through hole. After the electroplating is completed, a conductive or non-conductive filler material 3 5 5 is filled to fill the remaining gaps to ensure the reliability of the vias. Figure 3B shows another form of through-hole, the so-called blind hole (b 1 ind v i a), in which the opening of the blind hole extends into the insulation layer 3 06 but does not penetrate the circuit layer 307. After the plating layer 308 is deposited, a conductive or non-conductive material 309 is filled in the recess to provide proper flatness for subsequent processes. Figure 3C shows a third type of through-hole, in which the opening of the blind hole extends through the insulating layer 3 1 0 but does not penetrate the circuit layer 3 1 1. After the through holes are filled with the conductive material 3 1 to 3, a circuit layer 312 is formed. The above-mentioned first and third conventional techniques need to be filled in the gaps of the filling materials in the through holes (thr ughh ο 1 e). However, when the effective through hole diameter is less than 0.05 mm, the manufacturing process will change. Too difficult to implement. Therefore, in the general industry, when mass production is performed, the above-mentioned first and third conventional processes must be implemented when the diameter of the through hole is more than 0.75 mm, which makes the manufacturing feasibility much easier. In this case, the core circuit board will not be able to meet the requirements of higher wiring density due to the process technology limitations of the vias.

17100.ptd Page 7 200412219 V. Explanation of the invention (4) Compared with the traditional substrac ΐ ive etching method, the industry currently adopts an additive method that can produce finer lines in order to respond to more For high-density circuit boards, this method can be further divided into two processes, a full-additive method and a semi-additive method. A typical semi-additive method is to form a seed layer (s e d 1 a y e r) on an insulated circuit board by electroless copper, and then directly form a circuit layer on the seed layer. The typical process of the semi-additive method that can be used to make thinner circuits is shown in Figure 4. First, referring to FIG. 4A, a core circuit board 401 includes a patterned circuit layer 402, an insulation layer located between the two circuit layers 402, and a conductive passage for electrical interconnection between the circuit layers. Hole (plated-through hole) 4 0 4. Two organic insulating layers 405 are provided and bonded to the surface of the core circuit board 401 by vacuum, as shown in FIG. 4B. Next, referring to FIG. 4C, a plurality of blind holes 406 are formed on the organic insulating layer 405, and an electroless copper thin layer 407 is formed on the surface of the organic, insulating layer 405. A patterned resist iayer 408 is disposed on the copper 407. Then, the circuit layer 409 is formed by electroplating in the resist opening 4i0, as shown in FIG. 4D. After that, after removing the resistance layer 408 and a part of the electroless copper thin layer 407, a layered four-layer circuit board 400 is completed. As shown in FIG. 4E, the four-layer circuit board The 4 0 0 series includes a core circuit board 40 and a two-layer structure 41 1. The layer-added structure 411 series includes an organic insulating layer and a circuit layer 4 0 9, and the circuit layer 4 0 9 is a conventional one. It is made by the semi-additive method of circuit formation.乂 Therefore, the problem to be solved by the present invention is to provide a core circuit board with more local wiring density, which is formed—thinner and higher

200412219 V. Description of the invention (5) Layer-increasing multi-layer electricity of wiring density [Summary of the Invention] The above-mentioned conventional technique provides a step of a semi-additive method for high-line-density double-layer to make another object of the present invention The manufacturing method is to use the double-layer electric thin layer and increase the wiring density. Another object of the present invention: The manufacturing method is to use the double-layer circuit hole to achieve the above-mentioned electrical properties between the two circuit layers. The method of the road board preferably has a first surface and a corresponding second conductive layer with at least one blind hole formed in the method. Then, the first surface of the edge layer is provided and covered with a resist iayer. K The seed layer_exposed on the resist layer; the seed layer covered by the resist is not covered on the seed layer, complete @ 日 寺 'can also use the dual (core circuit board) power port Road boards. Slightly. Disadvantages of the technology, the circuit board manufacturing high line density provides-a high circuit board as a core multi-layer circuit to provide a high board insulation layer connection. The invention provides a step comprising: a second surface

The main purpose of the issue of the sun and the moon is the method ', and its manufacturing process includes a double-layer circuit board. 2, circuit density double-layer circuit board core circuit board to make a light board. The line density double-layer circuit board is formed with electrical continuity I and is placed on the blind layer through a layer of a high-level electricity to make the insulating seed layer L; and then to make electricity 4 credits; The board is used as a layer to provide one, and after the edge layer (seed) is provided with the blind hole method, the shift double layer is used as a core to make a double-layer electrical organic insulating layer. A layer) is provided on the insulating patterned resistive layer and a first conductive layer covering the readout resistive layer and a circuit board covered thereon. Heart circuit board type (build, up) multilayer electrical

17100.ptd

200412219 ~ — ~ —__ V. Explanation of the invention (6) [Method of corruption] In order to make the purpose of the present invention agree, we will cooperate with the detailed disclosure and detailed drawings. The step-by-step month can be implemented in various forms. The second: after. Of course, the examples are only examples, rather than limiting the present invention. The preferred embodiments of the present invention belong to A, and 疋 is attached to the present invention. It belongs to the scope of the present invention. + Shiyue's Ben Sheming provided "— a kind of 纟 φ using this double-layer circuit board as a nuclear second power: KJ circuit board manufacturing method, 俾 :: line-density multi-layer multilayer circuit board = = = thin and with The actual dimensions at a high level are described first. ~ 'Each layer of circuit board, see FIG. 5, which is a circuit board according to an embodiment of the present invention "is a circuit board with two circuit layers (丨, private method, Tuo Ni Bu, rcui seven layer), The emperor's old board is designed with electrical conductive blind holes. As shown in Figure _5A, first, an organic insulating layer 502 is provided, and i = two surfaces 5 0 2a are formed. The conductive layer 501. The organic insulating layer 502 is made of mechanical materials, fiber-reinf rced organic materials or particles, and reinforced (part l cl e-reinfo reed) organic materials, such as epoxy. Resin (epoxy Γ esi η), polyethylenimine (p 0 1 yimide), bis-cisbuteneimine / triazine (bisma 1 eimidetriazine, BT) resin, cyanate ester or its glass fiber ( glass fiber) of the composite material temple, of course, 'the organic insulating layer 502 can also be formed by stacking different organic materials, and the thickness of the insulating layer can also be designed below 0.05 mm if necessary. And the The conductive layer 501 may be made of metal or filled with a conductive substance.

17l〇〇. Ptd page 10 200412219 V. Description of the invention (7) 咼 molecular materials, such as copper, Shao, carbon-filled epoxy resin and so on. As shown in FIG. 5B, the conductive layer 501 is patterned, and a material of the conductive layer 501 is left at the position where the blind hole 50 3 is to be formed, so that the blind hole 5 to be formed is made. 0 3 can be connected to the conductive layer 5 0 1 'and then use laser blasting, chemical engraving or plasma (p 1 asma) rhyme engraving to form a blind on the second surface 5 0 2 b of the insulating layer 5 0 2 Hole 5 0 3. However, if the material of the insulating layer 502 is a photo-imaging resin (ph 〇〇〇〇〇〇 in ageab 1 eresir〇), it is best to first exposure (exposure), development, baking to form a blind hole 503, and then pattern the conductive layer 501. As shown in FIG. 5C, a semi-additive method is used to make a circuit layer on the second surface 5 0 2 b of the insulating layer 50 2. At first, it is tied to the insulating layer 5 0 A seed layer 5 0 4 is formed on 2, and the seed layer 50 4 can be chemically deposited, electroless plating, physical vapor deposition, or chemical vapor deposition. Phase deposition (chemical vapor deposition), sputtering (sputter) and other methods, in which electroless copper should be a better choice under the consideration of β implementation cost of the invention. Of course, the seed layer 504 can also be applied to The electroless palladium catalyzed particles may be formed by stacking multiple metal layers. In the step of forming the seed layer 504, the formation of the seed layer 504 should be avoided as much as possible. 0 1 of the insulating layer 5 0 2 A surface 5 0 2 a. A patterned resist layer 505 is disposed on the seed layer 5 0 4, which may be a photoresist material. As shown in FIG. 5 D, Use of electrochemical methods such as electroplating or / and

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V. Description of the invention (8) A plating layer is used to form a circuit layer 506 on the seed layer 504. The circuit layer 506 is made of copper. As shown in FIG. 5E, after removing the resist layer 505 and the seed layer 504 covered by the resist layer 505, a high-line-density double-layer circuit board 504 using the present invention is completed. In addition, in the above-mentioned semi-additive process, the surface of the insulating layer 502 may be subjected to surface roughening (surface yughenmg) before opening the seed layer 5 η to increase the insulating layer 5 0 2 The bonding force between the surface and the seed layer 504 or the electric layer 506. Alternatively, when the thickness of the circuit layer 506 is too thick, the grinding or etching method can also be used to reduce the thickness of the circuit layer. In the second embodiment t ′ of the present invention, a double-layer electrical layer can also be formed by using a semi-additive method on the insulating layer 50 2 bis—the surface 5 0 2 a and the second surface 50 2 b. As shown in the figure, the "first" is provided-the insulating layer 5 0 2, and the _ patterned conductive layer 50 is formed on each of its fy table = 5 0 2 a and the second surface, and is left at the same position as the blind hole 5Q3. The conductive layer to ## 5 ^ 1 ^ 的 ^ 彳 贝 allows the blind holes 503 to be formed to communicate with the main conductive layers 501, 501a, respectively. As shown in the sixth tone, the seed layer 504 and the resist layer are made by using the first surface 5 center and the second surface 5 半 of the above-mentioned half addition 5Ϊ, as shown in FIG. 6C. A. Electrochemical methods such as thermal plating, the first surface $ n 9 ^ # of the insulating layer 5 0 2 is formed on the surface of Cheng Tai a and the second surface 5 0 2 b to form a circuit layer 5 0 6, 5 0 7 Remove the sound blocking layer S "“ — save b 0 5 and the seed crystal covered by it b 0 4, and complete another application of the ancient φ < return circuit density double-layer circuit board of the present invention

17100

Ptd

200412219 V. Description of the invention (9) 6 0 0 ° In the third embodiment of the present invention, the first surface 502 a and the second surface 502 b of the aforementioned insulation j 5 0 2 may each have a patterned circuit. Layer 501 and a thin conductive layer 501b. As shown in FIG. 7A, the thin conductive layer 501b is preferably made of copper foil (copperf oi 1). The thinner the thickness, the better, preferably 2 to 5 microns thick. A blind hole 5 0 3 is formed at 1 b, so that the blind hole 5 0 3 to be formed can communicate with the conductive layer 5 0 1. As shown in FIG. 7B, a semi-additive method is used to fabricate a circuit layer. A seed layer 5 0 4 is formed on the second surface 5 0 2 b of the insulating layer containing the thin conductive layer 5 0 1 b. Lay out a patterned resistive layer 5 0 5. As shown in FIG. 7C, a circuit layer 5 0 8 is formed on the second surface 5 0 2 b of the insulating layer 5 0 2 by an electrochemical method such as electroplating or electroless plating, and then the resistive layer 5 0 5 is removed. With the seed layer 5 0 4 and the thin conductive layer 5 0 1 b covered thereon, another high-layer-density double-layer circuit board 7 0 0 of the present invention is completed. In the fourth embodiment of the present invention, the material on the aforementioned circuit layers 506, 507, and 508 does not need to completely fill the blind hole 503, but is only a covering layer, that is, _ inch. . As shown in FIG. 8A, a circuit board 5 0 0 ′ having a seed layer 5 0 4 and a resistance layer 5 0 5 is prepared (see FIG. 5 C), and then an electrochemical method such as electroplating or A circuit layer 509 is fabricated on the seed layer 504 by electroplating, and the circuit layer 509 does not fill the blind hole 503. As shown in FIG. 8B, the resist layer 5 05 and the seed layer 5 4 covered by the resist layer 5 5 are removed to complete another high-line-density double-layer circuit board 8 Q Q to which the present invention is applied. In the semiconductor package manufacturing process, the aforementioned double-layer circuit board can be used.

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200412219 V. Description of the invention (11) ^ As shown in Figure 10β of the same scholar, the double-layer circuit board 8 0 0 is used as the core = circuit board, and the multi-layer six-layer circuit board made by ηΓ is 1 0 0 0 Β schematic diagram. The six-layer circuit board 1000B includes a core and a two-layer build-up structure 105, which includes a circuit circuit / anti-800 and a two-layer build-up structure 1005; the structure 10. The second circuit layer of 5: 1.06 is connected to the insulating layer 10 0 7, and the additional layer is connected. Of course, the above-mentioned increased vias 108 are used for mutual electrical connection of circuit boards, and can also be used. Circuit boards are not limited to four-layer and six-core circuit boards. , +, And clothing are awarded multi-layer circuit boards. Zuo-two thin double Ϊ ί ::: Expose the semi-additive method using circuit forming. Thin and high wiring = board production, this is OK; reliability. The same day temple, “ta-layer multilayer circuit board” which also has good identifiable features. Points and functions: The specific embodiment of 1 is only used to illustrate the bamboo shoots without departing from the description of the present invention and is not intended to be limiting The implementation of the present invention can be described, and the content of the disclosure is complete: the spirit and technology of the mouth are used. Any application of the present invention, please apply for a patent. Lu

200412219 Schematic illustration [Schematic description] Figure 1 shows the structure of a multilayer circuit board in the conventional technology; Figure 2 is a schematic diagram of the structure of a multilayer circuit board in another conventional technology; Figure A is a schematic view of the structure of a plating via hole in the conventional technology;-Figure 3B is a schematic diagram of a blind hole structure filled with a filling material after the plating layer is deposited in the conventional technology; Figure 3C is the conventional technology Schematic diagram of blind hole structure completely filled with conductive material. Figures 4A to 4E are not intended for the semi-additive process used to make thinner circuits in the conventional technology. Figures 5A to 5EBM are the present invention. Schematic diagram of the first embodiment of the method for manufacturing a high-line-density double-layer circuit board; FIGS. 6A to 6C are schematic diagrams of the second embodiment of the method for manufacturing a high-line-density double-layer circuit board according to the present invention; Figure 7C is a schematic diagram of the first embodiment of the method for manufacturing a high-line-density double-layer circuit board according to the present invention; Figures 8A and 8B are schematic views of the fourth embodiment of the method for manufacturing a high-line-density double-layer circuit board according to the present invention; Lu 9A is the high line density of the present invention Schematic diagram of the structure of a double-layer circuit board applied to a flip-chip package; Figure 9B is not intended for another embodiment of the high-line-density double-layer circuit board of the present invention; Figure 9C is the use of the double shown in Figure 9B Layer circuit board for flip chip application

17100.ptd Page 16 200412219 Schematic illustration of the structure of the package; Figure 1 ο A is a schematic diagram of the structure of the high-line-density double-layer circuit board of the present invention applied to a build-up four-layer circuit board; and 1 0 B FIG. Is a schematic structural diagram of a high-line-density double-layer circuit board of the present invention applied to an increased-layer six-layer circuit board. 100, 200, 400 Multilayer circuit board 101,401 Core circuit board 1 02, 2 0 2, 4 1 1, 1 0 0 1, 1 0 0 5 Layer structure 103, 106, 203, 206, 302, 303, 307, 311, 312, 402, 409, 506, 50 7, 5 0 8, 5 0 9, 1 0 0 2, 1 0 0 6 circuit layer 1 0 4, 1 0 7, 2 0 4, 2 0 7, 3 0 1,3 0 6,3 1 0,4 0 5,5 0 2 Insulating layer 105, 108, 205, 404, 1004, 1008 Conductive through-hole Circuit board through-hole filling material Plating layer Conductive material Insulating layer Blind hole Unplated copper thin layer Resistive layer opening conductive layer / circuit layer 2 0 1,5 Q 0 '208 305, 309 3 0 8 ·, 313 403, 502, 1003, 1007 406,503 407 408,505 410 501

17100. ptd page 17 200412219 Simple illustration of the diagram 5 02 a 5 0 2 b 504 5 0 0, 6 0 0, 7 0 0, 8 0 0, 5 0 0 501a, 501b -901 902 903 904

1U0 0A 1 0 0 0 B First surface Second surface Seed layer Double-layer circuit board Conductive layer Semiconductor wafer Welding pad Solder bump Insulation protection layer Tin ball board Board circuit Electrical layer

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Claims (1)

200412219 1. The scope of application for patent 1. A method for manufacturing a south-line density double-layer circuit board, the steps of which include providing an organic insulating layer, which has a first surface and a corresponding second surface 1 and is provided on the organic insulation. At least one blind hole is formed in the layer to communicate with a predetermined second conductive layer on the second surface of the insulating layer, and a seed layer is placed on the first surface of the insulating layer and covers the A blind hole, en. Δ is further provided with a patterned resist layer (resist 1 ay (3Γ;)) on the seed layer, and the blind hole and the seed layer covering it are exposed to the resist layer, and by electrification Method to form a first conductive layer on the seed layer without covering the resist layer portion 9 and remove the resist layer and the seed layer covered by the resist layer. ^ 1 circuit board manufacturing method, wherein the first surface of the organic insulating layer The surface can be roughened before the layer. For example, the patent 々 / Γ Chapter 巳 of the high-line-density double-layer circuit board manufacturing method, where j the blind hole can also be formed in the organic insulating layer. One surface k and the second surface 俾 are electrically connected to the conductive layer on the other surface. 4. Please refer to the patent for the method for manufacturing a high-line-density double-layer circuit board of the first item of Arhr, Chapter 1, where 1 The surface of the insulating layer may also have A thin conductive layer 〇5. As claimed in the patent / τλτ Chapter 1 High-density double-layer circuit board manufacturing method wherein the conductive layer in the blind hole fills the blind hole 〇6. Patent scope as requested The manufacturing method of the high-line-density double-layer circuit board of item 1, wherein the conductive layer in the blind hole covers only the surface of the blind hole. 17100.ptd Page 19 200412219 VI. Application for patent scope 7. For the manufacturing method of the high-line-density double-layer circuit board under item 1 of the patent scope, where the double-layer circuit board can be used as a core circuit board (Qcore circuit board), In order to make a multilayer multilayer circuit board. 8. The method for manufacturing a high-line-density double-layer circuit board according to item 1 of the application, wherein the conductive layer is a metal conductive layer. . For example, the method for manufacturing a high-line-density double-layer circuit board according to item 1 of the patent application scope, wherein the seed layer can completely cover the blind hole and the remaining non-blind hole areas (f u 1 1 y). 10. The manufacturing method φ of a high-line-density double-layer circuit board according to item 1 of the patent application scope, wherein the seed layer may partially cover the blind hole and the remaining non-blind hole areas. 11. The method for manufacturing a high-line-density double-layer circuit board according to item 1 of the application, wherein the seed layer is electroless copper. 12. The method for manufacturing a high-line-density double-layer circuit board according to item 1 of the scope of patent application, wherein the seed layer is Tibetan plated (s p u 11 e r) copper. 1 3. According to the method for manufacturing a high-line-density double-layer circuit board according to item 1 of the scope of patent application, the seed layer is composed of feminine metal particles (P artic 1 e) in the scope of patent application. 1 4. The method for manufacturing a high-line-density double-layer circuit board according to item 1, wherein the electrochemical method is any one of an electroless plating method and a plating method. 15. The method for manufacturing a high-line-density double-layer circuit board according to item 1 of the scope of patent application, wherein the electrochemical method is an interactive use of electroless plating method and electroplating method. 17100.ptd Page 20