JP2006303338A - Multilayer circuit board and its manufacturing method - Google Patents

Multilayer circuit board and its manufacturing method Download PDF

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JP2006303338A
JP2006303338A JP2005125945A JP2005125945A JP2006303338A JP 2006303338 A JP2006303338 A JP 2006303338A JP 2005125945 A JP2005125945 A JP 2005125945A JP 2005125945 A JP2005125945 A JP 2005125945A JP 2006303338 A JP2006303338 A JP 2006303338A
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circuit board
conductor
bump
layer
plating
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Noboru Shinkai
昇 新開
Katsuro Aoshima
克郎 青島
Yogo Takahashi
要吾 高橋
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J MACC CO Ltd
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MACC CO Ltd J
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MACC CO Ltd J
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a novel multilayer circuit board with at least one of its surfaces smooth and having a conductive structure between layers formed of a highly reliable columnar conductor. <P>SOLUTION: The multilayer circuit board P has an integral structure with a plurality of circuit boards laminated. At least one of its surfaces is a smooth surface with a land and a conductor circuit leveled with the surface. At least one of conductive structures connecting an upper-layer circuit board 1 with a lower-layer circuit board 2 is made of the columnar conductor 5, including a tip of a bump conductor 5<SB>1</SB>protruding from the lower surface of the upper-layer board 1 and a tip of a bump conductor 5<SB>2</SB>protruding from the upper surface of the lower-layer board 2 coupled directly or via a conductive material. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は多層回路基板とその製造方法に関し、更に詳しくは、部品の実装面が平滑面であり、かつ部品の高密度実装が可能であり、そして層間の導通構造の信頼性が高い新規な多層回路基板とその製造方法に関する。   The present invention relates to a multilayer circuit board and a method for manufacturing the same, and more particularly, a novel multilayer having a smooth mounting surface for components, high-density mounting of components, and high reliability of a conductive structure between layers. The present invention relates to a circuit board and a manufacturing method thereof.

コンピュータ、携帯用通信機器、液晶パネルなどの各種電子機器に組込まれる半導体素子パッケージは、所定の半導体部品を回路基板に実装し、全体を樹脂モールドした構造になっている。
そして、最近では電子機器の小型化、高速化、多機能化が顕著に進んでいるが、このことに対応して半導体部品の高密度実装が可能で、ファインな導体回路パターンを備えた回路基板への要請が強い。
A semiconductor element package incorporated in various electronic devices such as computers, portable communication devices, and liquid crystal panels has a structure in which a predetermined semiconductor component is mounted on a circuit board and the whole is resin-molded.
Recently, electronic devices have been remarkably miniaturized, speeded up, and multi-functionalized. Corresponding to this, high-density mounting of semiconductor components is possible, and circuit boards with fine conductor circuit patterns The request to is strong.

このような要請に対応できる回路基板としては、複数の単位回路基板を積層した構造の多層回路基板が好適である。
この多層回路基板の製造方法としては、各種の方法が提案されているが、いずれにおいても、下層の回路基板と上層の回路基板の間に導通構造を形成することが必要である。
例えば、所定の導体回路パターンが形成されている下層回路基板のランド部にAgぺーストをパターン印刷して、そこに突起形状をしたバンプ導体を形成し、この下層回路基板と積層すべき上層回路基板の間に、両面に接着剤層が形成されている電気絶縁性のフィルムを配置し、全体を熱圧プレスすることにより、バンプ導体でフィルムを突き破らせ、そのバンプ導体を上層回路基板のランド部に接合させて上層と下層間の導通構造を形成する方法がある。
As a circuit board that can meet such a demand, a multilayer circuit board having a structure in which a plurality of unit circuit boards are stacked is preferable.
Various methods have been proposed as a method for manufacturing this multilayer circuit board. In any case, it is necessary to form a conductive structure between the lower circuit board and the upper circuit board.
For example, an Ag paste is printed on a land portion of a lower circuit board on which a predetermined conductor circuit pattern is formed, a bump conductor having a protruding shape is formed thereon, and an upper circuit to be laminated with the lower circuit board An electrically insulating film having an adhesive layer formed on both sides is placed between the substrates, and the whole is hot-pressed to break through the film with bump conductors, and the bump conductors are connected to the upper circuit board. There is a method of forming a conduction structure between an upper layer and a lower layer by bonding to a land portion.

また、多層回路基板の製造方法としては、ビルドアップ工法が広く実施されているが、この方法の場合、下層回路基板の導体回路やそのランド部を所定厚みの絶縁層で埋設し、ついでこの絶縁層の表面から下層回路基板の導体回路の表面にまで至るレーザビアを穿孔し、無電解めっきと電気めっき法によって、そのレーザビアの内壁、絶縁層の表面にCuめっき層を形成したのち、ビア内の凹部に絶縁材または樹脂材を充填し、全面に再び電気めっき法でCuめっき層を形成し、そしてこのCuめっき層を所定パターンの導体回路に加工して目的とする上層回路基板を形成している。この場合、下層回路基板と上層回路基板の間には、ビアホール内の内壁に形成されたCuめっき層で導通構造が形成されている。   As a method for manufacturing a multilayer circuit board, a build-up method is widely used. In this method, the conductor circuit of the lower circuit board and its land are embedded with an insulating layer having a predetermined thickness, and then this insulation is performed. After drilling a laser via from the surface of the layer to the surface of the conductor circuit of the lower circuit board, and forming a Cu plating layer on the inner wall of the laser via and the surface of the insulating layer by electroless plating and electroplating method, Filling the recess with an insulating material or resin material, forming a Cu plating layer on the entire surface again by electroplating, and processing this Cu plating layer into a conductor circuit of a predetermined pattern to form a desired upper circuit board Yes. In this case, a conduction structure is formed between the lower circuit board and the upper circuit board by a Cu plating layer formed on the inner wall in the via hole.

また、レーザビアに導電ペーストを充填し、この導通ペーストで上層と下層の導通構造が形成されることもある。   In addition, a conductive paste may be filled in the laser via and an upper layer and a lower layer conductive structure may be formed by this conductive paste.

最近、多層回路基板においても従来にましてより高密度な部品実装が要求されているが、このことに対応して、層間の導通構造のファイン化が要求されている。
この要求との関係でいうと、フィルムをバンプ導体で突き破って上層と下層の導通をとる方法の場合、突起形状のバンプ導体はAgペーストをパターン印刷して形成されているので、その径は200μm程の比較的大径となり、ファイン化の要請に充分応えることができない。また、そのバンプ導体はフィルムを突き破ることができる程度の強度を保持しなければならないので、例えば50μm程度に小径化できたとしても、それでフィルムを突き破れるとは限らず、熱圧プレス時に折損する虞れがあり、導通構造としての信頼性に欠ける。
Recently, even in multilayer circuit boards, higher-density component mounting is required than before, and in response to this, refinement of the conductive structure between layers is required.
In relation to this requirement, in the method of breaking the film with a bump conductor to make the upper layer and the lower layer conductive, the bump-shaped bump conductor is formed by pattern printing of Ag paste, and its diameter is 200 μm. The diameter becomes relatively large, and it is not possible to sufficiently meet the demand for finer processing. Moreover, since the bump conductor must maintain a strength that can break through the film, even if the diameter can be reduced to, for example, about 50 μm, it does not always break through the film, and breaks during hot press. There is a fear, and the reliability as a conductive structure is lacking.

また、上記したビルドアップ工法の場合、絶縁層表面のCuめっき層は厚くなるので、それを加工してファインな導体回路のパターンを形成することが困難であるという問題がある。そして、導電ペーストをレーザビアに充填する方法で形成された層間の導通構造は、電気特性や信頼性の点で制約がある。
本発明は、このような問題を解決して、ファイン化が可能で、高い信頼性も備えている導通構造を有し、また部品実装に好適な実装面を有する多層回路基板とその製造方法の提供を目的とする。
In the case of the build-up method described above, since the Cu plating layer on the surface of the insulating layer becomes thick, there is a problem that it is difficult to process it to form a fine conductor circuit pattern. And the conduction structure between layers formed by a method of filling a laser via with a conductive paste is limited in terms of electrical characteristics and reliability.
The present invention solves such problems, has a conductive structure that can be refined, has high reliability, and has a mounting surface suitable for component mounting, and a method of manufacturing the same. For the purpose of provision.

上記した目的を達成するために、本発明においては、
複数の回路基板を積層して一体化した構造の多層回路基板において、
少なくとも片側の表面は、ランド部と導体回路が前記表面と面一状態にある平滑面であり、
上層の回路基板と下層の回路基板を接続する導通構造の少なくとも1つは、前記上層の回路基板の下面に突出するバンプ導体の先端部と前記下層の回路基板の上面に突出するバンプ導体の先端部とを、直接または導電材を介して結合した柱状導体から成ることを特徴とする多層回路基板が提供される。
In order to achieve the above object, in the present invention,
In a multilayer circuit board having a structure in which a plurality of circuit boards are stacked and integrated,
At least one of the surfaces is a smooth surface in which the land portion and the conductor circuit are flush with the surface,
At least one of the conductive structures connecting the upper circuit board and the lower circuit board includes a front end portion of the bump conductor protruding from the lower surface of the upper circuit board and a front end of the bump conductor protruding from the upper surface of the lower circuit board. There is provided a multilayer circuit board characterized in that the parts are made of columnar conductors joined to each other directly or through a conductive material.

好適には、
上面にはランド部と導体回路が前記上面と面一状態で形成され、かつ、下面にはバンプ導体が突出している単層または多層の第1回路基板と、
下面にはランド部と導体回路が前記下面と面一状態で形成され、かつ上面にはバンプ導体が突出している単層または多層の第2回路基板とが、絶縁基板を介して接合され、前記絶縁基材内に形成された前記柱状導体の導通構造を有し、かつ両面が平滑面である多層回路基板が提供される。
Preferably,
A single-layer or multi-layer first circuit board in which a land portion and a conductor circuit are formed flush with the upper surface on the upper surface, and a bump conductor protrudes on the lower surface;
A single-layer or multi-layer second circuit board having a land portion and a conductor circuit formed flush with the lower surface on the lower surface and a bump conductor projecting on the upper surface is bonded via an insulating substrate, There is provided a multilayer circuit board having a conductive structure of the columnar conductor formed in an insulating base material and having smooth surfaces on both sides.

また本発明においては、
平滑基板の片面に形成された導電薄層の表面に、複数の回路基板が順次積層され、最後に積層された回路基板の表面には所定の平面パターンでバンプ導体が突出している中間材を製造する工程A;
2個の前記中間材のバンプ導体側の表面を、各表面のバンプ導体の平面パターンに対応してバンプ導体よりも大径の貫通孔が形成されている絶縁基材を介して対向させ、
各バンプ導体を前記貫通孔に挿入したのち全体に熱圧プレスを行なって2個の前記中間材を前記絶縁基材を介して接合することにより一体化構造にすると同時に、前記バンプ導体の先端部を前記貫通孔内で結合する工程B;および
前記一体化構造から、前記平滑基板と前記導電薄層を順次除去する工程C;
を備えることを特徴とする多層回路基板の製造方法が提供される。
In the present invention,
Produces an intermediate material in which a plurality of circuit boards are sequentially stacked on the surface of a conductive thin layer formed on one side of a smooth substrate, and bump conductors protrude in a predetermined plane pattern on the surface of the last stacked circuit board. Performing step A;
The surface on the bump conductor side of the two intermediate materials is opposed to each other through an insulating base material in which a through hole having a larger diameter than the bump conductor is formed corresponding to the planar pattern of the bump conductor on each surface,
After inserting each bump conductor into the through-hole, the whole is subjected to hot-pressing to join the two intermediate members through the insulating base material to form an integrated structure, and at the same time, the tip of the bump conductor In the through-hole; and step C in which the smooth substrate and the conductive thin layer are sequentially removed from the integrated structure;
A method for manufacturing a multilayer circuit board is provided.

その場合、
前記工程Aが、
平滑基板の表面に導体薄層を形成したのち、前記導体薄層の表面を被覆して絶縁層aを形成し、前記絶縁層aに露光・現像処理を行って、ランド部と導体回路を形成すべき箇所の前記絶縁層aを除去して、そこに前記導体薄層が表出している凹部パターンaを形成し、ついで、電気めっき法で、前記凹部パターンaの中に、残置する前記絶縁層aの表面と面一状態になるまでめっき材料を充填してめっき充填部aを形成する工程A1と、
前工程で形成しためっき充填部を含む表面全部を被覆して絶縁層bを形成し、前記絶縁層bに露光・現像処理を行って、ランド部と導体回路を形成すべき箇所の前記絶縁層bを除去し、そこに前記めっき充填部が表出している凹部パターンbを形成し、ついで電気めっき法で、前記凹部パターンbの中に、残置する前記絶縁層の表面と面一状態になるまでめっき材料を充填して新たなめっき充填部を形成することを1回行なうかまたは複数回反復する工程A2と、
工程A2で形成された最後のめっき充填部を含む表面全部を被覆して絶縁層cを形成し、前記絶縁層cに露光・現像処理を行なって、バンプ導体を形成すべき箇所の前記絶縁層を除去し、そこに前記めっき充填部が表出しているバンプ導体用凹孔を形成し、ついで電気めっき法で、前記バンプ導体用凹孔の中にめっき材料を充填したのち、前記絶縁層cを全て除去して、前記めっき充填部の表面にバンプ導体を突設する工程Cとを備えている。
In that case,
Step A is
After forming a thin conductive layer on the surface of the smooth substrate, the surface of the thin conductive layer is covered to form an insulating layer a, and the insulating layer a is exposed and developed to form a land portion and a conductive circuit. The insulating layer a in a place to be removed is removed to form a concave pattern a on which the conductive thin layer is exposed, and then the insulation is left in the concave pattern a by electroplating. A step A 1 of filling the plating material until the surface of the layer a is flush with the surface of the layer a to form the plating filling portion a;
The insulating layer b is formed by covering the entire surface including the plating filling portion formed in the previous step, and the insulating layer b is exposed and developed to form the land portion and the conductor circuit at the location where the conductor circuit is to be formed. b is removed, and the concave pattern b exposed by the plating filling portion is formed therein, and then the surface of the insulating layer to be left in the concave pattern b is flush with the surface of the concave pattern b by electroplating. Step A 2 in which the plating material is filled up to form a new plating filling portion up to one time or repeated a plurality of times;
All surfaces, including the step A 2 last plating filled portion formed in a coated form an insulating layer c, by performing exposure and development on the insulating layer c, the insulation of the portion to be formed a bump conductor The insulating layer is formed after removing a layer, forming a concave hole for a bump conductor exposed by the plating filling portion, and then filling a plating material into the concave hole for the bump conductor by electroplating. and a step C of removing bumps c and projecting bump conductors on the surface of the plating filling portion.

この多層回路基板の導通構造は、上層回路基板の下面に突出するバンプ導体と下層回路基板の上面に突出するバンプ導体のそれぞれの先端部を、絶縁基材の貫通孔の中で熱圧プレスすることにより例えば拡散結合して一体化した柱状導体で構成されているので、この柱状導体は高い結合強度を有し、また絶縁基板の貫通孔の中で遊動することなく固定されていて、導通構造として高い信頼性を備えている。   In this multilayer circuit board conduction structure, the bump conductors projecting from the lower surface of the upper circuit board and the bump conductors projecting from the upper surface of the lower circuit board are hot-pressed in the through holes of the insulating base. Thus, for example, it is composed of a columnar conductor integrated by diffusion bonding, so this columnar conductor has a high coupling strength and is fixed without floating in the through hole of the insulating substrate, and has a conductive structure. As highly reliable.

そして、この多層回路基板は、このバンプ導体の径が最小で10μmという細径にすることが可能であるため、形成された導通構造はファイン化しており、また表面は平滑面になっているので、従来にまして高密度実装が可能となる。   And since this multilayer circuit board can make the diameter of this bump conductor as small as 10 μm, the formed conductive structure is made fine and the surface is smooth. Higher density mounting is possible than before.

図1に、本発明の多層回路基板の一例Pの断面構造を示す。
この回路基板Pは、上層に位置する回路基板1と下層に位置する回路基板2が絶縁基材3を介して接合・一体化され、上層の回路基板1のランド部または導体回路(以後、まとめて導体回路と表現する)41と下層の回路基板2のランド部または導体回路(以後、まとめて導体回路と表現する)42との間の導通は、絶縁基材3の中に形成された後述の柱状導体5でとる構造になっている。
FIG. 1 shows a cross-sectional structure of an example P of the multilayer circuit board of the present invention.
In this circuit board P, the circuit board 1 located in the upper layer and the circuit board 2 located in the lower layer are joined and integrated via the insulating base material 3, and a land portion or a conductor circuit (hereinafter, summarized) of the upper circuit board 1 is joined. The conduction between 41 1 and the land portion of the lower circuit board 2 or the conductor circuit (hereinafter collectively referred to as a conductor circuit) 4 2 is formed in the insulating base 3. In addition, the structure is a column conductor 5 described later.

上層の回路基板1と下層の回路基板2は、いずれも、2層構造の回路基板であるため、この回路基板Pは、柱状導体5を有する絶縁基材3を含めて全体で5層構造の多層回路基板になっている。
そして、この回路基板Pの場合、上層回路基板1の表面1aと下層回路基板2の表面2aに形成されている導体回路は、各回路基板の絶縁層に埋設され、その絶縁層の表面と面一状態でそれぞれの表面に表出しているので、各回路基板1、2の表面1a、2aはいずれも平滑面になっている。
Since both the upper circuit board 1 and the lower circuit board 2 are circuit boards having a two-layer structure, the circuit board P has a five-layer structure as a whole including the insulating base material 3 having the columnar conductors 5. It is a multilayer circuit board.
In the case of this circuit board P, the conductor circuit formed on the surface 1a of the upper circuit board 1 and the surface 2a of the lower circuit board 2 is embedded in the insulating layer of each circuit board, and the surface and surface of the insulating layer Since each surface is exposed in one state, the surfaces 1a and 2a of the circuit boards 1 and 2 are both smooth surfaces.

なお、本発明の多層回路基板にあっては、回路基板Pのように両面が平滑面ではなくてもよく、どちらか一方の表面は平滑面でなくてもよい。しかし、本発明の多層回路基板では、後述する製造工程との関係で、どちらか一方の表面は平滑面になっている。
この回路基板Pにおける最大の特徴は、図1で示したように、上層回路基板1の導体回路41の下面に突出して形成されたバンプ導体51と、下層回路基板2の導体回路42の上面に突出して形成されたバンプ導体52とが、絶縁基材3に形成されている貫通孔3aの中で、互いの先端部で結合・一体化して柱状導体5を形成し、各導体回路41、42間の導通構造を形成していることである。
In the multilayer circuit board of the present invention, both surfaces may not be smooth surfaces like the circuit board P, and one of the surfaces may not be smooth surfaces. However, in the multilayer circuit board of the present invention, one of the surfaces is a smooth surface in relation to the manufacturing process described later.
The biggest feature of the circuit board P, as shown in FIG. 1, the upper circuit and bumps conductors 5 1, which is formed to protrude to the lower surface of the conductor circuit 4 first substrate 1, a conductor circuit of the lower circuit board 2 4 2 The bump conductors 52 projecting from the upper surface of the first and second conductors are coupled and integrated with each other in the through holes 3a formed in the insulating base 3 to form the columnar conductors 5. That is, a conductive structure between the circuits 4 1 and 4 2 is formed.

そして、この柱状導体5は後述する製造工程で形成されるのであるが、その工程中の熱圧プレスの過程で、柱状導体5の外周は絶縁基材3の貫通孔3aの内壁と密着するので、遊動することなく当該貫通孔3aによって強固に把持されている。
なお、回路基板Pにおける導体回路(ランド部も含む)と上記したバンプ導体は通常いずれもCuで形成される。
And this columnar conductor 5 is formed in the manufacturing process mentioned later, However, Since the outer periphery of the columnar conductor 5 adheres to the inner wall of the through-hole 3a of the insulation base material 3 in the process of the hot press in the process, it is. It is firmly held by the through hole 3a without floating.
Note that both the conductor circuit (including the land portion) on the circuit board P and the bump conductor described above are usually formed of Cu.

次に、本発明の多層回路基盤の製造方法を詳細に説明する。それを図1で示した回路基板Pの場合について説明する。
本発明の製造方法は、まず、上層の回路基板(第1回路基板)1と下層の回路基板(第2回路基板)2をそれぞれ別個に製造する工程Aと,各回路基板1、2を絶縁基板3を介して接合することにより一体化構造にする工程Bと、得られた一体化構造の表面を平滑面にする工程Cで構成されている。
Next, the method for manufacturing a multilayer circuit board according to the present invention will be described in detail. The case of the circuit board P shown in FIG. 1 will be described.
In the manufacturing method of the present invention, first, the process A for separately manufacturing the upper circuit board (first circuit board) 1 and the lower circuit board (second circuit board) 2 and the circuit boards 1 and 2 are insulated. It consists of a process B for forming an integrated structure by bonding via the substrate 3 and a process C for making the surface of the obtained integrated structure a smooth surface.

そして、上記した工程Aは、図1で示した回路基板Pにおける最も外側の表面に位置する回路基板を製造する工程A1と、工程A1で製造された回路基板の表面(下面)に別の回路基板を順次組付けて複数層の回路基板を製造する工程A2と、工程A2で製造された回路基板の表面(下面)に突出するバンプ導体を形成する工程A3で構成されている。
最初に工程A1について説明する。
The above-described process A is divided into a process A 1 for manufacturing the circuit board located on the outermost surface of the circuit board P shown in FIG. 1 and a surface (lower surface) of the circuit board manufactured in the process A 1. Are assembled in sequence A 2 to produce a multi-layer circuit board, and A 3 to form bump conductors protruding on the surface (lower surface) of the circuit board produced in process A 2. Yes.
First, the process A 1 will be described.

まず、図2で示したように、表面が平滑で、比較的厚く、剛性を有する平滑基板6を用意し、その片面に、電気めっき法やスパッタ法のような公知の薄膜形成法で導体薄層7を成膜する。
平滑基板6としては表面が平滑であればその材質は問わないが、例えば、ステンレス鋼板、ガラス板などをあげることができる。また、導体薄層の材料としては、例えばCuやNiをあげることができ、その厚みは3〜5μmとピンホールのない程度の厚みにすればよい。
First, as shown in FIG. 2, a smooth substrate 6 having a smooth surface, a relatively thick and rigid surface is prepared, and a conductor thin film is formed on one surface thereof by a known thin film forming method such as electroplating or sputtering. Layer 7 is deposited.
The material of the smooth substrate 6 is not limited as long as the surface is smooth, and examples thereof include a stainless steel plate and a glass plate. Moreover, as a material of a conductor thin layer, Cu and Ni can be mention | raise | lifted, for example, The thickness should just be 3-5 micrometers and the thickness which does not have a pinhole.

ついで、図3に示したように、導体薄層7の表面7aを被覆して所定厚みの絶縁層81を形成する。具体的には、例えば所定厚みのドライフィルムの粘着、液体レジストの印刷などによって形成する。
なお、絶縁層81の厚みは、形成すべき導体回路やランド部の設計厚みとの関係で適宜に選択すればよい。
Then, as shown in FIG. 3, an insulating layer 8 first predetermined thickness to cover the surface 7a of the conductor thin layer 7. Specifically, for example, it is formed by adhesion of a dry film having a predetermined thickness, printing of a liquid resist, or the like.
Note that the insulating layer 8 1 of thickness may be selected appropriately in relation to the design thickness of the conductor circuit or land portion to be formed.

ついで、この絶縁層81に露光・現像処理を施して、導体回路とランド部を形成する箇所の絶縁層81をエッチング除去し、図4で示したように、導体薄層7の表面7aが表出している凹部パターン9を形成する。
ついで、導体薄層7(または平滑基板が導電材である場合は平滑基板)をマイナス極にして電気めっきを行ない、凹部パターン9の中に例えばCuのようなめっき材料を充填して、図5で示したようなめっき充填部101を形成する。
Then, the insulating layer 8 1 is exposed and developed to etch away the insulating layer 8 1 where the conductor circuit and the land portion are to be formed, and as shown in FIG. The concave pattern 9 is exposed.
Then, electroplating is performed with the conductor thin layer 7 (or a smooth substrate if the smooth substrate is a conductive material) as a negative electrode, and the concave pattern 9 is filled with a plating material such as Cu, for example. forming a plating filling unit 10 1 as shown in.

その場合、めっき充填部101の表面と、残置している絶縁層81の表面が面一状態となるように電気めっきを行なう。このめっき充填部101が図1で示した回路基板Pの最も外側の表面に位置する導体回路になる。
このようにして、工程A1では、導体薄層7の表面の絶縁層81の中に、所定のパターンで配線されているめっき充填部(導体回路)が形成され、かつ、絶縁層81の表面とめっき充填部101の表面が面一状態になっている中間材P1が製造される。
In that case, the plating filling portion 10 1 of the surface, leaving to Dielectric 8 first surface performs electroplating so as to flush with. The plating filling portion 10 1 is conductive circuit located outermost surface of the circuit board P shown in FIG.
In this way, in step A 1 , a plated filling portion (conductor circuit) wired in a predetermined pattern is formed in the insulating layer 8 1 on the surface of the thin conductor layer 7, and the insulating layer 8 1 An intermediate material P 1 is manufactured in which the surface of the plating filling portion 10 1 is flush with the surface of the plating filling portion 10 1 .

次に工程A2を説明する。
工程A2では、図5の中間材P1のめっき充填部101も含めた全体の表面を被覆して絶縁層を形成し、その後は、工程A1の場合と同じように、導体回路を形成する箇所の絶縁層を除去して、そこに中間層P1のめっき充填材101の表面が表出している凹部パターンを形成し、ついで導電薄層7をマイナス極とする電気めっきを行なって凹部パターンの中をめっき材で充填し、新たなめっき充填部を形成する。
Next, a description will be given of Step A 2.
In step A 2, and covers the intermediate material plated filling unit 10 1 also entire surface, including the P 1 in FIG. 5 to form an insulating layer, then, as in the case of step A 1, a conductor circuit by removing the insulating layer portion that forms, there is formed a recess pattern plating filler 10 first surface of the intermediate layer P 1 is exposed, and then subjected to electroplating to the conductive thin layer 7 and negative pole Then, the recess pattern is filled with a plating material to form a new plating filling portion.

このとき、めっき充填部の表面と残置している絶縁層の表面を面一状態にすることは工程A1の場合と同じである。
その結果、図6で示したように、中間材P1のめっき充填部101と新たなめっき充填部が一体化した新たなめっき充填部102と、中間材P1の絶縁層81と形成した絶縁層とが一体化した新たな絶縁層82とを有する中間材P2が製造される。
In this case, it is the same as in Step A 1 of the surface of the insulating layer which is leaving the surface of the plating filling portion flush state.
As a result, as shown in FIG. 6, the intermediate member new plating filling section 10 2 1 a new plating filling section plating filling unit 10 are integrated in the P 1, an insulating layer 8 first intermediate material P 1 An intermediate material P 2 having a new insulating layer 8 2 integrated with the formed insulating layer is manufactured.

そして、中間材P2に対して同様の処理を行なうことにより、図7で示した中間材P3、すなわち導電薄層7の表面には図1の回路基板Pにおける上層の回路基板1の一部が一体化している中間材が製造される。
次の工程A3で、この中間材P3の表面にバンプ導体が突設される。
工程A3では、まず、図8で示したように、中間材P3のめっき充填部10を含む全面を被覆して絶縁層83がドライフィルムの粘着やレジスト印刷によって形成される。
Then, by performing the same process on the intermediate material P 2 , the intermediate material P 3 shown in FIG. 7, that is, the surface of the conductive thin layer 7, has one surface of the upper circuit board 1 in the circuit board P of FIG. An intermediate material in which the parts are integrated is manufactured.
In the next step A 3 , bump conductors are projected from the surface of the intermediate material P 3 .
In step A 3 , first, as shown in FIG. 8, the insulating layer 8 3 is formed by adhesion of a dry film or resist printing so as to cover the entire surface including the plating filling portion 10 of the intermediate material P 3 .

この絶縁層83の厚みは、図1の回路基板Pにおける柱状導体5の設計上の長さの1/2値と同じ値の厚みか若干厚くするとよい。
ついで、絶縁層83に露光・現像処理を施して、バンプ導体を形成する箇所の絶縁層83をエッチング除去し、図9で示したように、めっき充填部10の表面10aが表出している凹孔11を形成する。この凹孔11はそこにバンプ導体を形成するための凹孔である。このような凹孔の径は最小でも10μm程度にまですることができる。
The insulating layer 8 3 thickness, it is preferable to slightly larger or the thickness of the same value as 1/2 value of length of the design of the columnar conductor 5 in the circuit board P of FIG.
Next, the insulating layer 8 3 is exposed and developed to remove the insulating layer 8 3 where the bump conductor is to be formed. As shown in FIG. 9, the surface 10 a of the plated filling portion 10 is exposed. The concave hole 11 is formed. This concave hole 11 is a concave hole for forming a bump conductor there. The diameter of such a concave hole can be as small as about 10 μm.

ついで、導体薄層7をマイナス極にして電気めっきを行ない、凹孔11の中にめっき材料を充填して、図10で示したようにめっき充填部12を形成する。
このとき、めっき充填部12と残置している絶縁層83の表面は面一状態にすることが好ましい。
そして、残置している絶縁層83の全てをエッチング除去する。その結果、図11で示したように、導体回路10の表面(下面)から突出するめっき充填部12を有する中間材P4が製造される。
Next, electroplating is performed with the conductor thin layer 7 as a negative electrode, and the plating material is filled in the concave holes 11 to form the plating filling portion 12 as shown in FIG.
At this time, the surface of the insulating layer 8 3 which is leaving the plated filling portion 12 is preferably flush state.
Then, all of which insulating layer 8 3 and leaving removed by etching. As a result, as shown in FIG. 11, the intermediate material P 4 having the plating filling portion 12 protruding from the surface (lower surface) of the conductor circuit 10 is manufactured.

この中間材P4は、図1の回路基板Pにける上層回路基板1が導電薄層7の表面に組付けられた構造になっていて、めっき充填部12が上層回路基板1のバンプ導体51になっている。そして、このバンプ導体51の径は、凹孔11の径を最小で10μm程度にすることができるので、最小10μm程度にまで細径化することが可能である。
次に工程Bについて説明する。
The intermediate material P 4 has a structure in which the upper circuit board 1 in the circuit board P of FIG. 1 is assembled on the surface of the conductive thin layer 7, and the plating filling portion 12 is a bump conductor 5 of the upper circuit board 1. It is 1 . The diameter of the bump conductors 5 1, it is possible to approximately 10μm diameter of the concave hole 11 at the minimum, it is possible to reduce the diameter of up to a minimum 10μm approximately.
Next, step B will be described.

まず、図12で示したように、工程Aで製造した2個の中間材P4,P4'を、絶縁基材3を中間に置いて、互いのめっき充填部側の表面を対向させた状態で配置する。
なお、中間材P4のバンプ導体51の面内分布パターンと、中間材P4'のバンプ導体52の面内分布パターンは、2個の中間材P4,P4'を当接したときにそれぞれのバンプ導体が互いに同じ位置座標となるように設計されていて、その設計基準に基づいて工程Aで形成されている。
First, as shown in FIG. 12, the two intermediate materials P 4 and P 4 ′ produced in the process A are placed with the insulating base 3 in the middle, and the surfaces on the side of the plating filling portion are opposed to each other. Arrange in a state.
Note that the plane of the bumps conductors 5 1 intermediate members P 4 distribution patterns, the intermediate material P 4 'plane distribution pattern of bumps conductors 5 2, the two intermediate members P 4, P 4' and in contact with Sometimes, each bump conductor is designed to have the same position coordinates, and is formed in the process A based on the design criteria.

また、絶縁基材3には、それぞれのバンプ導体の座標位置に貫通孔3aが形成されている。そして絶縁基材3の厚みは、中間材P4,P4'に形成されているバンプ導体51,52の高さの合計と等しいか、若干それよりも薄くなっている。
絶縁基材3としては、例えばプリプレグ材やポリイミドフィルムなどを使用することができ、その両面に接着剤層を形成したものであることが好ましい。
Moreover, the through-hole 3a is formed in the insulating base material 3 at the coordinate position of each bump conductor. The thickness of the insulating base material 3 is equal to or slightly smaller than the total height of the bump conductors 5 1 and 5 2 formed on the intermediate materials P 4 and P 4 ′.
As the insulating substrate 3, for example, a prepreg material or a polyimide film can be used, and it is preferable that an adhesive layer is formed on both surfaces thereof.

また、絶縁基材3に形成されている貫通孔3aの口径は、中間材P4,P4'に形成されているバンプ導体51,52が挿通できる大きさであればよく、格別の加工精度で形成しなくてもよい。
そして、中間材P4と中間材P4'を絶縁基材3を介して重ね合せる。それぞれのバンプ導体は、絶縁基材3の貫通孔3aの中に挿入され、バンプ導体51の先端部とバンプ導体52の先端部は互いに接触するか、微小クリアランスを置いて対向配置された状態になる。
Further, the diameter of the through hole 3a formed in the insulating base material 3 is not limited as long as the bump conductors 5 1 and 5 2 formed in the intermediate materials P 4 and P 4 ′ can be inserted. It does not have to be formed with processing accuracy.
Then, the intermediate material P 4 and the intermediate material P 4 ′ are overlapped via the insulating base material 3. Each bump conductor is inserted into the through hole 3a of the insulating substrate 3, or the bumps conductors 5 1 of the tip portion and the bump conductors 5 2 of the tip portion are in contact with each other, they are located opposite each other with a minute clearance It becomes a state.

このとき、貫通孔3aの口径はバンプ導体の径よりも大きいので、バンプ導体の貫通孔への挿入は円滑に進む。
そして、2個の中間材を重ね合せた状態で、熱圧プレスを行なって2個の中間材を一体化にする。熱圧プレスは真空中で行なうのが好ましい。それは絶縁基材が樹脂成分を含むため、その熱分解時のガスを接着面から除去するためである。
At this time, since the diameter of the through hole 3a is larger than the diameter of the bump conductor, the insertion of the bump conductor into the through hole proceeds smoothly.
Then, in a state where the two intermediate materials are superposed, hot pressing is performed to integrate the two intermediate materials. The hot press is preferably performed in a vacuum. This is because the insulating base material contains a resin component, so that the gas during the thermal decomposition is removed from the adhesive surface.

熱圧プレス時の温度は、用いる絶縁基材の軟化点や後述するバンプ導体の先端部の結合との関係で適宜に選定されるが、概ね150〜340℃であればよい。また印加圧力は、得られた一体化構造の強度と、形成される柱状導体の信頼性向上の点から、概ね2.0〜4.5MPa程度に設定される。
この熱圧プレス時に絶縁基材3は軟化して変形する。そして、表面の接着剤層の働きで中間材P4と中間材P4'はそれぞれ絶縁基材3の表面と接着する。
The temperature at the time of hot-pressing is appropriately selected depending on the softening point of the insulating base material to be used and the bonding of the tip end portion of the bump conductor described later, but it may be about 150 to 340 ° C. The applied pressure is generally set to about 2.0 to 4.5 MPa from the viewpoint of the strength of the obtained integrated structure and the improvement of the reliability of the formed columnar conductor.
During this hot press, the insulating base material 3 is softened and deformed. The intermediate material P 4 and the intermediate material P 4 ′ are bonded to the surface of the insulating substrate 3 by the action of the adhesive layer on the surface.

一方、貫通孔3a内のバンプ導体51,52は互いの先端部が圧接し、熱と圧力により相互拡散をまたは溶融して一体化し、1本の柱状導体5に転化する。そして、その柱状導体5は、変形する貫通孔3aの内壁と密着した状態で貫通孔内に固定される。
なお、バンプ導体の貫通孔への挿入時に、それぞれのバンプ導体の中心軸線が多少ずれていても、熱圧プレス時における絶縁基材の変形により、形成された柱状導体はやはり貫通孔の内壁と密着して孔内で固定されることになる。
On the other hand, the bump conductors 5 1 and 5 2 in the through-hole 3 a are in pressure contact with each other, and are mutually diffused or melted and integrated by heat and pressure to be converted into a single columnar conductor 5. The columnar conductor 5 is fixed in the through hole in close contact with the inner wall of the deformed through hole 3a.
Even when the center axis of each bump conductor is slightly deviated when the bump conductor is inserted into the through hole, the formed columnar conductor is still in contact with the inner wall of the through hole due to deformation of the insulating base material during hot press. It will adhere and be fixed in the hole.

ここで、バンプ導体を形成するときに用いるめっき材は、導体回路やランド部の場合と同様に、通常、Cuである。
そして、熱圧プレス時におけるバンプ導体51,52の結合強度を高めるためには、用いる中間材P4と中間材P4'の少なくとも一方のバンプ導体の先端部に、熱によって拡散もしくは溶融する金属または合金を薄くめっきしておくことが好ましい。例えば、Auめっき、はんだめっき、Snめっきなどを施しておくことが好ましい。
Here, the plating material used when forming the bump conductor is usually Cu, as in the case of the conductor circuit and the land portion.
In order to increase the bonding strength of the bump conductors 5 1 and 5 2 during the hot press, diffusion or melting is caused by heat at the tip of at least one of the bump conductors of the intermediate material P 4 and the intermediate material P 4 ′. Preferably, the metal or alloy to be plated is thinly plated. For example, it is preferable to perform Au plating, solder plating, Sn plating, or the like.

例えば、図12の中間材P4のバンプ導体51の先端部にAuめっきを施し、中間材P4'バンプ導体52はCuのままである場合、熱圧プレス時に、CuとAuの間で相互拡散が起こり、そのことによってバンプ導体51とバンプ導体52の間では高い結合高度が得られる。
また、バンプ導体の先端部に、はんだやSnのような低融点材料をめっきしておくと、熱圧プレス時にバンプ導体51とバンプ導体52とが互いの先端部で接触していない状態の場合であっても、溶融固化した上記低融点材料によって両バンプ導体間の電気的結合を確保することができる。
For example, applying Au plating on the tip portion of the bump conductors 5 1 intermediate members P 4 in FIG. 12, when the intermediate material P 4 'bump conductors 5 2 remains Cu, during hot pressing, between Cu and Au in occurs mutual diffusion, high binding altitude is obtained between the bump conductor 5 1 and the bump conductor 5 2 by its.
The state at the tip portion of the bump conductor idea to plating a low melting point material such as solder, Sn, where the bumps conductor 5 1 and the bump conductor 5 2 during hot pressing is not in contact with each other at the tip portion Even in this case, the low-melting-point material melted and solidified can ensure electrical coupling between the bump conductors.

このことは、図11の中間材P4,P4'の製造時に、突出形成するバンプ導体の高さに自由度をもたせることができることを意味する。
また、バンプ導体の結合に際しては、例えば両面に接着材層が形成されているガラス繊維−エポキシ樹脂基板や、両面に接着材層が形成されているポリイミドフィルムのような樹脂フィルムや、プリプレグ材のような絶縁基材3に、穿孔ドリルやレーザ光で所望口径の貫通孔3aを形成したのち、その貫通孔3aにAgペースト、Cuペーストのように、金属粉体を樹脂バインダに分散させたような導電ペーストを充填した絶縁基材を用いることもできる。
This means that when the intermediate materials P 4 and P 4 ′ of FIG. 11 are manufactured, the height of the bump conductor to be formed can be given a degree of freedom.
When bonding the bump conductor, for example, a glass fiber-epoxy resin substrate having an adhesive layer formed on both sides, a resin film such as a polyimide film having an adhesive layer formed on both sides, or a prepreg material After forming a through hole 3a having a desired diameter in such an insulating base 3 with a drill or a laser beam, metal powder is dispersed in a resin binder like Ag paste or Cu paste in the through hole 3a. An insulating substrate filled with a conductive paste can also be used.

この場合には、中間材P4,P4'におけるバンプ導体51,52の高さを低くすることができる。バンプ導体が相互の先端部では接触していなくても、先端部の間に導電ペーストが介在しているので、導通は確保されて実質的に柱状導体が形成されるからである。
この工程Bを終了した時点で、図13で示したように、両面に導電薄層7と平滑基板6が配置されている中間材P5が得られる。
In this case, the height of the bump conductors 5 1 and 5 2 in the intermediate materials P 4 and P 4 ′ can be reduced. This is because even if the bump conductors are not in contact with each other at the tip portions, the conductive paste is interposed between the tip portions, so that conduction is ensured and a columnar conductor is formed substantially.
When this step B is completed, as shown in FIG. 13, an intermediate material P 5 in which the conductive thin layer 7 and the smooth substrate 6 are disposed on both surfaces is obtained.

そして工程Cで中間材P5から平滑基板と導電薄層が順次除去される。
具体的には、例えばエッチング処理によって平滑基板6を除去する。ついで、所定のエッチング処理を行なって導電薄層7を除去する。
その結果、図1で示した回路基板Pが得られる。すなわち、両面が平滑で、上層の回路基板1と下層の回路基板2が絶縁基材を介して一体化している構造で、上層の回路基板1と下層の回路基板2の間は、絶縁基材3内に形成された柱状導体5で導通がとられている多層回路基板である。
In step C, the smooth substrate and the conductive thin layer are sequentially removed from the intermediate material P 5 .
Specifically, the smooth substrate 6 is removed by, for example, an etching process. Next, a predetermined etching process is performed to remove the conductive thin layer 7.
As a result, the circuit board P shown in FIG. 1 is obtained. That is, both surfaces are smooth and the upper circuit board 1 and the lower circuit board 2 are integrated via an insulating base material, and the insulating base material is provided between the upper circuit board 1 and the lower circuit board 2. 3 is a multi-layer circuit board which is electrically connected by a columnar conductor 5 formed in the circuit board 3.

なお、以上の説明は、上層回路基板と下層回路基板がいずれも多層回路基板になっている図1の回路基板Pに関するものであるが、本発明はこれに限定されるものではない。
例えば、上層(または下層)の回路基板として、図5で示した中間材P1を使用し、この中間材P1のめっき充填部101の表面にバンプ導体を突設し、下層(または上層)の回路基板も同様なものを用いてもよい。
The above description relates to the circuit board P of FIG. 1 in which both the upper circuit board and the lower circuit board are multilayer circuit boards, but the present invention is not limited to this.
For example, as a circuit board for the upper layer (or lower layer), using an intermediate material P 1 shown in FIG. 5, bumps conductor projecting from the intermediate material plated filling portion 10 1 of the surface of the P 1, a lower layer (or upper layer The same circuit board may be used.

また、例えば上層(または下層)の回路基板として表面が平滑であるものを用い、下層(または上層)の回路基板としては表面に導体回路やランド部がある厚みをもって形成されているようなものを用いれば、片面が平滑な多層回路基板にすることができる。   Also, for example, an upper layer (or lower layer) circuit board having a smooth surface is used, and a lower layer (or upper layer) circuit board having a thickness with a conductor circuit or land on the surface is used. If used, a multilayer circuit board having a smooth one side can be obtained.

本発明の多層回路基板の場合、層間の導通構造が絶縁層内に固定された中実の柱状導体で形成されているので、信頼性の高い導通構造になっている。そして、柱状導体を形成するときに、結合すべきバンプ導体の少なくとも一方にAuめっき、はんだめっきなどを施すことにより、バンプ導体の結合強度は向上し、したがってより一層信頼性の高い層間の導通構造にすることができる。   In the case of the multilayer circuit board according to the present invention, the conductive structure between the layers is formed of a solid columnar conductor fixed in the insulating layer, so that the conductive structure is highly reliable. Then, when forming the columnar conductor, at least one of the bump conductors to be bonded is subjected to Au plating, solder plating, etc., so that the bonding strength of the bump conductor is improved, and thus a more reliable conductive structure between layers. Can be.

また、バンプ導体の径を最小で10μm程度にまで細径化することができるので、層間の貫通構造は非常にファインとなり、その結果、各種部品の高密度実装が可能となる。   Further, since the diameter of the bump conductor can be reduced to a minimum of about 10 μm, the through structure between the layers becomes very fine, and as a result, various parts can be mounted at high density.

本発明の多層回路基板の1例Pを示す断面図である。It is sectional drawing which shows one example P of the multilayer circuit board of this invention. 平滑基板の片面に導電薄層を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the conductive thin layer in the single side | surface of a smooth substrate. 導電薄層を被覆して絶縁層を形成した状態を示す断面図である。It is sectional drawing which shows the state which coat | covered the electroconductive thin layer and formed the insulating layer. 絶縁層に導体回路とランド部用の凹部パターンの形成した状態を示す断面図である。It is sectional drawing which shows the state in which the conductor circuit and the recessed part pattern for land parts were formed in the insulating layer. 凹部パターンにめっき材料が充填された中間材P1を示す断面図である。Plating material in the recess pattern is a sectional view showing an intermediate material P 1 filled. 中間材P2を示す断面図である。Is a sectional view showing an intermediate material P 2. 中間材P3を示す断面図である。Is a sectional view showing an intermediate material P 3. 中間材P3の表面に絶縁層を形成した状態を示す断面図である。It is a sectional view showing a state of forming an insulating layer on the surface of the intermediate member P 3. 絶縁層にバンプ導体用の凹孔を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the concave hole for bump conductors in the insulating layer. 凹孔にめっき材料を充填した状態を示す断面図である。It is sectional drawing which shows the state which filled the plating material in the concave hole. 中間材P4を示す断面図である。Is a sectional view showing an intermediate material P 4. 中間材P4と絶縁基材と中間材P4'の配置関係を示す断面図である。It is a cross sectional view showing the arrangement relationship between the intermediate member P 4 and the insulating base material intermediate member P 4 '. 中間材P5を示す断面図である。Is a sectional view showing an intermediate material P 5.

符号の説明Explanation of symbols

1 上層の回路基板
1a 上層の回路基板1の表面
2 下層の回路基板
2a 下層の回路基板2の表面
3 絶縁基材
3a 貫通孔
1,42 導体回路とランド部
5,51,52 バンプ導体
6 平滑基板
7 導電薄層
7a 絶縁層7の表面
1,82,83 絶縁層
9 凹部パターン
10,101,102 めっき充填部
11 凹孔
12 めっき充填部(バンプ導体)
DESCRIPTION OF SYMBOLS 1 Upper-layer circuit board 1a Surface 2 of upper-layer circuit board 1 Lower-layer circuit board 2a Surface 3 of lower-layer circuit board 2 Insulating base material 3a Through-hole 4 1 , 4 2 Conductor circuit and land portion 5, 5 1 , 5 2 surface 8 1 of the bump conductor 6 smooth substrate 7 electrically conductive thin layer 7a insulating layer 7, 8 2, 8 3 insulating layer 9 concave pattern 10, 10 1, 10 2 plated filling section 11 concave hole 12 plated filling portion (bump conductor)

Claims (8)

複数の回路基板を積層して一体化した構造の多層回路基板において、
少なくとも片側の表面は、ランド部と導体回路が前記表面と面一状態にある平滑面であり、
上層の回路基板と下層の回路基板を接続する導通構造の少なくとも1つは、前記上層の回路基板の下面に突出するバンプ導体の先端部と前記下層の回路基板の上面に突出するバンプ導体の先端部とが、直接または導電材を介して結合された柱状導体から成ることを特徴とする多層回路基板。
In a multilayer circuit board having a structure in which a plurality of circuit boards are stacked and integrated,
At least one of the surfaces is a smooth surface in which the land portion and the conductor circuit are flush with the surface,
At least one of the conductive structures connecting the upper circuit board and the lower circuit board includes a front end portion of the bump conductor protruding from the lower surface of the upper circuit board and a front end of the bump conductor protruding from the upper surface of the lower circuit board. A multilayer circuit board characterized in that the portion is made of a columnar conductor joined directly or via a conductive material.
上面にはランド部と導体回路が前記上面と面一状態で形成され、かつ、下面にはバンプ導体が突出している単層または多層の第1回路基板と、
下面にはランド部と導体回路が前記下面と面一状態で形成され、かつ上面にはバンプ導体が突出している単層または多層の第2回路基板とが、絶縁基材を介して接合され、前記絶縁基材内に形成された前記柱状導体の導体構造を有し、かつ両面が平滑面である、請求項1の多層回路基板。
A single-layer or multi-layer first circuit board in which a land portion and a conductor circuit are formed flush with the upper surface on the upper surface, and a bump conductor protrudes on the lower surface;
A land portion and a conductor circuit are formed on the lower surface in a state flush with the lower surface, and a single-layer or multilayer second circuit board on which the bump conductor protrudes is bonded to the upper surface via an insulating base material, The multilayer circuit board according to claim 1, wherein the multilayer circuit board has a conductor structure of the columnar conductor formed in the insulating base, and both surfaces are smooth surfaces.
平滑基板の片面に形成された導電薄層の表面に、複数の回路基板が順次積層され、最後に積層された回路基板の表面には所定の平面パターンでバンプ導体が突出している中間材を製造する工程A;
2個の前記中間材のバンプ導体側の表面を、各表面のバンプ導体の平面パターンに対応してバンプ導体よりも大径の貫通孔が形成されている絶縁基材を介して対向させ、
各バンプ導体を前記貫通孔に挿入したのち全体に熱圧プレス処理を行って2個の前記中間材を前記絶縁基材を介して接合することにより一体化構造にすると同時に、前記バンプ導体の先端部を前記貫通孔内で結合する工程B;および
前記一体化構造から、前記平滑基板と前記導電薄層を順次除去する工程C;
を備えることを特徴とする多層回路基板の製造方法。
Produces an intermediate material in which a plurality of circuit boards are sequentially stacked on the surface of a conductive thin layer formed on one side of a smooth substrate, and bump conductors protrude in a predetermined plane pattern on the surface of the last stacked circuit board. Performing step A;
The surface on the bump conductor side of the two intermediate members is opposed to each other through an insulating base material in which a through hole having a larger diameter than the bump conductor is formed corresponding to the planar pattern of the bump conductor on each surface,
After inserting each bump conductor into the through-hole, the whole is subjected to a hot press process to join the two intermediate members through the insulating base material to form an integrated structure, and at the same time, the tip of the bump conductor A step B of joining the parts in the through hole; and a step C of sequentially removing the smooth substrate and the conductive thin layer from the integrated structure;
A method for producing a multilayer circuit board, comprising:
2個の前記中間材のバンプ導体がいずれもCuから成り、少なくとも一方の中間材のバンプ導体の少なくとも先端部には、熱により溶融もしくは拡散する金属または合金のめっきが施されている請求項3の多層回路基板の製造方法。   The two bump conductors of the intermediate material are both made of Cu, and at least a tip portion of the bump conductor of at least one intermediate material is plated with a metal or alloy that melts or diffuses by heat. Manufacturing method for multilayer circuit board. 前記金属または合金のめっきが、Auめっき、Snめっき、またははんだめっきである請求項4の多層回路基板の製造方法。   The method for manufacturing a multilayer circuit board according to claim 4, wherein the metal or alloy plating is Au plating, Sn plating, or solder plating. 前記絶縁基材の前記貫通孔に充填された導電ペーストを介して2個の前記中間材のバンプ導体を互いに電気的に結合する請求項3の多層回路基板の製造方法。   4. The method of manufacturing a multilayer circuit board according to claim 3, wherein the two bump conductors of the intermediate material are electrically coupled to each other through a conductive paste filled in the through hole of the insulating base. 前記熱圧プレス処理が真空熱圧プレス処理である請求項3の多層回路基板の製造方法。   4. The method for manufacturing a multilayer circuit board according to claim 3, wherein the hot-pressing process is a vacuum hot-pressing process. 前記工程Aが、
平滑基板の表面に導体薄層を形成したのち、前記導体薄層の表面を被覆して絶縁層aを形成し、前記絶縁層aに露光・現像処理を行って、ランド部と導体回路を形成すべき箇所の前記絶縁層aを除去して、そこに前記導体薄層が表出している凹部パターンaを形成し、ついで、電気めっき法で、前記凹部パターンaの中に、残置する前記絶縁層aの表面と面一状態になるまでめっき材料を充填してめっき充填部aを形成する工程A1と、
前工程で形成しためっき充填部を含む表面全部を被覆して絶縁層bを形成し、前記絶縁層bに露光・現像処理を行って、ランド部と導体回路を形成すべき箇所の前記絶縁層bを除去し、そこに前記めっき充填部が表出している凹部パターンbを形成し、ついで電気めっき法で、前記凹部パターンbの中に、残置する前記絶縁層bの表面と面一状態になるまでめっき材料を充填して新たなめっき充填部bを形成することを1回行なうかまたは複数回反復する工程A2と、
工程A2で形成された最後のめっき充填部を含む表面全部を被覆して絶縁層cを形成し、前記絶縁層cに露光・現像処理を行って、バンプ導体を形成すべき箇所の前記絶縁層cを除去し、そこに前記めっき充填部が表出しているバンプ導体用凹孔を形成し、ついで電気めっき法で、前記バンプ導体用凹孔の中にめっき材料を充填したのち、前記絶縁層cを全て除去して、前記めっき充填部の表面にバンプ導体を突設する工程A3とを備えている請求項3の多層回路基板の製造方法。
Step A is
After forming a thin conductive layer on the surface of the smooth substrate, the surface of the thin conductive layer is covered to form an insulating layer a, and the insulating layer a is exposed and developed to form a land portion and a conductive circuit. The insulating layer a in a place to be removed is removed to form a concave pattern a on which the conductive thin layer is exposed, and then the insulation is left in the concave pattern a by electroplating. Step A 1 for filling the plating material until the surface of the layer a is flush with the surface of the layer a to form the plating filling portion a,
The insulating layer b is formed by covering the entire surface including the plated filling portion formed in the previous step, and the insulating layer b is exposed and developed to form the land portion and the conductor circuit at the location where the conductor circuit is to be formed. b is removed, and the concave pattern b exposed by the plating filling portion is formed therein, and then the surface of the insulating layer b to be left is flush with the surface of the concave pattern b by electroplating. A step A 2 of filling the plating material until forming a new plating filling portion b until it is completed or repeating a plurality of times;
All surfaces, including the step A 2 last plating filled portion formed in a coated form an insulating layer c, performing exposure and development on the insulating layer c, the insulation of the portion to be formed a bump conductor After removing the layer c, a bump conductor concave hole exposed by the plating filling portion is formed therein, and after filling the plating material into the bump conductor concave hole by electroplating, the insulation 4. The method of manufacturing a multilayer circuit board according to claim 3 , further comprising a step A3 of removing all the layers c and projecting bump conductors on the surface of the plating filling portion.
JP2005125945A 2005-04-25 2005-04-25 Multilayer circuit board and its manufacturing method Pending JP2006303338A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008192878A (en) * 2007-02-06 2008-08-21 Shinko Electric Ind Co Ltd Multilayer wiring substrate, and manufacturing method thereof
WO2013031815A1 (en) * 2011-08-31 2013-03-07 株式会社フジクラ Multilayered circuit board manufacturing method
JP2014130969A (en) * 2012-12-28 2014-07-10 Fujikura Ltd Wiring board and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008192878A (en) * 2007-02-06 2008-08-21 Shinko Electric Ind Co Ltd Multilayer wiring substrate, and manufacturing method thereof
WO2013031815A1 (en) * 2011-08-31 2013-03-07 株式会社フジクラ Multilayered circuit board manufacturing method
JP2014130969A (en) * 2012-12-28 2014-07-10 Fujikura Ltd Wiring board and method of manufacturing the same

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