TWI423752B - Advanced coreless support structures and their fabrication - Google Patents

Description

Multi-layer coreless support structure manufacturing method

The invention relates to a multi-layer coreless support structure and a manufacturing method thereof.

The electronics industry is becoming more complex and miniaturized, especially in mobile devices such as mobile phones and portable computers.

Integrated circuits (ICs) are the core of these electronic systems. Similarly, ICs are becoming more complex, integrating more and more transistors and requiring more and more input and output contacts. They work at faster conversion speeds and frequencies, require more energy and generate a lot of heat that needs to be dissipated.

ICs are connected to power supplies, user interfaces and other components through printed circuit boards (PCBs). In order to make the connection between these ICs and PCBs easier, a large number of electrical connections are required. A common solution is to use an electronic substrate connection. IC and its PCB. The electronic substrate is part of an IC package that replaces the conventional lead frame as an insertion mechanism between the IC and its PCB. Such a substrate may include one, two or more conductor layers separated by a plurality of insulating materials, such as ceramic or organic materials. Such substrates typically have a contact conducting array at their bottom. The conductive contacts can be spherical contacts that provide a so-called ball grid array (BGA) or pin, or so-called pin array (PGA), for the electrical connection of the PCB. Alternatively, the substrate can be mounted directly to the ball without using ball contacts or pins. On the PCB, a so-called moment grid array (LGA) is provided. At the top, the substrate typically carries one or more electrically connected ICs by so-called wire bonding techniques or flip chip packaging techniques.

1 shows an example of a prior art wire bonded BGA package including a substrate 100; a ball grid array (BGA) connecting the pads 104 on the bottom side of the substrate 100 to the bottom conductive PCB 102 (not shown), and An array of electrical leads, wire bonding 106, connects the top pads 108 of substrate 100 to IC 110. The packaged IC 110 is typically protected by a resin material 112, also known as a molding material.

2 shows an example of a prior art flip chip BGA package containing a flip chip BGA substrate 200. A ball grid array (BGA) 202 of electrically conductive balls connects the pads 204 on the bottom side of the substrate 200 to the bottom PCB. However, the electrically conductive bumps 206 located above the top pad 208 of the substrate 200 replace the wire bond and are connected to the IC 210 using a flip chip process. In this process, a resin material 212 is also applied between the IC 210 and the surface of the substrate 200. In this technique, resin material 212 is also commonly referred to as "unfilled" material. Resin 212 acts as a stress buffering material that reduces the fatigue experienced by IC 210 and bumps 206 during thermal cycling over the life of package 250. Sometimes, the flip chip package 250 also includes a metal reinforcement layer 216 attached to the substrate 200 by an adhesive layer 218 and a cover 220 attached to the back surface of the IC 210 by a thermal adhesive layer 222. The reinforcement layer 216 is used to further strengthen the substrate 200 and helps maintain the flatness of the subsequent IC integration process, while the cover 220 helps dissipate the heat generated by the IC 210 during operation.

The above-mentioned novel BGA substrate, PGA substrate, and LGA substrate for the wire bonding process and the flip chip process as shown in FIG. 1 and FIG. 2 generally include two main parts: a so-called "core portion" and a layer-by-layer construction. Combination part".

A detailed example of a typical organic flip chip BGA (FCBGA) substrate 300 is shown in FIG. The core portion 330 of the substrate 300 is composed of a plurality of copper conductor layers 332 separated by a glass fiber reinforced organic insulating layer 334. The copper conductor layer 332 in the core 330 is electrically connected by a metallized via (PTH) 336. In general, in the process of fabricating the substrate 300, the core portion 330 is first fabricated. Metallized vias 336 are then formed by mechanical drilling, copper plating, and plugging. Then, the outer copper conductor layer 338 of the core portion 330 is formed. Two combined portions 340', 340" are then added to both sides of the core 300. These combined portions 340', 340" are comprised of a plurality of copper conductor layers 342, the layers of which are reinforced by glass fibers between layers The insulating layers 344 are spaced apart. The interior of the insulating layer 344 includes copper plated microvias 346 that connect adjacent copper conductor layers. The microvias 346 are typically fabricated using a laser drilling process and, therefore, are typically smaller in diameter than the metallized vias 336. This saves valuable space on the substrate 300 for application ICs. The dielectric used in the combined portion has improved mechanical and electrical characteristics, and due to the higher conductor density achieved using the microvias 346, the density of the IC contacts is ultimately achieved and acts as an intermediate contact to the PCB.

It is noted that the core portion 330 of the substrate 300 of such an FCBGA first serves as an internal connection "carrier" for the combined portions 340', 340" while being suitable for operating the power supply and ground copper conductor layers of the density required by the IC.

Due to their finer I/O pitch, modern ICs require a very flat, warp-free substrate to ensure package reliability. This would be difficult to achieve if the combined portion of the substrate was only placed on one side of the core portion. In order to make a flat, warp-free substrate during the IC packaging process, the composite portion should be placed on both sides of the core portion to achieve a symmetrical structure to create a stress-balanced, flat substrate.

However, there is a price to place the combined portion on both sides of the core portion, which increases the number of manufacturing steps, thereby increasing the production cost. Since the base structure obtained by this method is more complicated, the production yield is also lowered. Moreover, an increase in the thickness of the substrate results in a decrease in compactness, and a thicker package is not required for mobile communication devices and other fields requiring miniaturization. In addition, an increase in substrate thickness results in an increase in package inductance and thermal impedance. These can destroy the performance of the IC. Based on these shortcomings, many attempts have been made to improve the sandwich structure described above.

One way to reduce the thickness is to make a substrate material without a core portion, providing a "coreless substrate" technique. In this technique, the core portion and the combined portion of the BGA (or PGA, LGA) side of the substrate are removed, whereby the entire substrate contains only one combined portion for connecting the IC to the PCB. The thickness of the substrate is greatly reduced while improving its thermal impedance and electrical properties. In addition, the removal of the core portion of the substrate can shorten the cycle time of the fabrication process and eliminate the need for expensive mechanical drilling of PTHs.

U.S. Patent Application Serial No. US Ser. No. 2002/0001,937, issued to to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire content even, The substrate was later partially removed to form a metal support reinforcement layer having holes for connecting ICs.

Although USK 2002/0001937 to Kikuchi provides a viable method of obtaining a coreless substrate, it has many drawbacks. First, all of the conductor layers of the substrate require expensive thin film interconnections. Although such thin film interconnects have good characteristics due to improved density and finer pitch, they are not suitable for making low density and large pitch power and ground layers, and at the same time making such expensive thin film interconnects economically. Not feasible. In addition, these layers typically require a specific metal thickness to reduce electrical resistance and prevent overheating. It is difficult to achieve this effect using a film making process. Furthermore, the flip chip bonding process imposes stresses that are unacceptable to the thin film interconnect structure. Such film thicknesses generally do not exceed 100 microns, and such pressure can cause the interconnect structure to bend or deform. This situation sometimes causes damage to the thin film insulating layer, thereby causing IC operation failure. In addition, the presence of metal-reinforced portions near the IC can take up valuable space on the outer surface of the substrate, limiting its use in applications where passive components are required, such as decoupling capacitors close to the IC. Furthermore, large diameter metal reinforced portions can result in this technique not being suitable for applications such as multi-wafer substrates, low-sized substrates, and two-dimensional matrix arrays or strip-shaped substrates.

U.S. Patent No. 6,872,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Although the substrate mentioned by Stanberg in the patent US 6,872,589 is more than the patent USSN 2002/0001937 The substrate is advantageous due to its low number of interconnect layers, but it still has all the drawbacks found in the USSN 2002/0001937 patent.

According to the above, many fields require a low-cost, high-performance coreless substrate. In order to meet this demand, a promising approach is to eliminate the expensive film composite structures described above, and replace them with other inexpensive materials and processes that are established and commonly used in the conventional PCB fabrication industry. Unlike thin film insulation, the new insulating materials used in the PCB industry are often applied in the form of laminated technology, in the form of pre-impregnated sheets reinforced with glass fibers or other reinforcing materials. By properly selecting these insulating materials, a "self-supporting" coreless base structure may be made which will eliminate or at least reduce the need for metal reinforcement. Moreover, with relatively low cost, existing PCB processes are expected to provide an economical multilayer substrate that includes both low density, large pitch power and ground metal layers and high density, small pitch metal signal layers.

This layered structure is easily warped, especially during heat compression or hardening. Therefore, the coreless substrate lacks the flatness required for safely and reliably mounting the IC.

When the substrate is assembled on only one side of the metal carrier substrate, the carrier substrate is removed or thinned prior to IC assembly, and as a reinforcing support substrate, an unbalanced stress is generated inside the fabrication process. These stresses may be released by the peeling of the metal carrier, which may cause bending and lifting of the substrate. This deformation can result in low yields when assembling the IC, and can also result in an uneven package that cannot be mounted on the corresponding PCB.

In order to solve this problem, the patent number proposed by Ho et al. is US 6,913,814. The U.S. patent teaches a lamination process and its corresponding structure in which a high density multilayer substrate is provided which is fabricated separately and finally stacked. This approach provides an alternative to asymmetrical, multilayer substrates fabricated on conventional metal carrier substrates that are common in the prior art, and which appears to utilize the tested material process in the PCB fabrication industry, where PTH is Instead of a solid copper microchannel, an economical organic coreless substrate is provided.

However, the technique in US 6,913,814 has two major drawbacks: first, in order to fabricate a structure comprising a low pitch BGA bottom layer and a high pitch IC side attached to a PCB, the substrate must be composed of separate layers, each layer having Different densities and different insulation thicknesses, this situation once again leads to an unbalanced, asymmetrical structure that is prone to warpage. Secondly, as is well known in the prior art, it is difficult to obtain better IC performance by using a via-pad connection between the layers of the substrate established by metal conduction through the insulating layer stack, since This leads to the loss of the via contacts and the resulting package failure. This is especially noteworthy in the high temperature process used in the process of IC mounting to the substrate.

The present inventors have also filed an application for a simultaneous application, which is referred to by Hurwitz et al. in IL171378, October 11, 2005, entitled "New Integrated Circuit Support Structure and Method of Making the Same". (a) selecting a first substrate layer; (b) adding an anti-etch barrier layer to the substrate layer; (c) adding a copper seed layer; (d) fabricating a first stack of conductive layers and insulating a layer, the conductive layer is connected through a through hole penetrating the insulating layer; (e) adding a first layer on the first half stack a second metal substrate layer; (f) adding a protective photoresist layer to the second metal substrate layer; (g) etching away the first substrate layer; (h) removing the photoresist layer; (i) removing the initial layer An anti-etching barrier layer; (j) fabricating a second stack of conductive layers and an insulating layer, the conductive layer being connected by a through hole penetrating the insulating layer, the second half stack being substantially symmetrical with the first half stack; (k) adding an insulating layer on the second half stack of the more stacked conductive layer and the insulating layer; (1) removing the second metal substrate layer.

The processing in IL171378 proposed by Hurwitz et al. essentially consists of halving the required structure on a sacrificial substrate, terminating the half of the structural stack with a thick layer that becomes the second sacrificial substrate and is removed. The first sacrificial substrate is fabricated and a second half of the stack substantially symmetrical to the first half of the stack is formed, whereby the initially added layer becomes the intermediate layer of the entire laminate.

Theoretically, the first half stack and the second half stack should be mirror images of each other, have reverse residual stresses, cancel each other out, and tend not to warp. However, since the pile structures are made outward from the center thereof, the first half stack is made from the center outward, and the second half stack on the first half stack is also made from the center outward, which makes it difficult to Ensure that the process conditions of the two halves are uniform, and the difference between the two sides may cause some unbalanced residual stress in the substrate, which may cause the substrate to bend. This curved substrate cannot meet the advanced IC packaging process, such as stacking. Strict planar requirements for package (POP), package package (PIP), stacked IC packages, flip-chip mounting with several ICs, or other wire bonding processes. For these reasons, the IL171378 proposed by Hurwitz et al. has made a big move forward compared to the original technology. However, it is still not suitable for a multi-layer, complex structure having a large number of active layers, and the yield of the above structure is lowered.

Therefore, in spite of the above advancement and the IL171378 proposed by Hurwitz et al., in view of the strict requirements for flatness, it is still necessary to propose a better fabrication process and a corresponding wafer support structure, which should have Even if it is applied in many layers of structures, it still has the advantages of economy and high yield. The present invention takes this need into consideration and provides new process technologies and new structures.

It is an object of the present invention to provide a novel multilayer interconnect support structure fabrication technique that is very economical and particularly suitable for large scale manufacturing industries.

Another object of the present invention is to provide a fabrication technique with high yield.

Another object provided by the present invention is to make an array of vias between conductive layers without the use of a drilling and plating process that is time consuming, expensive, and can only be used to make circular cross-section vias.

It is a particular object of the present invention to provide a fabrication process for a multilayer interconnect support structure having good planarity and flatness.

Still another object of the present invention is to provide a fabrication process for a multilayer interconnect support structure having high reliability.

The present invention provides a high performance coreless layered substrate for single IC or multiple ICs having a plurality of conductive power and ground layers and a high density, fine pitch conductive signal layer, which is thinner than the prior art. The layers are interconnected by solid copper vias surrounded by an insulating layer. The copper vias can have any cross-sectional shape and not just a circle. The substrate can transmit electronic signals with low loss and has low thermal impedance.

Another particular object of the present invention is to provide a self-supporting, flat, coreless layered substrate that can accommodate ICs using flip chip assembly processes and/or wire assembly.

Such a substrate can also be provided in a single unit or in a multi-cell manner prior to IC assembly, and these multiple units can be arranged in a matrix array or in a strip array.

Another object of the present invention is also to provide a substrate fabrication process and a substrate made therefrom. The inner layer of the substrate comprises a plurality of layers using a power source and a ground metal layer, has a low density, a large pitch, and a suitable metal layer. It has a low electrical resistance and therefore prevents overheating.

Another object of the present invention is also to provide a substrate fabrication process and a substrate made therefrom, the substrate comprising a layer or layers on both sides of the central substructure, the layers being prepared at the same time and under the same preparation conditions. It is prepared to withstand the balance of residual stress and has good flatness. In a first aspect, it is an object of the present invention to provide a method of fabricating a freestanding film that is the basis of an electronic support structure, the film comprising an array of vias in an insulating material, and the method of fabrication comprising stages: I-fabricated on a sacrificial carrier a film comprising conductive vias surrounding the insulating material; II - stripping the film from the sacrificial support to form a freestanding layered array.

Stage I contains substeps: (i) plating a barrier metal layer on the sacrificial carrier; (ii) adding a copper seed layer to the barrier metal layer; (iii) adding a photoresist layer to the copper seed layer, exposing and developing Forming a photoresist pattern; (iv) plating a copper via in the photoresist pattern; (v) stripping the photoresist layer, leaving an upright copper via; (vi) stacking an insulating material over the copper via The freestanding film thus formed contains an array of copper vias in the insulating matrix.

In another embodiment, stage I includes sub-steps: (i) adding a photoresist layer directly on the sacrificial carrier, exposing, developing, forming a photoresist pattern; (ii) line plating in the formed photoresist pattern Into the barrier metal; (iii) line-plating copper vias on the line-plated barrier metal; (iv) stripping the photoresist layer to expose the copper vias; (v) stacking the insulating material outside the exposed copper vias.

Step II includes the steps of: (vi) removing the sacrificial carrier layer, thereby forming an electronic substrate comprising a copper structure comprising a barrier metal layer within the insulating matrix.

In a second aspect, the present invention is to provide a freestanding through-hole film comprising an array of vias surrounded by an insulating material prepared by the above method.

Thirdly, the present invention provides a method of fabricating an electronic substrate, the method comprising at least Included: I- fabricating a film comprising conductive vias surrounded by an insulating material on a sacrificial carrier; II- stripping the film from the sacrificial carrier layer to form a free-standing layered array; V-thinning, leveling; VI- Assembly; VII-terminal phase.

Typically, the conductive vias can be fabricated by copper plating, which is selected from electroplating and electroless plating.

Stage I comprises sub-steps: (i) plating a barrier metal layer on the sacrificial carrier, (ii) adding a copper seed layer to the adhesion metal layer; (iii) adding a photoresist layer on the copper seed layer for exposure, Developing, forming a photoresist pattern; (iv) plating a copper via in the photoresist pattern; (v) stripping the photoresist layer, leaving an upright copper via; (vi) stacking the insulating material over the copper via Stage II includes sub-steps: (vii) removing the sacrificial carrier layer; (viii) removing the barrier metal layer, and the resulting electronic substrate contains a copper structure in the insulating matrix.

Typically, in this embodiment, the barrier metal layer comprises at least one of the following features:

(a) The barrier metal layer is selected from the group consisting of tantalum, tungsten, chromium, titanium, titanium-tungsten, titanium-niobium combination, nickel, gold, nickel-back gold layer, gold-plated nickel layer, tin, lead, lead layer Tin layer, tin-lead alloy, tin-silver alloy, the barrier metal layer is prepared by a physical vapor deposition process.

(b) The barrier metal layer is selected from the group consisting of nickel, gold, nickel back gold layer, gold layer back nickel layer, tin, lead, lead layer back tin layer, tin-lead alloy, tin-silver alloy, and the barrier metal layer passes Prepared by a method selected from electroless plating and electroplating.

(c) The barrier metal layer has a thickness of from 0.1 μm to 5 μm.

As an alternative, the method further comprises a stage III: adding a metal functional layer and an additional via layer to form an internal substructure comprising a central metal layer film surrounded by the via layer, whereby The electronic substrate established on the internal substructure includes an odd number of metal functional layers.

Typically, Stage III includes sub-steps: (a) adding a photoresist layer, exposing, developing, forming a functional pattern; (b) adding a copper layer to the functional pattern; (c) stripping the photoresist; (d) adding a a photoresist layer, exposing and developing to form a via pattern; (e) electroplating copper in the via pattern to form a copper via; (f) stripping the second photoresist layer; (g) etching away the copper seed layer; (h) laminating the insulating material.

As an alternative, the method comprises Stage IV: adding another internal functional layer, followed by adding another internal via layer to form an internal substructure comprising a central via layer surrounded by the functional layer, on which the internal substructure is The established electronic substrate includes an even number of metal functional layers.

Typically, the stage IV of adding another internal functional layer and via layer comprises the steps of: (i) thinning, leveling the layered insulating material added in step (h), exposing the copper pass added in step (e) (j) adding an adhesion metal layer such as titanium, chromium, nickel chromium to the outer surface exposed by the copper through hole and the surrounding insulating material; (k) adding a copper seed layer on the adhesion metal layer; (l) adding a second functional layer of the photoresist on the copper seed layer, performing exposure and development to form a second functional pattern.

(m) adding a metal functional layer on the second functional pattern; (n) stripping the second functional layer of the photoresist; (o) adding a third via layer of the photoresist, exposing and developing to form a third via pattern; (p) plating copper in the third via pattern to form a third copper via layer; (q) stripping the third layer of the photoresist; (r) etching away the copper seed layer and the attached metal layer; (s) laminating a layer of insulating material.

As an alternative, the manner of thinning and leveling the insulating material added in the step (h) in the step (i) is selected from the group consisting of mechanical grinding, chemical mechanical polishing, dry etching, and multi-step using two or more of the above techniques. Process.

Stage I comprises sub-steps: (i) adding a photoresist material directly on the sacrificial carrier, exposing, developing, forming a photoresist pattern; (ii) plating a barrier metal in the formed photoresist pattern; (iii) A copper plated through hole is formed on the barrier metal of the line plating; (iv) the photoresist is stripped to expose the copper via; and (v) the insulating material is stacked on the exposed copper via.

Stage II comprises sub-step (vi) removal of the sacrificial support; thus, the resulting electronic substrate contains a copper structure having a barrier metal layer within the insulating matrix.

A typical barrier metal layer has at least one of the following features: (a) the barrier metal layer is selected from the group consisting of nickel, gold, nickel back gold layer, gold layer back nickel layer, tin, lead, tin layer lead layer, tin lead The alloy, the tin-silver alloy, and the barrier metal layer are prepared by a method selected from the group consisting of electroless plating, electroplating, or a combination thereof; (b) the barrier metal layer has a thickness of 0.1 μm to 5 μm.

As an alternative, the fabrication method comprises an additional stage III: adding a first metal functional layer and a second via layer to form an internal substructure comprising a central metal functional layer film surrounded by a via layer, whereby The electronic substrate established on the internal substructure contains an odd number of metallic functional layers.

Typically, Stage III: adding a first metal functional layer and a second via layer to form an internal substructure comprising a central metal functional layer film surrounded by a via layer, the stage III comprising the steps of: Vii) adding an adhesion metal layer, such as titanium, chromium, nickel chrome, to the surface exposed in step (vi), the exposed outer surface comprising a copper via end surrounded by an insulating material covered by a barrier metal; (viii) Adding a copper seed layer to the adhesion metal layer; (ix) adding a first functional photoresist layer on the copper seed layer, performing exposure and development to form a functional pattern; (x) adding a copper layer to the functional pattern; (xi) Stripping the first functional photoresist layer; (xii) adding a second via photoresist layer, exposing and developing to form a second via pattern; (xiii) plating copper in the second via pattern to form a second copper a via layer; (xiv) stripping the second via photoresist layer; (xv) etching away the copper seed layer; (xvi) removing the adhesion metal layer; (xvi) Stacking an insulating material on the exposed second via layer.

The manufacturing method of the present invention further includes a stage IV: adding a second functional layer and a third via layer to form an internal substructure including two functional layers surrounding a central via layer, and electrons established on the basis of the internal substructure The substrate has an even number of metallic functional layers.

Adding the additional functional layer and the third via layer to the stage IV may include the steps of: (xviii) laminating the insulating material added in the thinning and leveling step (xvii), exposing the copper via hole added in the step (xiii) (xix) adding an adhesion metal layer such as titanium, chromium, nickel chromium on the exposed outer surface of the through hole and the surrounding insulating material; (xx) adding a copper seed layer on the adhesion metal layer; Xxi) Further adding a photoresist layer on the copper seed layer, performing exposure and development to form a functional pattern.

(xxii) adding copper in the step (xxi) functional pattern to form a second functional layer; (xxiii) removing the photoresist layer added in the step (xxi); (xxiv) adding another photoresist layer, exposing and developing Forming a third via pattern; (xxv) plating copper in the third via pattern to form a third copper via layer; (xxvi) stripping the other photoresist layer; (xxvii) etching away the copper seed layer and Attaching a metal layer; (xxviii) laminating a layer of insulating material.

Typically, the insulating material used throughout the process is a fiber reinforced resin composite.

Alternatively, the insulating material may comprise a resin selected from the group consisting of thermoplastic resins, thermosetting polymeric resins, and resins having thermoplastic and thermosetting properties.

In a preferred embodiment, the insulating material comprises an inorganic particulate filler having at least one of the following features: (a) the inorganic particulate filler comprises ceramic or glass particles; (b) the particle size is on the order of microns; The filler weight percentage is 15%-30%.

The insulating material is a fiber matrix composite comprising fibers selected from the group consisting of organic fibers and glass fibers, which may be chopped fibers or continuous fibers, arranged in a twill or woven manner.

Alternatively or preferably, the insulating material is a prepreg comprising a fiber mat pre-impregnated with a partially cured polymeric resin.

Typically, the step II of stripping the layered cylindrical via structure from the sacrificial carrier layer to form a freestanding layered array comprises the step of etching away the sacrificial carrier by an etching process.

Typically, Stage V of the present invention and other sanding and leveling processes, including the steps of sanding and leveling the insulating material to expose the underlying outer via surface, may be accomplished using one of the following techniques: mechanical grinding, chemical mechanical polishing (CMP), dry etching, and a multi-step process in which two or more of these techniques are combined.

Typically, the method includes an additional stage VI in which a growth functional layer and a via layer are formed on both sides of the membrane.

As an alternative, the additional stage VI comprises the steps of: (a) adding an adhesion metal layer on either side of the flat inner substructure, the adhesion metal layer being selected from titanium, chromium or nickel chromium.

(b) adding a copper seed layer on the adhesion layer; (c) adding a photoresist layer, performing exposure and development to form a first external photoresist pattern of the first external functional layer; (d) in the first photoresist The first external functional layer is electroplated in the pattern; (e) stripping the first outer photoresist pattern of the first outer functional layer; (f) adding a photoresist layer, exposing and developing to form a first outer via layer a second external photoresist pattern; (g) a line is plated into the first outer copper via layer in the second outer photoresist pattern; (h) stripping the second outer photoresist pattern; (i) etching away the copper seed layer And an attached metal layer; (j) stacking an insulating material on the exposed copper functional layer and the via layer; (k) thinning and leveling the insulating material until the outer surface of the via layer is exposed.

Alternatively, steps (a) through (k) above may be repeated one or several times to establish the desired additional outer layer.

The finalization of Phase VII can include the following steps: (i) adding an adhesion metal surface layer such as titanium, chromium, nickel chromium on the outer layer of the stacked structure; (ii) adding an external copper seed layer on the externally attached metal surface layer; (iii) adding, exposing and developing light a layer of glue to provide a pattern structure; (iv) adding copper pads and copper lines to the pattern structure; (v) stripping the photoresist layer; (vi) adding a masking photoresist layer to block the copper lines and the copper seed layer, Exposing the copper pads provides the final metal pattern.

(vii) plating a termination layer on the exposed copper pad, the termination layer being made of a metal selected from the group consisting of nickel, gold, tin, lead, silver, palladium, nickel gold, tin silver, and alloys thereof; (viii) stripping off the masking photoresist layer; (ix) removing the exposed copper seed layer and the exposed adhering metal layer; (x) adding a solder mask layer, exposing and developing, shielding the wires to expose the terminal metal layer.

As an alternative, stage VII: terminating the electronic support structure may comprise the steps of: (i) adding an externally attached metal surface layer on the outer layer of the stacked structure; (ii) adding an external copper seed layer to the externally attached metal surface layer; (iii) adding an external photoresist layer on the external copper seed layer; (iv) exposing and developing the external photoresist layer to form a patterned structure; (v) adding copper pads and wires to the above pattern structure; (vi) removing the outer photoresist layer; (vii) removing the exposed copper seed layer and the exposed adhesion metal layer; (viii) adding a solder mask Layering, exposing, developing to mask the copper wire to expose the copper pad; (ix) electroless plating a termination layer on the exposed copper pad, the termination layer being made of a metal selected from the group consisting of nickel, gold, Tin, lead, silver, palladium, nickel gold, tin silver, alloys and corrosion resistant polymeric materials.

In another aspect, it is an object of the present invention to provide a structure having an even number of functional layers produced by the above method.

In another aspect, it is an object of the present invention to provide a structure having an odd number of functional layers produced by the above method.

In another aspect, it is an object of the present invention to provide a substantially symmetrical structure made by the above method.

The present invention relates to a novel fabrication process for fabricating an electronic substrate and a novel electronic substrate obtained by the above process. Some of the fabrication steps, such as photoresist addition, exposure, development, and subsequent removal steps are not discussed in detail here, as the materials and processing flows in these steps are common knowledge, and if discussed in detail herein, The instructions are very cumbersome. It can be said exactly, the technology in the field Personnel can make appropriate choices for the manufacturing process and materials based on parameters such as specifications, substrate complexity, and components. In addition, the actual construction of the base material is not described. In fact, the present invention provides a method of fabricating a variety of wafer support structures. The following discussion relates to a novel, versatile method of fabricating a multilayer substrate in which various conductive layers are interconnected by vias through the insulating layer to form a three-dimensional stacked structure.

4 is a basic flow diagram of the key steps in the method of making the substrate of the present invention, the method comprising: Stage Ia - fabricating a film comprising conductive vias surrounded by an insulating material on a sacrificial carrier using a full-plate plating technique, or stage Ib-Using a line plating technique to fabricate a film comprising conductive vias surrounded by an insulating material on a sacrificial carrier; both techniques and their corresponding advantages are discussed in detail below.

In stage II, the film is peeled off from the sacrificial carrier layer, and the remaining stress is removed before the other layer is added to be fixed in the multilayer structure. In this way, a very high level of flatness is obtained, as an alternative, for a plurality of layer structures, one or two additional layers can be made on one side of the film, as described in the alternative stages III and IV below. . In stage V, the structure is thinned and flattened to form a flat inner substructure. Stage VI, where both sides of the substructure are added in pairs to obtain the desired structure, such a process can obtain (at least substantially) a symmetrical structure, and Figures 5a and 5b are schematic views of two such structures, depicting as follows. In Figures 5a and 5b, Stage III is followed by a leveling phase V, directly on the basis of a free-standing membrane, adding an even number of metal functional layers to form so-called 2-0-2 and 3-0-3 structures, also Is in insulation There are two and three symmetrical metal functional layers on the via layer in the film.

Thus, in the example of the even-numbered symmetric structure as shown in FIG. 5a, the layered structure includes two pairs of metal functional layers 38, copper pads T8, connected by copper vias 4, 34, and four layers as shown in FIG. 5a. The structure includes two pairs of external metal functional layers 38 and copper pads T8 respectively disposed on both sides of the substructure of the film having copper through holes in the insulating material, and thus is referred to as a 2-0-2 support structure, and is also referred to as The adhesion metal layer 6 and the copper seed layer 2 are shown. This structure is terminated with a termination metal layer 98 and a solder mask 99. The fabrication process and selection process are discussed in detail below.

In the example shown in the six-layer structure in FIG. 5b, the layered structure includes three pairs of metal functional layers 28, 38 and copper pads T8 disposed on both sides of the copper via hole in the insulating film structure, and thus is referred to as 3 -0-3 structure. Both the 2-0-2 structure in Fig. 5a and the 3-0-3 structure in Fig. 5b include a stack of symmetrical layers disposed around the copper vias 4 in the insulating film 5. The substrate is provided with three metal functional layers 28, 38, copper pads T8 on each side of the layered array. The metal functional layers 28 on both sides of the stacked array are identical and applied simultaneously (i.e., simultaneously deposited) as described below.

The symmetrical structure shown in Figures 5a and 5b comprises a copper plated layer 28, 38, a copper pad T8, vias 4, 34, 44, and an insulating material 5, preferably an insulative material 5, as described below .

However, the infrastructure can be modified. For example, as shown in Figure 4, phase III is added before phase V based on specific structural requirements: additional metal functional layers and via layers are added to create a symmetrical, odd-numbered layer. Internal substructure As shown in Fig. 15, the configurations of 2-1-2 and 3-1-3 shown in Figs. 16 and 17, respectively, can be constructed.

Where an even number of layers is required but not critical for strict symmetry, after stage III, before stage V, stage IV is added: a second additional metal functional layer and a central layer are added to obtain a semi-symmetrical structure as shown in FIG. This structure is stronger than the through hole in the insulating film shown in Fig. 6, but it is not true symmetry.

The core of the present invention is the fabrication of a freestanding film comprising an array of vias bonded together by an insulating material, as shown in Figure 6 as a specific embodiment of such a freestanding film, another variation being shown in Figure 8, The free-standing membrane is the structural basis for all of the following structures, and the fabrication steps are also the basic steps of the following process.

As shown in FIG. 12, and particularly as shown in FIG. 14, the overall process includes fabricating an array of copper structures including layers 8, 18 and vias 4, 14, 24 on the sacrificial carrier 0, surrounding the insulating material between the layers and the holes. 5. The insulating material is preferably a fiber reinforced composite insulating material produced by a lamination process. After being peeled off from the sacrificial carrier layer, metal functional layers 28, 38, copper pads T8 and vias 34, 44 are added on both sides of the film, the film is converted into an internal substructure, and then a terminal is added thereto The metal layer 98 and the solder mask 99 constitute a support structure for use as a wafer support.

The adhesion metal layer 6 serves to facilitate adhesion of the copper to other materials, and may also include a line plating barrier 1' in the copper structure if required by the process. Since both the adhesion metal layer 6 and the barrier layer 1' are thin layers of high-purity conductive metal, the electrical resistance of the monolithic conductive structure is hardly affected.

Due to the lamination of the layered symmetrical or substantially symmetrical free-standing multilayer substrate having an array of through holes, the outer layer is simultaneously mounted on both sides, so that the polymer resin of the insulating material shrinks during the curing process. The stresses tend to cancel each other out, thereby achieving high flatness and improved yield, so that the multilayer substrate of the present invention can serve as a medium for ICs and printed circuit boards, providing good contact for both.

The inner substructure may be a layered array, typically a via layer 4 wrapped within an insulating material 5. A metal functional layer 28 (shown in Figure 10) can be added to both sides of the internal substructure, followed by a terminal metal layer (as shown in Figure 11). This deformation can produce a substantially symmetrical, thin, with an even number of metallic functional layer support structures. It is also possible to simultaneously add the external metal functional layer 38 and the copper pad T8 on both sides, thereby forming a more complicated structure.

In some fields of application, only an odd number of metal layers are required. In this case, of course, the production process of the even layer can also be used, and only a metal functional layer is vacant, and the signal is not transmitted in the XY plane.

However, in order to avoid waste and to minimize the thickness of the support structure, the fabrication process can be modified. The internal substructure of the support structure has a central metal functional layer which is sandwiched by the through holes to form a sandwich structure. An outer layer can also be deposited on the outside of 8. In this way, a substantially symmetrical structure with a central metal functional layer 8 and an odd number of metal layers is obtained.

The structure produced by the manufacturing method of the present invention can greatly reduce the remaining Force and warpage caused by it, especially in those cases with relatively complicated structures, since the original layered array film is peeled off from the sacrificial carrier layer by stretching, straightening and shrinking it The residual stress is relieved, and then as an internal substructure, various outer layers are added on both sides of the film to obtain a complete structure. Since the outer layer is simultaneously added on both sides at the same time, the same residual stress is generated on both sides, and these stresses cancel each other out, and the substructure is not bent and deformed, thereby ensuring flatness.

As shown in FIG. 6, the core structure of the present invention is a free-standing film Ia comprising a via array 4 surrounded by an insulating material 5, which is on the copper seed layer 2. The description of the free-standing film Ia and its deformation Ib as shown in Fig. 8 are as follows, and these films are the basis for the establishment of various substrates in the present invention.

FIG. 7 is a schematic view showing the manufacturing process of the free-standing film shown in FIG. 6. For ease of understanding, the preparation process and the intermediate structure are as shown in FIGS. 7(i) to 7(viii). As shown in Fig. 7, Fig. 7(i) to Fig. 7(viii), step 7(i): the barrier metal layer 1 is entirely plated on the sacrificial carrier 0, and the typical metal is copper. The sacrificial carrier 0 is typically 75 microns to 600 microns thick and is typically copper or a copper alloy such as brass or bronze. The barrier metal layer 1 may be made of the following materials: tantalum, tungsten, chromium, titanium, titanium-tungsten combination, titanium-niobium combination, nickel, gold, nickel back gold layer, gold layer back nickel layer, tin, lead, lead layer back tin layer , tin-lead alloy, tin-silver alloy, the barrier layer is prepared by physical vapor deposition (PVD), such as sputtering. The barrier metal layer in step 7(i) is made of nickel, gold, nickel layer, gold layer, gold layer, nickel layer, tin, lead, lead layer, tin layer, tin-lead alloy, tin-silver alloy, etc. The layer can be electrolessly plated or plated or both Prepared in a combined manner. The typical thickness of the barrier metal layer 1 is generally from 0.1 micrometer to 5 micrometers.

An adhesion metal layer can be added on the barrier metal layer 1, which can help deposit copper on other metals. However, if a suitable barrier metal layer 1 is carefully selected, the adhesion metal layer is not required. Step 7 (ii), adding a copper seed layer 2 on the barrier metal layer 1, the copper seed layer having a thickness of 0.2 μm to 5 μm, which may be subjected to physical vapor deposition, for example, after sputtering, by electroplating or electroless plating or Prepared in a combined manner. Step 7 (iii), adding a photoresist layer on the copper seed layer 2, exposing and developing to form a photoresist pattern, which is achieved by a conventional electronic substrate or a method commonly used in equipment preparation processes. In step 7 (iv), a copper via 4 is added to the photoresist pattern 3, and the copper via 4 is located on the copper seed layer 2. The copper vias 4 are typically prepared by electroplating, specifically by a process known as line plating.

In step 7 (v), the photoresist layer 3 is stripped leaving the upright copper vias 4. In step 7 (vi), the insulating material 5 is superposed on the outer layer of the copper through hole 4. The insulating material 5 may be composed of a thermoplastic material such as polytetrafluoroethylene and its derivatives, or a thermosetting polymer gum such as maleimide triazine, epoxy resin, polyimide, and these materials. The composition of the mixture. The insulating material 5 using polyimide as a main material is preferably capable of adding an inorganic particulate filler, usually ceramic or glass particles, having a particle size on the order of micrometers, specifically, a particle size of 0.5 to 5 μm; In the polymeric matrix material, the particulate filler has a weight percentage of 15% to 30%.

In a preferred embodiment, the insulating material 5 is a fiber matrix composite material, packaged It contains organic fibers such as polyimide fibers (fiber B) or glass fibers. These fibers may be short fibers or continuous fibers, arranged in a diagonal interlacing manner or in a cloth weave. The pre-impregnated body is arranged by a diagonal interlacing method pre-impregnated with a partially hardened polymeric resin or according to a cloth weave.

In most preferred embodiments, the polymer matrix uses at least two woven fiber prepreg materials - the matrix composite comprising the prepreg material contains a ceramic filler. Epoxy materials and polyamide matrix woven prepreg materials were supplied by Rancho Cucamonga, Ca, Arlon, USA. These prepreg materials are used on the copper substructure of the via and then cured by a hot press lamination process. The continuous fibers that penetrate the insulating layer can provide additional strength and stiffness, thereby making the overall structure thinner and more easily flatter. In step 7 (vii), the sacrificial carrier 0 is removed by a wet etching process, and the barrier metal layer 1 formed in the step 7 (i) is used as an etch stop layer. The sacrificial carrier is generally copper or a copper alloy, and a suitable etchant is generally selected according to the barrier metal layer 1. For example, when the barrier metal layer 1 is germanium, etching in the wet etching process of etching the sacrificial carrier 0 in step 7 (vii) is performed. The ammonium hydroxide solution is used as the agent, and the wet etching process is completed at a higher temperature. Step 7 (viii), removing the metal barrier layer, for example, when the metal barrier layer is germanium, it can be plasma etched away by a mixture of CF4 and Ar, and is typically formulated to have a CF4 and Ar ratio of 1:1 to 3:1; The metal can be removed by other well known techniques.

Figure 8 is a variation of the freestanding membrane core structure (Ia - as shown in Figure 4) shown in Figure 6 (Ib - as shown in Figure 4). As shown in Figure 6, Ia, freestanding membrane Ib A copper via 4' surrounded by an insulating material 5' is included, and Ib is slightly modified for Ia. However, each of the copper via holes 4' is disposed on the barrier metal thin layer 1', and finally the barrier metal layer is placed in the substrate of the present invention.

The optional structure Ib shown in Fig. 8 can be fabricated by the preparation process in the flow chart shown in Fig. 9, the intermediate step of which is as shown in Figs. 9(i) to 9(vi).

Referring to the steps and structures shown in Figs. 9, 9(i) to 9(vi), as shown in Fig. 9(i), the photoresist pattern 3 is coated, exposed and developed on the sacrificial carrier 0. As shown in Fig. 9(ii), a barrier metal layer 1' is added to the formed photoresist pattern. As shown in Figure 9(iii), the copper via 4' is line-plated on the line plating barrier metal layer 1', typically using an electroplated copper process, as necessary for the process described in Figure 7 above, with only necessary corrections . As shown in Fig. 9(iv), the photoresist pattern 3 is peeled off, and then the insulating material 5 is laminated on the outside of the bare copper via 4' as shown in Fig. 9(v). Finally, as shown in Fig. 9(vi), the sacrificial carrier 0 is removed. Among these steps, the selection of the insulating material 4, the barrier metal 1', and the fabrication flow is the same as that of Ia shown in Fig. 7, and only necessary corrections are made thereto.

Depending on the selected full-plate plating (as in Figure 7) or the line plating (Figure 9) process, and the final structural requirements are an odd or even number of metal functional layers, various support structures and correspondingly selected fabrication processes in the present invention It will be different. Thus, the present invention is directed to a generalized technique comprising a series of different process flows and correspondingly obtained structures.

Referring to Figure 10, a metal functional layer can be added on both sides of the internal substructure X. 28 obtained a "1-X-1" coreless support structure - stage V as shown in FIG. If the metal functional layer 28 is added and the vias 34 and the additional metal functional layer 38 (shown in Figure 5a) are added simultaneously on both sides, a "2-X-2" coreless support structure can be obtained. Therein, there are many variations of the internal substructure X, which are assembled on one side of the film Ia or Ib. Some of these different internal substructures are described below, with reference to various examples.

As shown in FIG. 10, the steps of simultaneously adding the external functional layer and the via layer are: first, in step 10(i), the adhesion metal layer 6 is added on both sides of the flat internal substructure X, and the adhesion of the metal layer 6 contributes. Copper adhesion is especially important when depositing copper onto the insulating material 5. The adhesion metal layer 6 is usually made of the following materials: titanium, chromium or nickel chromium. In step 10(ii), a copper seed layer is added after the metal layer 6 is attached. Step 10 (iii), followed by the addition of a photoresist pattern 7, exposure and development. In step 10 (iv), the copper functional layer 28 is electroplated in the photoresist pattern. In step 10 (v), the photoresist layer 7 is stripped.

In step 10 (vi), a pair of second photoresist layers 33 are added to perform exposure and development. In step 10 (vii), the copper vias 34 are electroplated in the photoresist layer. In step 10 (viii), the second photoresist layer 33 is peeled off. In step (ix), the copper seed layer and the attached metal layer are etched away. It is worth noting that typically the thickness of the seed layer is much smaller than the copper functional layer on which the circuit is plated, although it is difficult to clearly depict this actual contrast relationship in the cross-sectional schematic of Figures 10(i) through 10(xi). Step 10 (x), adding a layer of insulating material 5 on the metal functional layer 28 and the via layer 34 on both sides, the entire stack continues to change thick. In step 10 (xi), the insulating material layer 5 is thinned and flattened until the outer edge of the through hole 34 is exposed.

By adding other external functional layers 38, T8, etc. (as shown in Fig. 5b) on both sides of the growth structure, a more complicated structure can be formed, whereby step 10 (i) can be repeated according to the needs of the final structure. ) To 10 (xi), make more via layers and conductive functional layers.

Finally, the substrate including the inner substructure and the outer structure terminates. Figure 11 shows the final termination process, and Figures 11(i) through 11(x) show the steps of the finalization process.

11 and 11(i) to 11(x), the termination stage VII is a multi-step process comprising the following steps: Step 11 (i), first, adding an external adhesion metal layer 6 on the outer layer of the stacked structure Y . Step 11 (ii), subsequently, adding the external copper seed layer 2 on the external adhesion metal layer 6, step 11 (iii), adding a photoresist layer T7 on the outermost copper seed layer, the photoresist layer T7 was exposed and developed to obtain a photoresist pattern structure. In step 11 (iv), a copper pad T8 and a wire are added to the above pattern structure. In step 11 (v), the photoresist layer T7 is peeled off. In step 11 (vi), a final photoresist layer 97 is added, exposed and developed to expose the copper pad T8. In step 11 (vii), the terminal metal layer 98 is electroplated on the exposed copper pad T8. The termination metal layer 98 can be a nickel, gold, or nickel post-gold layer, tin, lead, silver, palladium, or an alloy of the foregoing. In step 11 (ix), the copper seed layer 2 and the external adhesion metal layer 6 are etched away. Step 11 (x), adding a solder mask 99 for exposure and development, and having a choice The underlying copper pad T8 and the terminal metal layer 98 are exposed.

Thus, on the basis of the film Ia, by performing steps 10(i) to 10(xi) twice, and then performing steps 11(i) to 11(x), 2 as shown in FIG. 5(b) can be obtained. -2-2 structure.

In the finalization step, different materials and fabrication processes can be selected. One possible termination step involves adding a conductor layer to the outer surface (above and below) of the stack. This termination step involves the following substeps: (a) Thinning The base insulating material on both sides may be exposed by mechanical grinding, or chemical mechanical polishing (CMP), or dry etching or a combination of the above methods to expose the outer surface of the copper through hole, and (b) in the stacked structure Adding an externally attached metal layer to the outer surface; (c) continuing to add an external copper seed layer on the externally attached metal layer; (d) adding a photoresist layer on the outermost copper seed layer; (e) performing a photoresist layer Exposure, development, obtaining a photoresist pattern structure; (f) adding a copper pad and a wire in the photoresist pattern structure; (g) removing the photoresist layer to leave a copper seed layer, a copper pad and a wire (h) etching away the exposed copper seed layer and the exposed adhesion metal layer; (i) adding a solder mask, exposing, developing, shielding the wire to expose the copper pad. (j) Electroless plating, plating the terminal layer on the exposed copper pad, the terminal layer may be a nickel, gold, or nickel layer, or a gold layer, a nickel layer, tin, lead, silver, Palladium and alloys of these metals as well as resist polymer materials.

However, although the structures in Figures 5a and 5b have been optimized in a number of ways, in some cases, the electronic design of the substrate requires the thickness of the stacked array layers ("internal substructures" of Figures 5a and 5b) to be as large as possible. Reduced. Because of these internal substructures Natural brittleness, which jeopardizes the yield of the step process detailed above. There are some variations in the process described above to solve the above problems, resulting in some differences in structure.

Example

FIG. 12 is a schematic cross-sectional view showing a "2-0-2" type symmetrical, coreless support structure including a barrier metal layer 1', by performing the deformation Ib shown in FIG. 8 in FIGS. 10 and 11. The process is processed. The deformed structure in Fig. 12 is similar to the structure in Fig. 5a, but the deformed structure includes the barrier metal layer 1'. This structure was prepared by the macro stages Ib, II, V, VI and VII shown in FIG.

The process flow for producing the "2-0-2" type symmetrical, coreless support structure shown in Fig. 12 is shown in Figs. 13 and 13(i) to 13(xxvii). First, in steps 13(i) to 13(vi), the structure of the film Ia is produced. These steps are the same as those in the process of forming the film 8 in Figs. 9(i) to 9(vi), and only necessary modifications are made. In step 13(vii), the structure formed in step 13(vi) is thinned to expose the copper via. This step is substantially the same as phase V in FIG. The inner substructure after grinding to date is assembled on both sides by the preparation process as shown in Fig. 10, and the intermediate structure of Figs. 13(viii) to 13(xviii) is obtained by steps 10(i) to 10 shown in Fig. 10 ( Xi)--that is, the phase V in Figure 4. The structure "1-0-1" in Fig. 13 (xviii) passes through the intermediate structure as shown in Fig. 13 (xix) to Fig. 13 (xxviii), and these intermediate structures correspond to the step 11 (i shown in Fig. 11). ) to 11 (x), wherein the deformation of the structure is obtained by the intermediate structures 13 (xxiii) to 13 (xxvii) "2-0-2" structure.

Figure 12 is similar to Figure 5a, but it has a barrier metal layer 1' formed by a line plating process to form a separate via film (as shown in Figure 9(vi)), which is retained and bonded to the final structure. As one.

Since the barrier metal layer 1' is conductive, in many applications, the introduction of the barrier metal layer is not problematic, and its introduction is very useful for reducing residual stress. 14 is a schematic cross-sectional view of a "3-0-3" type symmetrical, coreless support structure, the fabrication process of which is shown in FIG. 13, and the flow in FIG. 13 includes flow 9, flow 10, and repeat step 13 (viii). ) to 13 (xvii), followed by process 11.

Fig. 14a is a flow chart showing the preparation of the structure shown in Fig. 14 which is produced by using the steps of Figs. 10 and 11 for the film shown in Fig. 6.

Figure 16 shows a 2-1-2 structure. The internal substructure includes a central metal functional layer 8 with through-hole layers 4, 14 on both sides. The fabrication process of the structure is shown in Figure 15a.

As shown in FIG. 15a, the stage of fabricating the inner core substructure of the odd layer symmetric layer structure comprises the following steps: step (i), first, the barrier metal layer 1 is entirely plated on the sacrificial carrier 0. In step (ii), a copper seed layer 2 is added to the barrier metal layer 1. In step (iii), the first photoresist pattern 3 is added to the seed layer 2, and exposure and development are performed to form a via pattern. Step (iv), plating copper in the photoresist pattern 3 by electroplating or electroless plating Copper through hole 4. In the step (v), the first photoresist pattern 3 is peeled off, leaving the upright copper via 4 . In step (vi), the insulating material 5 is stacked on the copper via holes. In step (vii), the sacrificial carrier 0 is removed. In step (viii), the barrier metal layer 1 is removed. The structure obtained by the above steps is the same as the structure Ia shown in Fig. 6, and the flow is identical to the method of Fig. 7, except that necessary modifications are made thereto.

Before entering the stage V shown in FIG. 4, the insulating material is ground to expose the copper via 4, and then the metal functional layer 8 and the second via layer are added on the exposed surface on which the barrier metal layer 1 is removed. 14 establish substructure X (as shown in Figures 10(i) through 10(xi)). Referring to Fig. 15(a), the preparation process is as follows: Step (ix), adding a second photoresist layer 7, exposing and developing to form a functional pattern. In step (x), a copper functional layer 8 is added to the functional graphic. In step (xi), the second photoresist layer is stripped. In step (xii), a third photoresist layer 13 is added to cover the gap of the copper functional layer 8, and exposure and development are performed to form a second via pattern on the copper functional layer 8. In step (xiii), copper is added to the via pattern to form the second copper via layer 14. In the step (xiv), the third photoresist layer 13 is peeled off to expose the copper functional layer 8 and the second copper via layer 14. Step (xv), etching the copper seed layer 2. In the step (xvi), the insulating material 5 is stacked on the functional layer 8 and the second copper via layer 14. In step (xvii), the insulating material is thinned and flattened to prepare for the subsequent preparation process.

Returning to Figure 4, after film Ia is prepared, Stage III is added prior to Stage V to create a symmetric internal substructure containing odd functional layers.

Figure 16 shows the 2-1-2 based on the internal substructure shown in Figure 15. The structure is the addition of two rows of via layers 34, 44 on either side of the internal substructure by employing the steps of Figures 10 and 11.

As shown in Fig. 17, the functional layer is further formed to form a 3-1-3 structure, which is modified as necessary for the structure shown in Fig. 16. The sub-step shown in Fig. 10 is repeated, and an external metal functional layer is further added on both sides of the internal substructure. 38 and via layer 44.

As shown in Fig. 18, an odd-numbered layered inner support structure for plating a via hole on an insulating film is shown. As shown in Figs. 18 and 18(i) to 18(xvii), the odd-numbered layer-symmetric internal support substructure shown in Fig. 18 is prepared by first plating a via hole on the insulating film Ib shown in Fig. 8 (step 18 (i) ) to 18(vi)), these steps correspond to the necessary modifications in steps 9(i) through 9(vi). In the following manner, only the one side of the film Ib is constructed, and in step (vii), the adhesion metal layer 6 is added instead of the stripped copper sacrificial carrier 0. In step (viii), a copper seed layer 2 is added to the adhesion metal layer 6. In step (ix), a second photoresist layer 7 is added, exposed and developed to form a functional pattern. In step (x), copper is added to the functional pattern to form the functional layer 8. In step (xi), the second photoresist layer 7 is peeled off. In step (xii), a third photoresist layer 13 is added, exposed and developed to form a second via pattern. In step (xiii), copper is electroplated in the second via pattern to form a second copper via layer 14. In the step (xiv), the third photoresist layer 13 is peeled off. In step (xv), the copper seed layer 2 and the adhesion metal layer 6 are etched away. In step (xvi), the insulating material 5 is stacked to the inner support structure, and the insulating material 5 is generally a prepreg layer. Step (xvii): Both sides of the stacked material are polished to expose copper through holes 4', 14.

Figure 19 is an odd layer symmetry formed in Fig. 18 including the barrier metal layer 1'. The deformation "2-1-2" structure based on the internal support substructure. By polishing both sides of the structure shown in Fig. 18, the insulating material 5 is removed, and the outer edges of the through holes 4', 14 are exposed and exposed (as shown in phase V), further increasing the outer functional layer 28 and the via layer 34, 16 Make the necessary changes.

Fig. 20 is a view showing a modified "3-1-3" structure based on the odd-numbered layered inner support substructure including the barrier metal layer 1' shown in Fig. 18. By grinding both sides of the structure shown in FIG. 18, the insulating material 5 is removed, the outer edges of the through holes 4', 14 are flattened and exposed (as shown in phase V), and the external metal functional layer 28 is further added by repeating step 10, 38 and the via layers 34, 44, Figure 16 can be modified as necessary.

The 2-0-2 and 3-0-3 even layer structures shown in Figures 5a and 5b, the films Ia and Ib shown in Figures 6 and 8 may be very fragile, and in some specific applications, due to design considerations, The thickness of the substructure is required to be minimized, so that the yield in the phase II phase V in Fig. 4 is lowered. Thus, although a through hole is added to the insulating film 1a shown in FIG. 6 and the insulating film 1b shown in FIG. 8, and a functional layer is simultaneously added on both sides, a symmetrical structure can be obtained, which has desirable characteristics, but some Specific processes that take into account material, endurance and dimensional requirements require modifications to these processes, sacrificing absolute symmetry for easy production and high yield.

The thickness of the through hole 4 or the through hole 4' and the selected insulating material 5 cannot ensure that the layered structure Ia or the layered structure Ib is sufficiently intact after the insulating material 5 is ground to expose the copper through hole 4 (4'). Sex, it is necessary to make a thicker structure on one side of the films Ia and Ib, which removes the excess insulating material 5 to expose the copper via 4 or the copper pass. Prior to the hole 4', the copper via 4 or the copper via 4' is covered with an under-polished insulating layer to form a reinforcing layer.

Therefore, when the structure requires an even number of metal functional layers, and for electrical considerations, a low-thickness film is required and productivity is increased, Stage II is followed by Stage III (as shown in Figure 15) to form a first internal metal functional layer 8 and The second via layer 14; Stage IV, to which the second metal functional layer 18 and the third via layer 24 are further added. Thus, a semi-symmetric inner layer structure "-2-" comprising two metal functional layers 8, 18 is formed, and after the thinning and flattening of the phase V, more external metal functional layers can also be constructed by the flow in FIG. 28, 38, and the outer via layers 34, 44, if this process needs to be repeated, then the termination process shown in Figure 11 is performed.

A substantially symmetrical internal "-2-" substructure constructed on the basis of the film Ia shown in Fig. 6 is shown in Fig. 21.

The substantially symmetrical inner "-2-" substructure can combine 4 and 6 metal functional layers to form "1-2-1" and "2-2-2" structures, respectively, which are substantially identical to Figure 5a. The "2-0-2" and "3-0-3" structures in Fig. 5b are identical in construction, except that the internal metal functional layers 8, 18 added one at a time are different.

As shown in Fig. 21a and Figs. 21b(i) to 21b(xxviii), for the fabrication flow of the structure shown in Fig. 21, steps 21(i) to 21(viii), the film Ia as shown in Fig. 6 is produced (Fig. 21a). Phase I and Phase II) in 4, and then combine this structure into the semi-symmetric internal structure in Figure 21 through Phase III (as shown in Figure 4). Here, step (ix) to step (xvi): the first metal functional layer 8 and the second via layer 14 are added, and then the insulating material layer 5 is stacked. Step (xvii): thinning the structure to expose the end of the second via layer 14. Then enter stage IV: adding a second metal functional layer 18 and a third via layer 24, corresponding to step 21 (xviii) to step (xxvii), then step 21 (xxviii) the entire structure is thinned and leveled ( Corresponds to stage V) in Figure 4.

The construction process is as follows: (stage I, stage II, ie step (i) to step (viii)), after obtaining the film Ia in FIG. 6, step (ix), adding the second photoresist layer 7, exposing and developing, forming Functional graphics. In step (x), a copper functional layer 8 is formed in the functional pattern. In step (xi), the second photoresist layer 7 is peeled off. In step (xii), a third photoresist layer 13 is added, covering the gap of the copper functional layer 8, exposed and developed, and a second via pattern is formed on the functional layer. In step (xiii), copper is electroplated in the second via pattern to form the copper via layer 14. In the step (xiv), the third photoresist layer 13 is peeled off to expose the copper functional layer 8 and the via layer 14. In step (xv), the copper seed layer 2 is etched away. In the step (xvi), the insulating material layer 5 is stacked on the surfaces of the exposed copper functional layer 8 and the copper via layer 14. Step (xvii), thinning and leveling the insulating material to expose the end of the copper via layer, the above content is Stage III.

Step (xix), after depositing another layer of the adhesion metal layer 6 (step (xviii)), deposit another layer of the copper seed layer 2. In step (xx), a fourth photoresist layer 17 is added, exposed and developed to form a second functional pattern. In step (xxi), a second copper functional layer 18 is formed in the functional pattern. Step (xxii), peeling off the fourth photoresist layer 17, In step (xxiii), a fifth photoresist layer 23 is added, covering a gap in the second functional layer 18, exposed and developed, and a third via pattern is formed on the second copper functional layer 18. In step (xxiv), the copper via layer 24 is formed by line plating in the third via pattern. Step (xxv): The fifth photoresist layer 23 is peeled off to expose the second copper functional layer 18 and the via layer 24. In step (xxvi), the adhesion metal layer 6 and the copper seed layer 2 between the via layers 24 are etched away. In step (xxvii), the insulating material layer 5 is stacked on the exposed surface of the second copper functional layer 18 and the via layer 24, which is the stage IV.

Such a thicker substructure having two functional layers, which is thinned and flattened in stage V, can generally be milled: the outer layer and the final stage VII are assembled by deposition.

Referring to Fig. 22, a semi-symmetric internal substructure corresponding to the structure shown in Fig. 21 can also be assembled on the basis of the wiring plating film shown in Fig. 8. The internal substructure is constructed in the same manner as the process shown in FIG. 21a except that the starting point is the substructure in FIG. 8 instead of the substructure in FIG.

Figures 22b(i) through 22b(xxviii) are intermediate structures generated corresponding to the steps in Figure 22a. Corresponding to stage I, the fabrication of the film Ib is shown in Fig. 22b(i) to Fig. 22b(v). Corresponding to Stage II, Figure 22b(vi) shows the etching of the sacrificial carrier layer, resulting in the freestanding film Ib shown in Figure 9. In Figs. 22b(vii) to 22b(xvi), the second functional layer 8 and the second via layer 14 are added to the freestanding film Ib to obtain a single layer substructure shown in Fig. 18. These steps correspond to stage III in the overall flow shown in FIG. In stage IV, the single layer structure continues the assembly process to form the bifunctional layer structure shown in Figure 22, ie, steps (xvii) through (xxvii), A second functional layer 18 and a third via layer 24 are formed. In stage V, step (xviii), the bifunctional layer is thinned and flattened. In stage VI, it is also possible to further add layers on both sides thereof to form the 1-2-1, 2-2-2 semi-symmetric support structure shown in FIG. 23 and FIG. 24, and the details of these processes refer to FIG. 10 and FIG. 10(i) to Figure 10(xi).

The semi-symmetric structure shown in Figs. 23 and 24 is constructed on the basis of the internal substructure shown in Fig. 21. The structure shown in the cross-sectional schematic views of Figures 23 and 24 is similar to the 2-0-2 structure and the 3-0-3 structure of Figures 5a and 5b, with only the necessary changes. But it is not really symmetrical in nature because its substructure is an asymmetrical form in the assembly process as described above. However, since the external functional layers are simultaneously deposited, they have similar thicknesses and process conditions, and the resulting substrate material is less likely to warp.

Similarly, the corresponding various semi-symmetric structures as shown in FIG. 25 and FIG. 26 are constructed on the basis of the internal substructure shown in FIG. 22, which is a semi-symmetric 1-2-1, 2 similar to the structure shown in FIG. 23 and FIG. -2-2 support structure, but it contains a line plating barrier metal layer 1' in the first stage, the barrier metal layer remains in the final structure, which can be clearly seen by comparing the structures shown in Figs. 12 and 14. The difference between the two production processes.

As noted above, the different multilayer substrates comprise optional conductive layers 8, 18, 28, 38, copper pads T8, etc., which have high conductivity for use as conductive paths, separated by an insulating material 5. It is expected that these conductive layers include resistors, in-layer capacitors, inductors, and the like. In general, a high resistance material is selected as the insulating material 5, which should have a suitable thickness and dielectric constant to match the capacitance and inductance values required by the substrate designer.

Therefore, those skilled in the art can dedicate that the present invention is not limited to the details and the details shown and described herein. Modifications are intended to fall within the scope of the appended claims.

In the claims, the word "comprise" and its conjugations "comprises" and "comprises" and the like are meant to include the elements or methods listed, but in general, the other elements and methods are not excluded.

100‧‧‧Base

102‧‧‧Electric conduction ball

104‧‧‧ pads

106‧‧‧Wire bonding

108‧‧‧ pads

110‧‧‧Integrated Circuit (IC)

112‧‧‧Resin materials

200‧‧‧Base

202‧‧‧ Ball Grid Array of Conductive Balls (BGA)

204‧‧‧ pads

206‧‧‧Electrical conduction bumps

208‧‧‧ pads

210‧‧‧Integrated Circuit (IC)

212‧‧‧Resin materials

214‧‧‧Insulation materials

216‧‧‧Metal reinforcement

218‧‧‧Adhesive layer

220‧‧‧ Cover

222‧‧‧ Thermal bonding layer

250‧‧‧Package

300‧‧‧Base

330‧‧‧ core part

332‧‧‧ copper conductor layer

334‧‧‧Organic insulation

336‧‧‧Metalized Through Hole (PTH)

338‧‧‧ copper conductor layer

340’‧‧‧Combination

340”‧‧‧Combination

342‧‧‧ copper conductor layer

344‧‧‧Insulation

346‧‧‧copper plated microvia

350‧‧‧Organic Flip Chip BGA

0‧‧‧ sacrificial carrier

1‧‧‧metal layer

1'‧‧‧ metal layer

2‧‧‧ copper seed layer

3‧‧‧Photoresist graphics

4‧‧‧through hole

4'‧‧‧through hole

5‧‧‧Insulation film

5'‧‧‧Insulation film

6‧‧‧metal layer

7‧‧‧Photoresist graphics

14‧‧‧through layer

24‧‧‧through layer

28‧‧‧Metal functional layer

33‧‧‧Second photoresist layer

34‧‧‧through hole

38‧‧‧Metal functional layer

44‧‧‧through hole

97‧‧‧Photoresist layer

98‧‧‧Terminal metal layer

99‧‧‧ solder mask

Ia‧‧‧Separate membrane

Ib‧‧‧Separate membrane

X‧‧‧internal substructure

Y‧‧‧Stacked structure

T7‧‧‧ photoresist layer

T8‧‧‧ copper pad

In order to better understand the present invention, how to implement it will be described, and the drawings will be described below by way of embodiments.

In the course of the detailed description of the drawings, the drawings are used in the discussion of the preferred embodiments of the present invention, and the principles and conceptual aspects of the present invention are provided by a method which is considered to be the most practical and easy to understand. . In this regard, a more specific structural description not necessary to provide a basic understanding of the invention is provided. Those skilled in the art can understand and implement several forms of the present invention in conjunction with the drawings and the accompanying drawings.

It should be noted that the cross sections of the layers and stacks are only schematic and not drawn to actual scale, and their thickness is enlarged. In addition, the substrates and fabrication processes described herein are applicable to a variety of end products and do not specifically describe the conductivity characteristics of each layer.

In the drawings: FIG. 1 is a schematic cross-sectional view of a prior art wire bonding IC BGA package structure; FIG. 2 is a cross-sectional view of a flip chip BGA package structure in the prior art; FIG. 3 is a prior art organic flip chip BGA substrate class. A schematic cross-sectional view of a support structure; FIG. 4 is a basic flow diagram of a macro stage of the fabrication process including the necessary stages (solid lines) and optional steps (dashed lines) for fabricating the support structure of the present invention; FIG. 5a is the first corresponding to the present invention. An embodiment has a cross section of a "2-0-2" symmetric coreless support structure of two functional layers distributed on each side of a through hole in an insulating film Figure 5b is a schematic cross-sectional view of a "3-0-3" symmetric coreless support structure having a functional layer on each side of three through-holes distributed in an insulating film in accordance with a second embodiment of the present invention; 6 is a schematic cross-sectional view of a free-standing through hole in an insulating film as a novel foundation of various supporting structure embodiments; FIG. 7 is a flow chart showing a manufacturing step of producing the free-standing film shown in FIG. 6; FIG. 7(i) is a view 7 is a schematic cross-sectional view of the intermediate structure obtained by the intermediate fabrication step; FIG. 7(ii) is a schematic cross-sectional view of the intermediate structure obtained by the intermediate fabrication step shown in FIG. 7; FIG. 7(iii) is the middle of FIG. A cross-sectional schematic view of the intermediate structure obtained in the fabrication step; FIG. 7(iv) is a schematic cross-sectional view of the intermediate structure obtained by the intermediate fabrication step shown in FIG. 7; and FIG. 7(v) is obtained from the intermediate fabrication step shown in FIG. A cross-sectional schematic view of the intermediate structure; FIG. 7(vi) is a schematic cross-sectional view of the intermediate structure obtained by the intermediate fabrication step shown in FIG. 7; and FIG. 7(vii) is a cross-sectional view of the intermediate structure obtained by the intermediate fabrication step shown in FIG. Cross-sectional schematic view; Figure 7 (viii) is a schematic cross-sectional view of the intermediate structure obtained by the intermediate fabrication step shown in Figure 7; Figure 8 is a schematic cross-sectional view of a variation of the freestanding film shown in Figure 6; Figure 9 is a variant of Figure 8 A flow chart of a process for producing a free-standing film; FIG. 9(i) is a schematic cross-sectional view of the intermediate structure produced by the intermediate production step shown in FIG. 9; and FIG. 9(ii) is a middle portion of the intermediate production step shown in FIG. A cross-sectional view of the structure; FIG. 9(iii) is a cross-sectional view of the intermediate structure produced in accordance with the intermediate fabrication step shown in FIG. 9; and FIG. 9(iv) is a cross-section of the intermediate structure produced in the intermediate fabrication step shown in FIG. Figure 9 (v) is a schematic cross-sectional view of the intermediate structure made according to the intermediate fabrication step shown in Figure 9; Figure 9 (vi) is a schematic cross-sectional view of the intermediate structure produced according to the intermediate fabrication step shown in Figure 9; Figure 10 A process flow diagram for constructing a substantially symmetrical structure by adding a via layer and a functional layer on both sides of a freestanding film structure or other internal substructure; FIG. 10(i) is an intermediate structure fabricated by the steps shown in FIG. Schematic diagram; Figure 10 (ii) shows the steps shown in Figure 10. Schematic diagram of the fabricated intermediate structure; Figure 10 (iii) is an illustration of the intermediate structure fabricated using the steps shown in Figure 10. Figure 10 (iv) is a schematic view of an intermediate structure fabricated using the steps shown in Figure 10; Figure 10 (v) is a schematic view of the intermediate structure fabricated using the steps shown in Figure 10; Figure 10 (vi) is taken as Figure 10 (vii) is a schematic view of an intermediate structure fabricated using the steps shown in Figure 10; Figure 10 (viii) is an intermediate structure fabricated using the steps shown in Figure 10. Figure 10 (ix) is a schematic view of an intermediate structure fabricated using the steps shown in Figure 10; Figure 10 (x) is a schematic view of the intermediate structure fabricated using the steps shown in Figure 10; Figure 10 (xi) is taken as FIG. 11 is a schematic view showing the preparation of the structure shown in FIG. 10; FIG. 11 is a schematic view showing the structure of the structure shown in FIG. 10; FIG. 11(i) is a schematic view showing the intermediate structure produced by the step shown in FIG. (ii) is a schematic view of an intermediate structure fabricated using the steps shown in FIG. 11; FIG. 11(iii) is a schematic view of the intermediate structure fabricated using the steps shown in FIG. 11; and FIG. 11(iv) is produced using the steps shown in FIG. Schematic diagram of the intermediate structure; FIG. 11(v) is an illustration of the intermediate structure fabricated using the steps shown in FIG. FIG. 11(vi) is a schematic view of the intermediate structure fabricated by the steps shown in FIG. 11; FIG. 11(vii) is a schematic view of the intermediate structure fabricated by the step shown in FIG. 11; FIG. 11(viii) is the use of FIG. A schematic view of the intermediate structure produced by the step; FIG. 11 (ix) is a schematic view of the intermediate structure fabricated by the steps shown in FIG. Figure 11 (x) is a schematic view of the intermediate structure fabricated using the steps shown in Figure 11; Figure 12 is a block metal layer formed internally by applying the steps shown in Figure 10 to the generally deformed film of Figure 8. A schematic cross-sectional view of a "2-0-2" symmetric coreless support structure; FIG. 13 is a flow chart of the preparation of the "2-0-2" structure shown in FIG. 12; and FIG. 13(i) is a corresponding step shown in FIG. Schematic diagram of the fabricated intermediate structure; Fig. 13(ii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 13; Fig. 13(iii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 13; Fig. 13(iv) Schematic diagram of the intermediate structure made for the corresponding steps shown in FIG. 13; FIG. 13(v) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 13; FIG. 13(vi) is the intermediate structure of the corresponding step shown in FIG. Figure 13 (vii) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (viii) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (ix) is Figure 13 A schematic diagram of the intermediate structure produced by the corresponding steps; FIG. 13(x) is the middle of the corresponding step shown in FIG. Figure 13 (xi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (xii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 13; Figure 13 (xiii) is Figure 13 A schematic view of the intermediate structure produced by the corresponding steps; FIG. 13 (xiv) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 13; FIG. 13 (xv) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 13(xvi) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in FIG. 13; Figure 13 (xvii) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (xviii) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (xix) is the corresponding step shown in Figure 13. Schematic diagram of the intermediate structure produced; FIG. 13(xx) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in FIG. 13; FIG. 13 (xxi) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in FIG. 13; FIG. 13 (xxii) Schematic diagram of the intermediate structure produced for the corresponding steps shown in FIG. 13; FIG. 13 (xxiii) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 13; FIG. 13 (xxiv) is the intermediate structure of the corresponding step shown in FIG. Figure 13 (xxv) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (xxvi) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (xxvii) is shown in Figure 13. Schematic diagram of the intermediate structure produced by the corresponding steps; FIG. 14 is a symmetrical coreless support structure of the barrier metal layer formed by applying the process shown in FIG. 10 to the film shown in FIG. Cross-sectional schematic view; Figure 14a is the structure shown in Figure 14 Preparation of a flowchart; Figure 15 is established as shown in FIG. 6 a schematic view of the internal support structure of the odd-numbered sub-layer having a through hole on the insulating film; FIG. 15a is a transition diagram film Ia shown in FIG. 6 to 15 odd internal layer structure of FIG. Figure 15 (i) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 15a; Figure 15 (ii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 15a; Figure 15 (iii) is a diagram 15a is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 15; FIG. 15 (iv) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 15a; FIG. 15 (v) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 15a; Figure 15 (vi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 15a; Figure 15 (vii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 15a; Figure 15 (viii) is the corresponding step shown in Figure 15a Schematic diagram of the fabricated intermediate structure; Fig. 15(ix) is a schematic view of the intermediate structure made by the corresponding steps shown in Fig. 15a; Fig. 15(x) is a schematic view of the intermediate structure produced by the corresponding step shown in Fig. 15a; Fig. 15(xi) Schematic diagram of the intermediate structure made for the corresponding steps shown in Fig. 15a; Fig. 15 (xii) is a schematic view of the intermediate structure made by the corresponding steps shown in Fig. 15a; Fig. 15 (xiii) is the intermediate structure made by the corresponding step shown in Fig. 15a Schematic; Figure 15 (xiv) is the corresponding step shown in Figure 15a Schematic diagram of the intermediate structure; Figure 15 (xv) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 15a; Figure 15 (xvi) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 15a; Figure 15 (xvii) A schematic diagram of an intermediate structure made for the corresponding steps shown in Figure 15a; 16 is a schematic diagram of a 2-1-2 structure constructed on the internal substructure shown in FIG. 15; FIG. 17 is a schematic diagram of a 3-1-3 structure constructed on the internal substructure shown in FIG. 15; FIG. 18 is a schematic diagram showing the preparation of the odd-numbered layered inner support substructure on the through hole in the insulating film shown in FIG. 8; FIG. 18a is a flow chart for preparing the film Ib shown in FIG. 6 into the odd inner layer substructure shown in FIG. 18; (i) Schematic diagram of the intermediate structure made for the corresponding steps shown in Fig. 18a; Fig. 18(ii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 18a; Fig. 18(iii) is made for the corresponding steps shown in Fig. 18a Schematic diagram of the intermediate structure; Fig. 18(iv) is a schematic view of the intermediate structure made by the corresponding steps shown in Fig. 18a; Fig. 18(v) is a schematic view of the intermediate structure produced by the corresponding step shown in Fig. 18a; Fig. 18(vi) is a diagram 18a is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 18; FIG. 18(vii) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 18a; and FIG. 18(viii) is a schematic view of the intermediate structure produced by the corresponding step shown in FIG. 18a; Figure 18 (ix) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 18a; 18(x) is a schematic view of the intermediate structure made by the corresponding steps shown in FIG. 18a; FIG. 18(xi) is a schematic view of the intermediate structure made by the corresponding steps shown in FIG. 18a; FIG. 18(xii) is the corresponding step shown in FIG. 18a. Schematic diagram of the intermediate structure; Figure 18 (xiii) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 18a; Figure 18 (xiv) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 18a; Figure 18 (xv) is the corresponding step shown in Figure 18a Schematic diagram of the fabricated intermediate structure; Fig. 18(xvi) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 18a; Fig. 18(xvii) is a schematic view of the intermediate structure produced by the corresponding step shown in Fig. 18a; Figure 18 is a schematic view of the structure of the internal substructure shown in Figure 18; Figure 20 is a schematic view of the 3-3-1 structure of the internal substructure shown in Figure 18; Figure 21 is provided in the insulating film shown in Figure 6. Schematic diagram of the semi-symmetric internal structure "-2-" of the two functional layers on each side of the through hole; FIG. 21a is a flow chart for preparing the film shown in FIG. 6 into the semi-symmetric internal structure shown in FIG. 21; 21b(i) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 21a; FIG. 21b(ii) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 21a; and FIG. 21b(iii) is the corresponding step shown in FIG. 21a. Schematic diagram of the intermediate structure; Fig. 21b (iv) is the intermediate structure made by the corresponding steps shown in Fig. 21a Figure 21b (v) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (vi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (vii) is Figure 21a Schematic representation of the intermediate structure produced by the corresponding steps Figure 21b (viii) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (ix) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (x) is shown in Figure 21a Schematic diagram of the intermediate structure produced by the corresponding steps; Fig. 21b (xi) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 21a; Fig. 21b (xii) is a schematic view of the intermediate structure produced by the corresponding step shown in Fig. 21a; Fig. 21b ( Xiii) Schematic diagram of the intermediate structure made for the corresponding steps shown in Fig. 21a; Fig. 21b (xiv) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 21a; Fig. 21b (xv) is the middle of the corresponding step shown in Fig. 21a Figure 21b (xvi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (xvii) is a schematic view of the intermediate structure made by the corresponding step shown in Figure 21a; Figure 21b (xviii) is Figure 21a A schematic view of the intermediate structure produced by the corresponding steps; FIG. 21b (xix) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 21a; Figure 21b (xx) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (xxi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (xxii) is the corresponding step shown in Figure 21a Schematic diagram of the fabricated intermediate structure; Fig. 21b (xxiii) is a schematic view of the intermediate structure made by the corresponding steps shown in Fig. 21a; Fig. 21b (xxiv) is a schematic view of the intermediate structure made by the corresponding step shown in Fig. 21a; Fig. 21b (xxv) Schematic diagram of the intermediate structure made for the corresponding steps shown in Fig. 21a; Fig. 21b (xxvi) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 21a; Fig. 21b (xxvii) is the intermediate structure of the corresponding step shown in Fig. 21a Figure 21b (xxviii) is a schematic view of the intermediate structure made in the corresponding step shown in Figure 21a; Figure 22 is a line-plated film shown in Figure 8 corresponding to the deformation of the semi-symmetrical internal structure "-2-" shown in Figure 21 A schematic diagram of a semi-symmetric internal structure constructed as shown in FIG. 22; FIG. 22a is a flow chart showing the preparation of the semi-symmetric internal structure shown in FIG. Figure 22b (i) is a schematic view of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (ii) is a schematic view of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (iii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a Figure 22b (iv) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (v) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (vi) is the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (vii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (viii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (ix) is the middle of the corresponding step of Figure 22a Figure 22b (x) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xi) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xii) is made by the corresponding steps of Figure 22a Figure 22b (xiii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xiv) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xv) is Figure 22b (xvi) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xvii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xviii) FIG. 22b(xix) is a schematic diagram of an intermediate structure prepared by using the corresponding steps of FIG. 22a; FIG. 22b(xx) is a schematic diagram of an intermediate structure fabricated by using the corresponding steps of FIG. 22a; Figure 22b (xxi) is a schematic diagram of the intermediate structure fabricated by the corresponding steps of Figure 22a; Figure 22b (xxii) is a schematic diagram of the intermediate structure fabricated by the corresponding steps of Figure 22a; Figure 22b (xxiii) is a schematic diagram of the intermediate structure fabricated by the corresponding steps of Figure 22a Figure 22b (xxiv) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxv) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxvi) is the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxvii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxviii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxix) is the middle of the corresponding step of Figure 22a Figure 22b (xxx) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxxi) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxxii) is made by the corresponding steps of Figure 22a Schematic diagram of the intermediate structure; Fig. 22b (xxxiii) is a schematic diagram of the intermediate structure made by the corresponding steps of Fig. 22a; Fig. 22b (xxxiv) is the intermediate junction made by the corresponding steps of Fig. 22a Schematic; Fig 22b (xxxv) for the corresponding steps of FIG. 22a produced using an intermediate structural diagram; Figure 22b (xxxvi) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxxvii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxxviii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a Figure 23 is a cross-section of a "1-2-1" semi-symmetric support structure similar to Figure 5a, which is not truly symmetrical, which is slightly symmetrical to the structure shown in Figure 5, for the structure of Figure 5a. FIG. 24 is a schematic cross-sectional view of the "2-2-2" semi-symmetric support structure similar to FIG. 5a, which is not completely symmetrical, by adding an outer layer to the structure shown in FIG. 21, slightly changing the structure of FIG. 5a. Figure 25 is a schematic cross-sectional view of a "1-2-1" semi-symmetric support structure similar to "2-0-2" shown in Figure 12, which slightly changes the structure of Figure 12, but shows the fabrication process The barrier metal layer of the first stage of the circuit plating is still located at different positions in the structure, which also reflects the asymmetry of the structure; FIG. 26 is similar to "3-0-3" of FIG. 2-2" schematic view of a cross-section of a semi-symmetrical support structure, but showing the production process A barrier metal layer pattern plating stage is still located at different positions in the structure, which also reflects the asymmetry of the structure.

In all cross-sectional schematics, the same material uses the same shading, from The oblique line from the top left to the bottom right indicates copper. Conversely, the hatching from the top right to the bottom left indicates the barrier metal, the spotted shadow indicates the attached metal, the dot indicates the insulating material, and the dense straight shadow indicates the solder mask. The solid black line indicates the terminal material, and the shaded portion indicated by the vertical line formed by the short extension line represents the photoresist. Similarly, the same digits in different combinations and structures represent the same layers.

It should be understood that in particular embodiments, the terminal metal, the attachment metal, and the barrier metal may, but need not all, use different materials. However, copper cannot be used for all three materials. How to choose the right metal material will be described in detail below.

Claims (36)

A manufacturing method of a multi-layer coreless support structure, characterized in that the manufacturing method comprises the following stages: I. Making a polymerized film containing conductive vias surrounded by an insulating material on a sacrificial carrier, comprising the following sub-steps: (iv) preparing a copper via hole by plating on a sacrificial carrier by using a photoresist pattern; (v) stripping the photoresist layer leaving the upright copper vias; and (vi) laminating a layer of insulating material over the copper vias, thereby forming a multilayer brazed insulating matrix film; and II. The film is peeled from the sacrificial carrier to form a free-standing layered array. The method for fabricating a multi-layer coreless support structure according to the above item 1, wherein the stage I further comprises a starting sub-step: (i) plating a barrier metal layer on the sacrificial carrier; (ii) adding a seed layer on the barrier metal layer; (iii) adding a photoresist layer on the seed layer, performing exposure and development to form the photoresist pattern; and wiring the copper through the photoresist pattern The hole is the graphic as described. For example, the method for manufacturing the multi-layer coreless support structure described in the first item is The feature is that the phase I comprises a starting sub-step: (i) directly adding a photoresist layer on the sacrificial carrier, exposing, developing, forming the photoresist pattern; (ii) in the formed photoresist pattern The line is plated with a barrier metal layer; the lined copper via is over the barrier metal of the line plating. The method of fabricating a multilayer coreless support structure according to the above item 1, wherein the film comprises an array of copper via holes in the insulating material. A method of fabricating a multilayer coreless support structure, characterized in that the method comprises at least the following stages: I-forming a film comprising a conductive via surrounded by an insulating material on a sacrificial carrier; II- peeling said surface from said sacrificial carrier Membrane, forming a free-standing layered array; V-Thinning, Planarizing stage, which is performed on a separate layered array; VI-Assembled (UP) stage, which is in a separate layer After the array is thinned and flattened, the independent layered array is layered to form a functional layer and/or a via layer; VII-terminal stage, which is a terminal for making a multilayer coreless support structure; The through hole is made of copper made of electroplating technology selected from electroplating or electroless plating. Into. The method for fabricating a multilayer coreless support structure according to claim 5, characterized in that the polymer is contained in a conductive via surrounded by an insulating material. The method of fabricating a multi-layer coreless support structure according to claim 5, wherein the stage I comprises the substeps of: (i) plating a barrier metal layer on the sacrificial carrier; (ii) Adding a copper seed layer on the barrier metal layer; (iii) adding a photoresist layer on the copper seed layer, performing exposure and development to form a photoresist pattern; (iv) plating a copper via hole in the photoresist pattern; (v) stripping the photoresist layer leaving an upright copper via; (vi) stacking an insulating material over the copper via; stage II includes sub-steps: (vii) removing the sacrificial carrier; (viii) removing the barrier metal The layer, the electronic substrate thus formed, comprises a copper structure in an insulating matrix. The method for fabricating a multi-layer coreless support structure according to claim 7, wherein the barrier metal layer has at least one of the following features: (a) the barrier metal layer is selected from the group consisting of germanium, tungsten, and chromium. , titanium, titanium and tungsten combination, Titanium-niobium combination, nickel, gold, nickel post-gold layer, gold layer post-nickel layer, tin, lead, lead layer post-tin layer, tin-lead alloy, tin-silver alloy, the barrier metal layer is prepared by physical vapor deposition process; (b) the barrier metal layer is selected from the group consisting of nickel, gold, nickel back gold layer, gold layer back nickel layer, tin, lead, lead layer back tin layer, tin-lead alloy, tin-silver alloy, and the barrier metal layer passes Prepared by electroplating or electroless plating; (c) the barrier metal layer has a thickness of 0.1 micron to 5 microns. The method for fabricating a multi-layer coreless support structure according to claim 7, wherein the method further comprises a stage III, adding a metal functional layer and an additional via layer to form an internal substructure, the inner sub In the structure, the central metal functional layer film is surrounded by the via layer, and the assembled electronic substrate has an odd number of metal functional layers. The method for fabricating a multi-layer coreless support structure according to claim 9 is characterized in that the step III comprises a sub-step: (a) adding a photoresist layer on the copper seed layer for exposure and development, Forming a functional pattern; (b) plating a copper functional layer in the functional pattern; (c) stripping the photoresist layer; (d) adding a second photoresist layer, exposing, developing, forming a via pattern; (e) line plating in the via pattern to obtain copper vias; (f) stripping the second photoresist layer; (g) etching away the copper seed layer; (h) laminating on the exposed copper via and the copper functional layer A layer of insulating material. The method for fabricating a multi-layer coreless support structure according to claim 9, further comprising a stage IV, adding an additional internal functional layer and a subsequent internal via layer to form an internal substructure, the internal sub The structure includes a central via layer surrounded by a functional layer, whereby the assembled electronic substrate has an even number of metallic functional layers. The method of fabricating a multi-layer coreless support structure according to claim 11, wherein the step IV of adding the additional internal functional layer and the subsequent internal via layer comprises the substeps: (i) the step ( The layered insulating material layer in h) is thinned and flattened to expose the outer surface of the through hole formed in the step (e); (j) the outer surface exposed by the copper through hole and the surrounding insulating material are added and adhered a metal layer; (k) adding a copper seed layer on the adhesion metal layer; (1) adding a photoresist layer on the copper seed layer, performing exposure and development to form a second functional pattern; (m) electroplating the copper functional layer in the second functional pattern; (n) stripping the photoresist from the second functional layer; (o) adding a photoresist layer, exposing and developing to form a third via pattern; p) plating copper in the third via pattern to form a third copper via layer; (q) stripping the third photoresist layer; (r) etching away the copper seed layer and the attached metal layer; (s) insulating the stack Material layer. The method for fabricating a multilayer coreless support structure according to claim 11, wherein the adhesion metal is selected from the group consisting of titanium, chromium and nickel chromium. The method for fabricating a multi-layer coreless support structure according to claim 5, wherein the phase I comprises a sub-step: (i) directly adding a photoresist layer on the sacrificial carrier, exposing, developing, forming a photoresist pattern; (ii) a line plating barrier metal in the formed photoresist pattern; (iii) a copper plating via hole on the line plating barrier metal; (iv) stripping the photoresist layer to expose the copper via hole (v) stacking the insulating material on the exposed copper vias; stage II includes sub-steps: (vi) removing the sacrificial carrier; The electronic substrate thus obtained contains a copper structure in an insulating matrix containing a barrier metal layer. The method for fabricating a multi-layer coreless support structure according to claim 14, wherein the barrier metal layer has the following characteristics: (a) the barrier metal layer is selected from the group consisting of nickel, gold, and nickel. After the gold layer, nickel layer, tin, lead, lead layer, tin layer, tin-lead alloy, tin-silver alloy, barrier metal layer is prepared by electroless plating, electroplating or a combination of the two; (b) the thickness of the barrier metal layer is 0.1 Micron to 5 microns. The method for fabricating a multi-layer coreless support structure according to claim 14, further comprising a stage III, adding a first metal functional layer and a second via layer to form an internal substructure, the internal substructure A central metal functional layer film surrounded by a via layer is included, whereby the assembled electronic substrate has an odd number of metal functional layers. The method for fabricating a multi-layer coreless support structure according to claim 16, wherein the adding the first metal functional layer and the second via layer to form a central metal function including the via layer Stage III of the inner substructure of the layer comprises the step of: (vii) adding an adhesion metal layer to the exposed surface in step (vi), The exposed surface includes an end of a copper via hole covered with an insulating material covered with a barrier metal layer; (viii) adding a copper seed layer on the adhesion metal layer; (ix) adding a first functional photoresist layer for exposure And developing to obtain a functional pattern; (x) wiring a copper functional layer in the functional pattern; (xi) stripping the first functional photoresist layer; (xii) adding a second photoresist via layer for exposure and development , to obtain a second through hole pattern. (xiii) electroplating copper into the second via pattern to obtain a second copper via layer; (xiv) stripping the second photoresist via layer; (xv) etching away the copper seed layer; (xvi) removing the adhesion a metal layer; (xvii) stacking an insulating material on the exposed second via layer. The method for fabricating a multi-layer coreless support structure according to claim 17, wherein the adhesion metal is selected from the group consisting of titanium, chromium and nickel chromium. The method for fabricating a multi-layer coreless support structure according to claim 16, wherein the method further comprises a stage IV, adding a second functional layer and The three-via layer forms an internal substructure comprising two functional layers surrounding the central via layer, whereby the assembled electronic substrate has an even number of metallic functional layers. The method for fabricating a multi-layer coreless support structure according to claim 19, wherein the step IV of adding the additional functional layer and the additional via layer comprises the steps of: (xviii) thinning and leveling step (xvii) a layer of layered insulating material to expose the outer surface of the via layer in step (xiii); (xix) adding an adhesion metal layer to the exposed outer surface of the via and the surrounding insulating material; (xx) Adding a copper seed layer to the adhesion metal layer; (xxi) adding another photoresist layer on the copper seed layer, exposing and developing to form a functional pattern; (xxii) circuit plating in the functional pattern formed in the step (xxi) Into copper, forming a second copper functional layer; (xxiii) stripping the photoresist layer added in the step (xxi) from the functional layer; (xxiv) adding another photoresist layer, exposing, developing, forming a third via a pattern; (xxv) electroplating copper into the third via pattern to form a third copper via layer; (xxvi) a photoresist layer added in the stripping step (xxiv); (xxvii) etching away the copper seed layer and Attaching a metal layer; (xxviii) Stacking layers of insulating material. The method for fabricating a multilayer coreless support structure according to claim 5, wherein the insulating material is a fiber reinforced resin composite material. The method for fabricating a multi-layer coreless support structure according to claim 5, wherein the insulating material layer comprises a resin selected from the group consisting of thermoplastic resin, thermosetting polymer resin, thermoplastic resin and thermosetting property. A mixture of polymeric resins. The method for fabricating a multi-layer coreless support structure according to claim 22, wherein the insulating material further comprises an inorganic particle filler, the insulating material having at least one of the following features: (a) inorganic The particulate filler comprises ceramic or glass particles; (b) the particle size is on the order of microns; (c) the filler weight percentage is from 15% to 30%. The method for fabricating a multi-layer coreless support structure according to claim 22, wherein the insulating material is a fiber matrix composite material, further comprising an organic fiber selected from the group consisting of an organic fiber and a twill weave or a weaving method. A glass fiber arranged as a chopped fiber or a continuous fiber. A method of fabricating a multilayer coreless support structure according to claim 23, wherein the insulating material layer is a prepreg comprising a fiber mat pre-impregnated with a partially cured polymeric resin. The method for fabricating a multi-layer coreless support structure according to claim 5, characterized in that the layered cylindrical via structure is peeled off from the sacrificial carrier to form a phase II of the free-standing layered array, including etching using The process of removing the sacrificial carrier. The method for fabricating a multi-layer coreless support structure according to claim 5, characterized in that the stage of thinning and flattening the layer of insulating material to expose the outer surface of the underlying through hole comprises one selected from the following technologies: Grinding, chemical mechanical polishing, dry etching, and multi-stage processes using two or more of these processes. The method for fabricating a multi-layer coreless support structure according to claim 5, characterized in that the method further comprises an additional stage VI: adding a functional layer and a via layer on both sides of the film. The method for fabricating a multi-layer coreless support structure according to claim 5, wherein the additional stage VI comprises the steps of: (a) adding an adhesion metal layer; (b) adding a copper seed layer to the adhesion metal layer; (c) adding a first external photoresist layer on the copper seed layer, performing exposure and development to form a first external lithography for the first external functional layer a glue pattern; (d) electroplating the first outer copper functional layer in the first outer photoresist pattern; (e) stripping the first outer photoresist layer; (f) adding a second outer photoresist layer for exposure And developing to form a second outer photoresist pattern for the first outer via layer; (g) performing a line plating of the first outer copper via layer in the second outer photoresist pattern; (h) stripping the second An external photoresist layer; (i) etching away the copper seed layer and the adhesion metal layer; (j) stacking the insulating material layer on the exposed copper functional layer and the via layer; (k) thinning and leveling the insulating material layer Until the outer surface of the copper through hole is exposed. The method of fabricating a multilayer coreless support structure according to claim 29, wherein the adhesion metal is selected from the group consisting of titanium, chromium and nickel chromium. A method of fabricating a multilayer coreless support structure according to claim 29, wherein steps (a) through (k) are repeated, thereby assembling more additional outer layers. The method for fabricating a multilayer coreless support structure according to claim 5, wherein the termination stage VII comprises the steps of: (i) adding an externally attached metal layer on the outer layer of the stacked structure; (ii) Adding an external copper seed layer to the externally attached metal layer; (iii) adding an external photoresist layer, exposing and developing to form a photoresist pattern; (iv) line plating copper wires and pads in the external photoresist pattern (v) stripping off the outer photoresist layer; (vi) adding a terminal photoresist layer, exposing and developing, selectively exposing the copper pad; (vii) plating the terminal metal on the exposed copper pad The layer, the terminal metal layer can be selected from the group consisting of nickel, gold, tin, lead, silver, palladium, and combinations and alloys of the above metals; (viii) removing the terminal photoresist layer; (ix) etching away the exposed copper a seed layer and an exposed adhesion metal layer; (x) a solder mask layer is added, exposed, developed, and the copper wire is covered to expose the terminal metal layer. The method for fabricating a multi-layer coreless support structure according to claim 5, wherein the terminal stage VII of the electronic support structure comprises the steps of: (i) adding an externally attached metal layer to the outer layer of the stacked structure; (ii) adding an external copper seed layer to the external adhesion metal layer; (iii) adding an external photoresist layer, performing exposure and development to form a photoresist pattern; (iv) performing line plating in the external photoresist layer pattern Copper wires and pads; (v) stripping off the outer photoresist layer; (vi) etching away the exposed copper seed layer and the attached metal layer; (vii) adding a solder mask layer for exposure, development, and hiding the copper wires (viii) electroless plating of the termination layer on the exposed copper pad, the termination layer can be selected from the following metals: nickel, gold, tin, lead, silver, palladium, nickel-gold, tin-silver , alloys and anti-corrosive materials. The method for fabricating a multi-layer coreless support structure according to claim 5, wherein the multi-layer coreless support structure has a feature layer of an even number of layers. The method for fabricating a multi-layer coreless support structure according to claim 5, wherein the multi-layer coreless support structure has a functional layer of a single layer. The method for fabricating a multi-layer coreless support structure according to claim 5, wherein the multi-layer coreless support structure is a symmetric multi-layer coreless support structure.