JP3913632B2 - Manufacturing method of build-up multilayer printed wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a build-up multilayer printed wiring board.
[0002]
[Prior art]
A multilayer printed wiring board having a structure in which resin insulating layers and wiring patterns are alternately laminated is well known. In recent years, products in which resin insulation layers and wiring patterns are sequentially laminated one after another while maintaining electrical connection between layers through vias drilled by laser or photography, that is, build-up multilayer printed wiring boards, have become mainstream. . The structure is, for example, as shown in FIG.
[0003]
FIG. 3 is a cross-sectional view schematically showing an enlarged part of a conventional build-up multilayer printed wiring board 100. On the core material 2 ', a core wiring pattern 35, first and second buildup resin insulation layers 40 and 60 (hereinafter also simply referred to as resin insulation layers), and wiring patterns 36 and 37 are laminated. . Vias 31, 32, 33, and 34 are formed in the resin insulating layers 40 and 60, and electrical connection between the layers is achieved through them. The wiring pattern 37 formed in the uppermost layer of the wiring patterns is covered with a solder resist layer 80. The solder resist layer 80 is opened so that the conductive pads 50 and 51 for electrical connection with the electronic component are exposed. After the solder paste is printed and filled in the opening, the solder resist layer 80 is reflowed to form solder bumps. Become. Normally, a through hole penetrating the core material 2 ′ is provided (not shown).
[0004]
By the way, as the electronic components to be mounted are highly integrated, it is necessary to reduce the distance between the centers of the conductive pads 50 and 51 accordingly. Such in order to respond to such needs, conceivable is possible to reduce the distance D ₁ of the between conductive pads 50 and 51. That way, without reducing the conductive pads 50 and 51, it is possible to take a relatively large opening diameter D ₂ of the solder resist layer 80 on which the solder paste is filled, without being difficult to fill the solder paste That's it.
[0005]
[Problems to be solved by the invention]
However, reducing the interval D ₁ of the between conductive pads 50 and 51, to easily occur solder bridge, the pad - are under pressure to greatly miniaturize the wiring pattern 37 through the inter-pad.
[0006]
As another means in place of the above means, as in the conventional build-up multilayer printed wiring board 101 shown in FIG. 4, the small-diameter conductive pads 62 and 63 are employed, and the opening diameter D ₂₁ of the solder resist layer 80 is set. It can be considered to be small. According to this, although take relatively large distance D ₁₁ between the conductive pads 62 and 63, now it is faced with the need to reduce the aperture diameter D ₂₁ of the solder resist layer 80. When the aperture diameter D ₂₁ of the solder resist layer 80 is too small, can not be sufficiently filled with the solder paste on the opening, solder inside voids lead to problems such as prone. In such a state, good conduction with the electronic component cannot be compensated. However, if the solder paste is printed excessively, solder bridges are generated.
[0007]
In view of this, the present invention is able to ensure good electrical continuity with the electronic component to be mounted, and is formed with conductive pads and solder bumps so as to prevent problems such as wiring short-circuits, and build-up corresponding to high integration of electronic components. It is an object to provide a method for producing a multilayer printed wiring board.
[0008]
[Means for solving the problems and actions / effects]
In order to solve the above problems, the present invention
A build-up multilayer printed wiring board manufacturing method in which a resin insulating layer and a wiring pattern are alternately laminated on a core substrate, and a plurality of conductive pads as external connection terminals are formed. The manufacturing method includes a core material and a core wiring pattern. A step of laminating a predetermined number of resin insulation layers and wiring patterns on the core substrate so that the wiring patterns are not exposed on the substrate surface, and the insulating resin layer that is positioned closest to the surface layer side of the resin insulation layer A step of drilling a via whose bottom wiring pattern is a bottom by laser processing, a step of roughening the inner surface of the laser-processed via, and a step of forming a plating resist so as to expose the opening peripheral edge of the via And copper plating on the via to form a conductive pad that extends to the peripheral edge of the opening of the via, and a solder pad on the conductive pad by electrolytic solder plating. The flop, from the surface of the plating resist, so that the surface of the solder bumps becomes lower position, forming, and removing the plating resist and performing in this order.
[0009]
According to the electrolytic solder plating method, a solder bump having a uniform thickness can be formed. However, that alone cannot satisfy the high integration of wiring patterns. Therefore, in the method of the present invention, the uppermost layer of the build-up multilayer printed wiring board is dedicated to a conductive pad serving as a connection part of an electronic component by observing the order of the steps described above. That is, the wiring pattern is formed under the conductive pad with one resin insulating layer interposed therebetween. Therefore, there is little possibility that the solder bump bridges the wiring pattern. In addition, the plating resist for forming the solder bumps can be used simply as the plating resist for copper plating in the via.
[0010]
In a preferred embodiment, the copper plating filled in the via can be formed by an electroless copper plating method and an electrolytic copper plating method. That is, before forming the plating resist, the surface of the insulating resin layer and the inner surface of the via are roughened, and the electroless copper plating step is performed. After forming the plating resist, the conductive pad is formed by electrolytic copper plating. After removing the plating resist, the step of removing the electroless copper plating layer where the conductive pad is not formed is performed. That is, according to the semi-additive method, the inside of the via can be filled with copper plating by adjusting the plating conditions, which can be suitably used in the present invention.
[0011]
Also, in the step of drilling vias, it is desirable to drill in a positional relationship in which vias are stacked on the fill vias one layer below in order to form conductive pads. In this way, there is a margin in the space for creating the wiring pattern one layer lower than the via is offset.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is an enlarged cross-sectional view showing a main part of a build-up multilayer printed wiring board 1 according to the present invention. The build-up multilayer printed wiring board 1 is formed by alternately stacking resin insulating layers and wiring patterns on a core substrate. In the present embodiment, an example configured as a flip-chip wiring board is shown. Such a build-up multilayer printed wiring board 1 is subjected to a reflow process and is flip-chipd to provide an electronic component such as an IC chip (not shown). Is installed.
[0013]
A plate-like core material 2 composed of a heat-resistant resin plate (for example, bismaleimide-triazine resin plate) or a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin), and a predetermined pattern on both surfaces of the core material 2 The core wiring pattern 3 formed in (1) is configured as a core substrate of the build-up multilayer printed wiring board 1. Normally, a through hole penetrating the core material 2 is formed, but it is omitted in this figure. A wiring pattern (not shown) may be formed inside the core substrate.
[0014]
On the upper layer of the core wiring pattern 3, a first buildup resin insulating layer 4 is formed of an insulating organic resin material such as an epoxy resin (having ultraviolet curable or thermosetting). Furthermore, the 1st wiring pattern 5 is formed in the surface by copper plating, respectively. The core wiring pattern 3 and the first wiring pattern 5 are connected to each other through vias 21 and 22 filled with copper plating in the holes. Note that the vias 21 and 22 may be filled with conductive paste in the holes.
[0015]
Similarly, a second buildup resin insulation layer 6 is formed on the first wiring pattern layer 5 from the same material as the first buildup resin insulation layer 4. A second wiring pattern 7 is formed on the surface by copper plating. Both the first wiring pattern 5 and the second wiring pattern 7 are connected to each other by vias 19 and 20 filled with copper plating.
[0016]
As can be seen from a comparison with the conventional product of FIGS. 3 and 4, normally, the wiring pattern 7 is directly covered with a solder resist layer, and solder bumps are formed in the openings of the solder resist layer. However, in the present invention, after the uppermost wiring pattern 7 of the wiring patterns is formed, the third buildup resin insulation layer 8 is further formed of the same material as that of the first buildup resin insulation layer 4. I have to. Then, conductive pads 10 and 12 as external connection terminals are formed on the third buildup resin insulating layer 8, and solder bumps 11 and 13 are formed on the conductive pads 10 and 12, respectively. That is, the wiring pattern that crosses between the pair of adjacent conductive pads 10 and 12 and the solder resist layer that should cover the wiring pattern are not formed.
[0017]
When the structure as described above, reducing the center distance D ₃ of the conductive pads 10, 12 adjacent, i.e. the distance D ₄ between the conductive pads 10 and the conductive pad 12, having to worry about the presence of the wiring pattern It becomes possible to reduce without any loss. From another point of view, it can also be considered that a layer including only the conductive pads 10 and 12 is formed on the surface of the resin insulating layer positioned closest to the surface (resin insulating layer 8 in FIG. 1). That is, it is possible to prevent a wiring pattern from being formed in the same layer as the conductive pads 10 and 12 as external connection terminals. As a result, the main plate surface of the build-up multilayer printed wiring board 1 is constituted by the surface 8a of the third build-up resin insulating layer 8, the conductive pads 10, 12 and the solder bumps 11, 13. As described above, by forming the uppermost wiring pattern 7 and the conductive pads 10 and 12 in separate layers, it is possible to provide a margin for each dimension. The main plate surface indicates the front and back surfaces excluding the side surface of the wiring board.
[0018]
Specifically, in this embodiment, all the wiring patterns 5 and 7 (which can be considered including the core wiring pattern 3) formed by the build-up process are covered with the resin insulating layers 6 and 8. The conductive pads 10, 12 are located on the most surface side of the resin insulating layers 4, 6, 8, that is, the wiring pattern one layer below through the vias 14, 16 formed in the resin insulating layer 8. 7 is taken. In this case, even if the solder resist layer is not provided, the wiring pattern is not exposed on the surface, so that problems such as insulation degradation do not occur. The via for interlayer connection is generally located on a land formed as a part of the wiring pattern, but a landless structure may be adopted.
[0019]
The conductive pads 10, 12 in this embodiment is substantially circular, center distance D ₃ of the mutually closest is adjusted to 150μm or less. In other words, the build-up multilayer printed wiring board 1 is suitably employed as a flip chip substrate having a terminal-to-terminal distance of 150 μm or less. In this case, the diameter of the conductive pads 10 and 12, for example by adjusting the 90μm or 110μm or less, the pad - the inter-pad distance _{D 4} can be kept at least 40 [mu] m. The vias 14, 16, 19, 20, 21, and 22 are perforated in a cylindrical shape, and the diameter thereof can be about 60 μm. Further, the land that is formed immediately above the vias 19, 20, 21, and 22 and forms a part of the wiring patterns 5 and 7 can be reduced to the positioning limit at the time of via drilling.
[0020]
The conductive pads 10 and 12 are formed on the surface 8a of the resin insulating layer 8 by copper plating in the form of a plateau, and terminals of components (for example, flip chips) to be mounted on the conductive pads 10 and 12 respectively. Solder bumps 11 and 13 that are in direct contact with each other are formed by solder plating. The solder bump formation by the screen printing method is simpler than that by the plating method. However, as the distance between adjacent conductive pads becomes small as in the build-up multilayer printed wiring board 1 of this embodiment, a certain amount is formed. It becomes difficult to form a uniform print. On the other hand, since the plating method can make the plating thickness uniform by adjusting the plating conditions, it is suitable for forming fine solder bumps.
[0021]
In the above, the solder bumps 11 and 13 are formed directly on the conductive pads 10 and 12, respectively, but the present invention is not limited to this. For example, Ni plating and Au plating may be performed on the conductive pads 10 and 12, and the solder bumps 11 and 13 may be formed on the Au plating, respectively.
[0022]
Next, a manufacturing method of the build-up multilayer printed wiring board 1 shown in FIG. 1 will be described. FIG. 2 is a diagram for explaining the manufacturing process. First, the uppermost wiring pattern 7 is laminated on the core substrate by a known build-up process (step (1)). Next, the wiring pattern 7 is covered with the resin insulating layer 8 (step (2)). Through the steps so far, a predetermined number of resin insulating layers and wiring patterns are laminated so that the wiring patterns are not exposed on the substrate surface.
[0023]
Next, the wiring pattern 7 under the resin insulating layer 8 (specifically, a land that forms a part of the wiring pattern 7) is disposed on the resin insulating layer that is positioned on the most surface side, that is, the resin insulating layer 8. The bottom via 14 is drilled (step (3)). This drilling step is preferably performed by laser processing using an Nd: YAG laser, a CO ₂ laser, an excimer laser, or the like. Further, in the present embodiment, the vias 14 for forming the conductive pads 10 are perforated in such a positional relationship that they are stacked on the lower fill via 19. This is preferable because there is a margin in the space for creating the wiring pattern as much as the via is not offset. The fill via 19 cannot be replaced with a conformal via because the via 14 must be stacked thereon. It should be noted that smear remaining on the bottom of the via 14 may be removed by desmearing after completion of drilling with the laser.
[0024]
After forming the via 14, the inner surface of the via 14 is roughened together with the surface of the resin insulating layer 8 in order to form a plating layer in the via 14 by a semi-additive method (step (4)). The electroless copper plating layer 30 is thinned on the roughened surface by a known electroless plating method (process (5)), and plating is performed so that the peripheral edge of the opening of the via 14 (position where the conductive pad 10 is to be formed) is exposed. A resist 31 is formed (step (6)). A photosensitive dry film may be used for the plating resist 31 and the opening peripheral edge of the via 14 may be exposed by a photographic method.
[0025]
After the plating resist 31 is formed, the inside of the via 14 is filled with copper plating by an electrolytic copper plating method to form the conductive pad 10 (step (7)). In the present embodiment, the via 14 for connecting the conductive pad 10 to the underlying wiring pattern is a fill via filled with copper plating. However, as for the via 14, it is filled with solder plating. You can use conformal vias.
[0026]
After forming the conductive pad 10, the solder bump 11 is formed directly on the conductive pad 10 by the electrolytic solder plating method (step (8)). Regarding electrolytic solder plating, Pb—Sn—Sb solder plating or lead-free Sn—Sb solder plating can be formed using a known fluorination bath or acid bath. Then, the plating resist 31 is removed, and the electroless copper plating layer 30 in the portion where the conductive pad 10 is not formed is removed (step (9)). As described above, the build-up multilayer printed wiring board 1 shown in FIG. 1 is manufactured.
[Brief description of the drawings]
FIG. 1 is an enlarged cross-sectional view of a main part of a build-up multilayer printed wiring board according to the present invention.
2 is a view for explaining a manufacturing process of the build-up multilayer printed wiring board of FIG. 1;
FIG. 3 is a cross-sectional view showing a conventional build-up multilayer printed wiring board.
4 is a cross-sectional view similar to FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Build-up multilayer printed wiring board 2 Core material 3 Core wiring patterns 4, 6, 8 Build-up resin insulation layers 5, 7 Wiring pattern 8a Surfaces 10, 12 of build-up resin insulation layers Conductive pads 11, 13 Solder bumps 14, 16 Via 19, 19 Fill via 30 Electroless copper plating layer 31 Dry film (plating resist)

Claims (3)

A method for producing a build-up multilayer printed wiring board in which resin insulating layers and wiring patterns are alternately laminated on a core substrate, and a plurality of conductive pads as external connection terminals are formed,
A step of laminating a predetermined number of the resin insulating layer and the wiring pattern on the core substrate composed of a core material and a core wiring pattern so as not to expose the wiring pattern on the substrate surface;
A step of drilling a via which is the bottom of the wiring pattern under the resin insulation layer by laser processing, to the one located on the most surface side of the insulation resin layer;
Roughening the inner surface of the laser processed via;
Forming a plating resist in a form to expose the opening peripheral edge of the via;
Applying copper plating to the via to form the conductive pad extending to the opening periphery of the via; and
Forming a solder bump on the conductive pad by electrolytic solder plating so that the surface of the solder bump is lower than the surface of the plating resist ;
Removing the plating resist;
A method for manufacturing a build-up multilayer printed wiring board, wherein the steps are performed in this order. The copper plating filled in the via is formed by an electroless copper plating method and an electrolytic copper plating method,
Before forming the plating resist, while performing a step of roughening the inner surface of the via together with the surface of the insulating resin layer, and an electroless copper plating step,
After forming the plating resist, performing the step of forming the conductive pad by electrolytic copper plating method,
The manufacturing method of the buildup multilayer printed wiring board of Claim 1 which performs the process of removing the electroless copper plating layer of the part in which the said conductive pad is not formed after removing the said plating resist.   3. The method for manufacturing a build-up multilayer printed wiring board according to claim 1, wherein in the step of drilling the via, the via is drilled in a positional relationship in which the via is stacked on a fill via below one layer in order to form the conductive pad. .

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