JP2000100988A - Pga package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a build-up multilayer wiring board high in wiring density at low cost as a PGA package, by making the resin layer only on mounting side a one-side build-up wiring layer capable of flip mounting, and leaving the mother board side as a resin layer. SOLUTION: Resin layers 16 are stacked on both sides of the core board 10 consisting of a printed wiring board. Then, the resin layer 17 on chip mounting side is made a one-side build-up wiring layer capable of flip mounting, and the mother board side is made a build-up layer of the resin layer 16. Then, in the resin layer 16 on mother board side, a blind through hole 36 leading to the wiring of the core board 10 is made, and a pin is inserted into a through hole 36. Therefore, the blind hole 36 can be made without taking the position of the via of the one-side build-up wiring layer into consideration, and also there is no necessity of land formation, either. Moreover, the resin charge of the blind through hole 36 and the fixing can be performed at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention can be used as an IC package and an MCM (multi-chip module) for mounting a semiconductor device, and can also be used as a single-layer and multilayer circuit board for mounting electronic components. Regarding PGA package.

[0002]

2. Description of the Related Art Conventionally, as an IC package for an MPU, an alumina PGA package obtained by laminating and sintering alumina green sheets formed by wiring with a tungsten paste has been dominant.

However, in recent years, high-frequency driving of MPUs has been rapidly progressing, and the package structure has been changed to W / B (wiring board).
Type PGA packages and package materials are shifting to low-permittivity resin materials with Cu plating wiring, which is advantageous for higher frequencies. It is expected that IC packages will rapidly shift to C4 type PGA packages using resin material / Cu wiring in the future.

[0004] Under these circumstances, a build-up substrate has recently attracted attention. The build-up board forms an insulating layer on the wiring pattern of the printed wiring board, which is the core board, by screen printing, etc., forms an upper wiring layer by additive method, etc. This is a multilayer wiring board obtained by repeating this process as many times as necessary. In particular, a built-up multilayer board using a printed board as a core board, a resin material as an interlayer insulating material, and using Cu plating for wiring formation is an MP
Attention has been paid to IC packages and MCMs for mounting U and high-density mounting boards for mounting electronic components, and printed circuit board manufacturers, IC package manufacturers, semiconductor manufacturers, etc. are vigorously developing them.

Here, the manufacturing method of the build-up multilayer substrate, which has been recently developed, is further described as follows. Manufacturing methods are broadly classified into a photolithography method in which wiring is formed by plating using a photosensitive resin for an insulating layer, and a press lamination method in which a prepreg resin and a metal foil are laminated by hot pressing. Furthermore, the photolithography method is classified into a subtractive method, a semi-additive method, and a full-additive method from the difference in a wiring forming method.
A well-known example of the subtractive method is SLC of IBM, and a typical example of the full-additive method is IBSS of Ibiden. In recent years, attention has been paid to a semi-additive method which is advantageous for fine wiring.

Here, for reference, a manufacturing process of a build-up multilayer substrate by a subtractive method will be described below. (1) Form a wiring pattern on the copper foil surface of the core board (PWB-Printed Wiring Board). (2) A photosensitive resin is applied to form an interlayer insulating layer.

(3) Via holes are formed in the insulating layer by ultraviolet exposure and development. (4) The surface of the insulating layer is roughened with an oxidizing agent (desmear). (5) Electroless Cu or electrolytic Cu plating is deposited on the surface of the insulating layer.

(6) A Cu wiring pattern is formed by forming a pattern resist, developing, and Cu etching. (7) The surface of the Cu wiring is roughened by plating or etching.

(8) Steps (2) to (7) are repeated to form a desired build-up layer. (9) Apply solder resist to the outermost wiring surface, expose,
Develop to form a solder mask layer. (10) Perform electroless Ni and Au plating.

[0010] In this respect, according to the manufacturing process of the build-up multi-layer substrate by the full additive method, the electroless plating is performed on the laminated board pattern containing the catalyst with the adhesive. There are a printing method and a photo etching method for forming the resist. The manufacturing process at that time is completed by making a through hole in the laminated board with the adhesive and the catalyst, forming a plating resist, and performing electroless plating on this.

Furthermore, according to the manufacturing process of the build-up multilayer substrate by the semi-additive method, after a through-hole is formed in the laminated plate containing a catalyst with an adhesive, (1) electroless panel plating, (2) plating resist formation, A build-up multilayer board is manufactured through the steps of (3) electrolytic copper, solder plating, (4) resist stripping, and (5) etching.

As described above, a build-up multi-layer substrate can be obtained by various methods even in the related art, but at present, L / S = 50
Build-up boards having a total of 4 to 8 layers are manufactured based on design rules of about / 50 to 100/100 μm and via diameter = about 50 to 100 μm.

[0013]

[Problems to be Solved by the Invention] In the build-up multilayer board for mounting the MPU, fine wiring is required on the build-up layer on the chip mounting side of the core board (printed wiring board), and on the motherboard side on the build-up layer. No need to be. Basically, a single-sided build-up, that is, a single-sided build-up is sufficient. However, it was necessary to build up on both sides, that is, to provide a build-up layer on both sides due to the problem of substrate warpage. However, in such a method, when the via processing is performed using a laser that is inferior to a photo via in terms of speed, the number of vias to be processed is doubled in double-sided build-up, so that the processing speed and the number of steps are considerably disadvantageous.

[0014] Further, with the miniaturization of wirings, it is necessary to form vias on through holes. But,
When a through hole is formed, it is necessary to form a land on it, so a via cannot be formed at that part, which not only hinders the miniaturization of wiring, but also involves techniques such as resin filling for land formation. However, since there are many man-hours, there are problems such as an increase in cost. Here, the purpose of the present invention is
An object of the present invention is to provide a method for manufacturing a build-up multilayer substrate having a high wiring density as a PGA package at low cost.

[0015]

Means for Solving the Problems In the case where a printed wiring board is used as a core substrate and resin layers are laminated in multiple layers on both surfaces of the core substrate, the single-sided built-up capable of flip-mounting the resin layer only on the mounting side is provided. By setting the wiring layer and leaving the resin layer on the motherboard side, blind through-holes can be formed without considering the positions of vias in the single-sided build-up wiring layer. If a pin is inserted into the through hole, it is possible to simultaneously fill the resin in the blind through hole and fix the pin, thereby reducing the manufacturing cost.

Further, the present inventors have found that laser processing is possible when forming blind through holes in the resin layer on the motherboard side. When a via is formed in the build-up wiring layer on the chip mounting side, laser build-up in which molding is performed by laser processing is also possible.

Here, the present invention is directed to a core substrate composed of a single-layer or multilayer printed wiring board, a resin layer laminated in multiple layers on both surfaces thereof, and a resin layer on the chip mounting side is a single-sided build-up that can be flip-mounted. It is a wiring layer, the motherboard side is a build-up layer of a resin layer, is formed on the resin layer on the motherboard side, and a blind through hole reaching the wiring of the core substrate, and inserted into the through hole This is a PGA package characterized by having

In the present invention, the resin layer on the chip mounting side may have a via formed by laser processing. Preferably, in the case of the present invention, the resin layer on the motherboard side is composed of only the resin layer.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 9 are explanatory views of a manufacturing process of a PGA package according to the present invention. FIG.
In the figure, a wiring formation process is performed. In the drawing, for example, a wiring is formed by a Cu pattern 12 on only one surface of a core substrate 10 which is a single-layer or multilayer printed wiring board. Hereinafter, this is referred to as "Cu substrate 14" for convenience. In the illustrated example, a single-layer printed board is used as a core board.

FIG. 2 shows a resin layer forming step, and is a schematic view of a cross section in which a resin layer 16 is formed on both sides of the Cu substrate 14 formed by providing a Cu pattern 12 on one side of a core substrate 10. . In the present invention, the resin layer 16 is preferably made of a highly reliable epoxy or polyimide photosensitive resin or thermosetting resin.

Further, the interface between the Cu pattern 12 and the resin layer 16 needs to be devised in order to obtain an adhesive strength. As a specific method therefor, there is a method of roughening the surface of the Cu substrate or forming a buffer metal at the interface. As in this example,
When Cu is used for forming the wiring, there are a method of securing the strength by roughening the surface by needle plating and etching, and a method of securing the adhesive strength by using a Cr-Zn alloy or the like as a buffer metal.

FIG. 3 shows a via forming step, and is a schematic view of a cross section in which a via 20 is formed in a resin layer 16 on one side. If the resin layer 16 provided in the step of FIG. 2 is a photosensitive resin, vias can be formed by photo via technology. In the case of this photo via, the aspect of the via diameter and the via depth is about 1 and the diameter is 25 μm.
Processing up to m is possible. Via formation can also be performed using a laser. When a laser is used, processing up to a via diameter of 10 μm is possible. In addition, via formation may be performed using a drill, plasma, or the like. The resin layer on the opposite side is not particularly processed and is left as it is.

FIG. 4 shows a further wiring forming step, and is an explanatory view showing the plating coating 22 in the via 20 and the wiring 24 formed on the resin layer 16. In the present invention, wiring is formed only on one side.

This is an explanatory diagram in the case of using the semi-additive method, but the method of manufacturing the build-up wiring resin layer in the present invention is not limited. As the wiring forming method at this time, in addition to the above-described semi-additive method, a full additive method, a subtractive method, and the like can be given.

In particular, in the case of the present invention, since a single-sided wiring forming method is used, a conventional semiconductor thin film forming technique (sputtering method,
Vapor deposition, CVD, jet plating, ashing, etc.) can be used easily, and fine wiring can be formed. This is the formation of one layer. In the case of the wiring of the outermost layer, a buffer metal (Ni, Pd, Au, etc.) film may be formed on the wiring surface.

FIG. 5 shows a step of forming a resin layer on both sides. The resin layer 26 is formed again on both sides of the substrate on which wiring is formed on one side as shown in FIG. Thereafter, as shown in FIG. 3 again, a via 28 is formed only on one side, and the printed wiring board is formed.
30. See FIG. 6 below.

In the case of further multi-layering, the steps of FIGS. 4 and 5 are repeated a required number of times. FIG. 6 shows a process of forming a blind through-hole. From the pin bonding surface side (motherboard side) of the single-layer or multilayer printed wiring board 30 obtained in the process of forming the resin layer 26 of FIG. A through hole leading to the back side of the pad on the chip mounting side, that is, the wiring of the Cu pattern 12, that is, a blind through hole 36 is formed. In the case of the present invention, since no wiring is provided on the resin layer on the motherboard side, no consideration is required for this, and the position can be freely determined as needed.

In order to increase the solder wettability and the pin strength of the pin joint, the inside of the through hole 36 may be covered with metal by plating or the like. FIG. 7 shows a pin bonding step. In the illustrated example, the Cu pattern 12 which is the wiring of the core substrate 10 is shown.
The pin 40 is inserted into the through hole 36 that has reached the above, and the pin joint 38 at the tip thereof is joined to the Cu pattern 12 using a high-temperature solder or the like.

FIG. 8 shows a pin reinforcing step, in which a reinforcing plate is bonded to the pin bonding side or the pin is reinforced by sealing the mold resin 42. In the illustrated example, the pin is reinforced by enclosing the mold resin 42 in the through hole 36. As a result, a semiconductor mounting substrate capable of fine wiring can be obtained.

FIG. 9 shows a bump forming step on the chip mounting side. A bump 44 is provided on the uppermost layer via to obtain a PGA package which can be lip mounted.

Next, FIGS. 10 to 18 are explanatory views of another embodiment according to the present invention. As is clear from FIGS. 10 to 18, this example shows a case in which a core substrate on which wiring is formed in multiple layers is used. Except for this point, formation of a build-up resin layer and formation of a through hole The same applies to the case where the single-layer wiring board is used, and only the differences will be described below.

FIG. 10 corresponds to FIG. 1 described above and shows a core substrate made of a multilayer printed wiring board. In FIG. 10, a core substrate which is a multilayer printed wiring board is shown.
Numeral 100 is provided with wiring by Cu pattern 112 on both sides.
The Cu patterns 112 on the upper and lower surfaces are connected by through-holes 113 similarly plated with metal. Hereinafter, the substrate thus obtained is referred to as “Cu substrate 114” for convenience.
Say

FIG. 11 shows a resin layer forming step corresponding to the step of FIG.
FIG. 4 is a schematic view of a cross section in which is formed. In this case, the resin layer 11
At the same time as the formation of 6, the filling of the through holes 113 is performed. Also in this case, the interface between the Cu pattern 112 and the resin layer 116 requires the same contrivance as in FIG.

FIG. 12 shows a via forming step, and is a schematic diagram of a cross section when a via 120 is formed in one side of the resin layer 116. This corresponds to FIG. 3, and the via formation and the like may be performed according to the case of FIG.

FIG. 13 shows a further wiring forming step, and is an explanatory view showing the state of the plating coating 122 in the via 120 and the wiring 124 formed on the resin layer 116. This is Figure 4
Is equivalent to This is the formation of one layer. For the outermost layer wiring, buffer metal (Ni, Pd, Au, etc.) on the wiring surface
A film may be formed.

FIG. 14 shows a step of forming a resin layer on both surfaces. A resin layer 126 is formed again on both surfaces of the core substrate 100 on which wiring is formed on one surface as shown in FIG. Thereafter, in the same manner as shown in FIG.
To form a printed wiring board 130. See FIG.

In the case of multi-layering, the steps of FIGS. 13 and 14 are repeated a required number of times. FIG. 15 shows a process of forming a blind through hole in the resin layer. The core printed circuit board 130 obtained from the resin layer forming process up to FIG. A through-hole, ie, a through-hole 136 is formed up to the back side of the pad on the chip mounting side of 100, that is, to the Cu pattern 112. In the illustrated example, the through-hole is formed in a region where no via is provided. At this time, the via on the wiring resin layer side may come over the through-hole.

The inside of the through hole 136 may be metal-coated with plating or the like in order to increase the solder wettability and the pin strength of the pin joint. FIG. 16 shows a pin bonding process. In the illustrated example, a pin 140 is inserted into the through hole 136 that has reached the Cu pattern 112, and the pin bonding portion 138 at the tip is formed using a high-temperature solder or the like. Join to 112.

FIG. 17 shows a pin reinforcing step, in which a reinforcing plate is bonded to the pin bonding side or the pin is reinforced by sealing the mold resin 42. In the illustrated example, the pin is reinforced by enclosing the mold resin 42 in the through hole 36. As a result, a semiconductor mounting substrate capable of fine wiring can be obtained.

FIG. 18 shows a bump forming step on the chip mounting side. By providing the bump 144 on the via on the chip mounting side, a PGA package that can be flip-mounted is obtained.

[0041]

As described above, according to the present invention, the printed wiring board is used as the core substrate, and the resin layers on both sides thereof are laminated in multiple layers, and the resin layer only on the chip mounting side can be flip-mounted. Since it is a single-sided build-up wiring layer and the motherboard side is not provided with wiring, it is preferably a resin-layer only build-up layer, the structure of the PGA package is substantially single-sided built-up,
Therefore, it is possible to supply a substrate in which vias of the build-up wiring layer and blind through holes provided in the resin layer on the motherboard side can be freely arranged. Further, since the pins are provided only on the motherboard side, the pins can be bonded to the entire surface, and further, on the chip side, wiring can be formed irrespective of the positions of the pins, and the wiring density can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory view showing a step of forming a wiring on a core substrate.

FIG. 2 is a schematic explanatory view showing a resin layer forming step.

FIG. 3 is a schematic explanatory view showing a via forming step.

FIG. 4 is a schematic explanatory view showing a wiring forming step.

FIG. 5 is a schematic explanatory view showing a resin layer forming step of forming a resin layer on both surfaces.

FIG. 6 is a schematic explanatory view showing a step of forming a blind through hole.

FIG. 7 is a schematic explanatory view showing a pin joining step.

FIG. 8 is a schematic explanatory view showing a pin reinforcing step.

FIG. 9 is a schematic explanatory view showing a bump forming step on the chip bonding side.

FIG. 10 is a schematic explanatory view of a step of forming wiring on a core substrate corresponding to FIG. 1 in another embodiment.

11 is a schematic explanatory view of a resin layer forming step corresponding to FIG. 2.

FIG. 12 is a schematic explanatory view of a via forming step corresponding to FIG. 3;

FIG. 13 is a schematic explanatory view of a wiring forming step corresponding to FIG. 4;

14 is a schematic explanatory diagram of a resin layer forming step of forming a resin layer on both surfaces corresponding to FIG. 5;

FIG. 15 is a schematic explanatory view of a step of forming a blind through hole corresponding to FIG. 6;

FIG. 16 is a schematic explanatory view of a pin bonding step corresponding to FIG. 7;

FIG. 17 is a schematic explanatory view of a pin reinforcing step corresponding to FIG. 8;

18 is a schematic explanatory view of a bump forming step on the chip bonding side corresponding to FIG. 9;

[Explanation of symbols]

10: Core substrate 12: Cu pattern 14: C
u board 16: resin layer 20: via 22:
Plating coating 24: Wiring 28: Via 36:
Through hole 38: Pin joint 40: Pin 42
:: Old resin

Claims (2)

[Claims] 1. A core substrate comprising a single-layer or multilayer printed wiring board, resin layers laminated on both surfaces of the core substrate,
The resin layer on the chip mounting side is a single-sided build-up wiring layer that can be flip-mounted, the motherboard side is a build-up layer of the resin layer, formed on the resin layer on the motherboard side, and connected to the wiring of the core substrate. A PGA package comprising blind through holes and pins inserted in the through holes. 2. The PGA package according to claim 1, wherein said resin layer on the chip mounting side has a via formed by laser processing.