JP2006041029A - Wiring substrate, manufacturing method thereof, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring substrate which is provided with fine sets of wiring and is not accompanied by a problem resulting from use of photoresist and dry film resist. <P>SOLUTION: In the wiring substrate provided with a substrate and an exposed wiring pattern layer formed on the substrate, the wiring pattern is formed by depositing the precursor of the wiring pattern to a groove formed in the predetermined depth at the predetermined position of the substrate, and thereafter removing an excessive part of the precursor from the front surface side of the substrate. Moreover, the wiring substrate has a flat surface. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wiring board, and more specifically, a wiring board having a fine wiring on the surface and a flat wiring layer surface, and a semi-additive method that has been conventionally used in general. The present invention relates to a method of manufacturing a wiring board easily and with high yield. The present invention also relates to an electronic device such as a semiconductor device using the wiring board of the present invention.

  As is well known, a wiring board is formed by forming a wiring pattern (electric circuit) with a metal that is a good electrical conductor (hereinafter referred to as “conductor metal”) on an electrically insulating substrate, and is a semiconductor element (eg, LSI). It is used to mount and support electronic parts such as.

  Currently, the wiring board is formed by, for example, an additive method or a semi-additive method. For example, the semi-additive method is disclosed in Patent Documents 1 and 2. With reference to Patent Document 2, as shown in order in FIG. 11, a method of manufacturing a printed wiring board by a semi-additive method is disclosed. According to this method, first, as shown in step (A), a base metal layer 102 is formed on an insulating substrate 101, and then a mask pattern 103 for forming a wiring pattern by plating is formed from a photoresist. Next, as shown in step (B), a plating pattern 104 is formed by electrolytic plating in the groove portion where the base metal layer 102 other than the mask pattern 103 is exposed. Next, after the mask pattern 103 is contracted, a metal protective film 105 is formed on the entire surface of the plating pattern 104 by sputtering or the like, as shown in step (C). Subsequently, as shown in step (D), the used mask pattern 103 is removed with a stripping solution. Finally, when the base metal layer 102 that is no longer needed is removed by flash etching, the intended printed wiring board is obtained as shown in step (E).

  However, when the wiring board is manufactured using the semi-additive method in this way, the limit of the formation of fine wiring has been seen due to the problem of resolution and adhesion of the photoresist used for forming the mask pattern. In recent years, it has not been possible to sufficiently cope with the miniaturization of wiring patterns that are particularly demanding. This is because when the wiring pattern is formed by the semi-additive method, a process of stacking the conductor metal by plating is required, and therefore the mask pattern, that is, the photoresist, needs to have a certain thickness. On the other hand, in order to satisfy the requirement of a thick film photoresist, a dry film resist having a film thickness of about 20 to 25 μm is generally used. The dry film resist has the advantage that it is easy to handle and a mask pattern with a high aspect ratio can be easily formed. However, in the formation of fine wiring, the dry film peels off in the middle, the resist pattern collapses, the line There still remains the problem of resist residue between them.

Japanese Patent Laying-Open No. 2003-101194 (Claims, FIG. 1) JP-A-2004-63643 (Claims, FIGS. 1 to 2)

  The object of the present invention is therefore to provide fine wiring and not to use a semi-additive method, so problems caused by the use of photoresists and dry film resists (for example, reduced resolution and adhesion, collapse of resist pattern, It is to provide a wiring board that does not involve a resist residue or the like.

  Another object of the present invention is to provide a wiring board that can meet future demands for high-density wiring and can easily manage the thickness of an insulating resin or the like laminated on a wiring pattern layer.

  Furthermore, an object of the present invention is to provide an improved manufacturing method of a wiring board capable of manufacturing the wiring board of the present invention as described above easily and with a high yield.

  Still another object of the present invention is to provide a small and high-performance electronic device in which electronic elements such as semiconductor elements are mounted on the wiring board of the present invention having fine wiring.

  These and other objects of the present invention will be readily understood from the following detailed description.

In one aspect, the present invention is a wiring board comprising a substrate and an exposed wiring pattern layer formed thereon,
After the wiring pattern layer is deposited in a groove formed at a predetermined depth in a predetermined position of the substrate, an excess amount of the wiring pattern precursor is removed from the surface side of the substrate. The wiring board is formed by removing the wiring board, and the wiring board has a flat surface.

In another aspect, the present invention is a method of manufacturing a wiring board comprising a substrate and an exposed wiring pattern layer formed thereon,
Forming a groove at a predetermined depth in a predetermined position of the prepared substrate;
Depositing a wiring pattern forming material including the groove on the substrate to form a wiring pattern precursor;
Removing an excessive amount of the precursor of the wiring pattern from the surface side of the substrate to form a wiring substrate having a flat surface and exposing the wiring pattern layer. It exists in the manufacturing method of a wiring board.

  Furthermore, in another aspect, the present invention includes the wiring board of the present invention and at least one electronic component mounted on the surface and / or inside the wiring board. In electronic devices.

  As will be understood from the following detailed description, according to the present invention, it is possible to provide a wiring board provided with fine wirings at high density.

  The wiring board of the present invention does not require the use of the semi-additive method that has been generally used in the manufacture of the wiring board, and therefore, the use of a photoresist or a dry film resist that could not be avoided by conventional techniques. The problem caused by the problem can be solved. In the wiring board of the present invention, for example, there is no problem of reduction in resolution and adhesion, and since it is not necessary to use a thick dry film resist, patterning can be performed at a high resolution. Problems such as falling down and resist residue can be solved.

  Further, according to the present invention, it is possible to form a wiring pattern layer (for example, width: about 10 μm, pitch: about 20 μm) made of fine copper wiring, which can meet the demand for future high-density wiring.

  Furthermore, since the surface of the wiring pattern layer is flat, when a thin film such as an insulating resin is further laminated on the wiring pattern layer, it is easy to manage the thickness of the insulating film formed, and The uniformity of the film can be improved.

  Furthermore, according to the present invention, the wiring board of the present invention provided with fine wiring can be manufactured easily and with a high yield.

  In the case of the wiring board of the present invention, the wiring pattern layer can be formed by filling a conductor metal into a groove formed in the insulating resin on the substrate, preferably by etching. Therefore, the thickness of the insulating resin can be set according to the wiring density. The complicated process of changing can be omitted.

  Furthermore, according to the present invention, it is possible to provide a small and high-performance electronic device in which electronic components such as semiconductor elements are mounted on the wiring board of the present invention having fine wiring.

  The wiring board, the manufacturing method thereof, and the electronic device according to the present invention can be advantageously implemented in various forms. Hereinafter, the present invention will be described with reference to preferred embodiments thereof.

  The present invention resides in a wiring board comprising a substrate and an exposed wiring pattern layer formed thereon. Here, the configuration of the wiring board is not particularly limited as long as the requirements of the present invention are satisfied. In addition to the example illustrated and shown below, the wiring board (circuit board, printed circuit board, printed circuit board) is used. It is possible to have a configuration similar to that employed in a circuit board (also called a wiring board). The wiring board of the present invention is for mounting and supporting various functional components (hereinafter collectively referred to as “electronic components”). Typical examples of mountable electronic components are as follows. Although not limited to those listed, for example, semiconductor elements such as IC chips and LSI chips, capacitor elements, reactor elements, inductor elements, and the like can be given.

  In the wiring board of the present invention, the main body is the board. Although the substrate is formed from various materials depending on the configuration of the wiring substrate, it is usually formed from an insulating resin material such as a polyimide resin, an epoxy resin, or a phenol resin. Otherwise, a copper-clad laminate, a metal core wiring board, a composite wiring board, etc., which are commonly used in this technical field, may be used as the board. In the latter case, since a copper foil or the like, which is a conductor metal, is already laminated on the surface of the substrate, the formation of the conductor metal layer in the manufacturing process of the wiring substrate can be omitted.

  In the wiring substrate of the present invention, the wiring pattern layer formed on the substrate is formed on the surface of the wiring substrate and exposed from the surface. Here, “wiring pattern layer” is synonymous with “wiring circuit”, “wiring layer”, “wiring pattern” and the like, which are terms commonly used in this technical field, and therefore, any conductor metal such as copper, It can be advantageously formed from nickel, chromium, gold, silver, aluminum or the like or an alloy thereof. In addition, since the wiring pattern layer can be formed into a thick film by a simple method, it is advantageous to form it by plating, preferably electrolytic plating. If necessary, it can be performed by combining electroless plating and electrolytic plating. Good. If acceptable, the wiring pattern layer may be formed using a conventional thin film forming method such as sputtering or vapor deposition. If necessary, an inner wiring pattern layer (wiring circuit) may be formed in advance in an arbitrary position and pattern inside the above-described substrate.

  The first thing to be noted in the wiring board of the present invention is that the wiring board is not formed by a conventional semi-additive method, that is, by using a photoresist or a dry film resist. The mask pattern (plating groove) for stacking the wiring pattern layers is not formed. The effect by this is as having demonstrated previously.

  Therefore, the wiring board of the present invention has an excess of the wiring pattern precursor after the wiring pattern layer is deposited in a groove formed at a predetermined depth in the substrate at a predetermined depth. It is formed by removing the amount from the surface side of the substrate.

  That is, in the case of the wiring board of the present invention, after forming a groove for forming a wiring pattern layer at a predetermined depth on the substrate at a predetermined depth, a wiring pattern precursor is placed in the groove portion of the wiring pattern. The layer thickness is at least the same as the final required thickness, and is preferably deposited in a larger thickness (and thus preferably the precursor of the wiring pattern with a certain thickness overflowing from the groove and covering the substrate) After that, the wiring pattern layer can be formed by removing the excess amount of the wiring pattern precursor from the surface side of the substrate.

  When the wiring pattern forming groove is formed as described above, the groove may be formed by selectively removing the substrate itself. However, after insulating resin is laminated on the substrate, the insulating resin layer It is more common and advantageous to carry out by selective removal. Here, although the selective removal of the substrate or the insulating resin layer can be performed according to various techniques, it is usually preferably performed by etching, and more preferably by plasma etching. Further, as will be described below with reference to FIG. 5, since the etching can be performed only in the downward direction, the groove is preferably formed by anisotropic etching.

  When a groove is formed on the surface of the substrate by etching, the depth of the groove can be changed in a wide range according to the thickness of the intended wiring pattern layer. As understood from the above, the depth of the groove needs to be at least the same depth as the thickness finally required for the wiring pattern layer. Considering that the excessive amount of the precursor of the pattern is removed from the surface side of the substrate, it is preferable that the depth be larger than the thickness of the wiring pattern layer. The depth of the groove is recommended to be, for example, about 10 to 15 μm or more.

  After forming the groove, a wiring pattern precursor suitable for forming the wiring pattern layer is deposited so as to fill the groove portion and cover the surface of the substrate. As described above, the wiring pattern precursor is preferably a conductor metal such as copper, and the deposition method of the precursor is preferably an electrolytic plating method.

  After the wiring pattern precursor is deposited with a predetermined film thickness, the precursor deposit is selectively removed from the surface side of the substrate to a predetermined depth. Here, the “predetermined depth” is a depth necessary for obtaining a target wiring pattern layer with a predetermined thickness by the deposit removing step and exposing the upper surface of the wiring pattern layer. Means. In addition, although various techniques can be used for selective removal of deposits, it is common to use a polishing method because the deposits are typically made of conductive metal plating. Can do. Examples of suitable polishing methods include chemical mechanical polishing (CMP) and grinding.

  As a result of removing the surface portion of the substrate by polishing to a predetermined depth, a wiring substrate having an exposed wiring pattern layer on the surface is obtained. This wiring board has a substantially flat surface and does not have steps or irregularities resulting from the wiring pattern layer forming step. That is, the surface of the wiring pattern layer and the surface of the wiring board surrounding the periphery are at the same level and are entirely flat.

Although the wiring board according to the present invention can be manufactured using various methods, it is advantageous to manufacture the wiring board as follows without using the conventional semi-additive method. That is, the method for manufacturing a wiring board of the present invention is a method for manufacturing a wiring board including a substrate and an exposed wiring pattern layer formed thereon,
Forming a groove at a predetermined depth in a predetermined position of the prepared substrate;
Depositing a wiring pattern forming material including the groove on the substrate to form a wiring pattern precursor;
Removing an excessive amount of the precursor of the wiring pattern from the surface side of the substrate to form a wiring substrate having a flat surface and exposing the wiring pattern layer. It exists in the manufacturing method of a wiring board.

  Each step of the method of the invention is advantageously carried out as described above.

  For example, the groove forming step in the substrate is performed by etching the substrate or the insulating resin layer laminated thereon, and at least the same thickness as the wiring pattern layer at the wiring pattern layer forming portion, preferably deeper than that, It can be advantageously carried out by forming a groove for forming the wiring pattern layer by etching. A suitable etching method is plasma etching having anisotropy.

  Further, the step of depositing the wiring pattern forming material to form the wiring pattern precursor uses a conductive metal such as copper as the wiring pattern forming material, and deposits the conductive metal to a predetermined thickness by plating. Can be advantageously implemented. In the case of this step, an electrolytic plating method is particularly suitable as a method for depositing the wiring pattern forming material.

  Furthermore, the process of forming the exposed wiring pattern layer can be advantageously performed by polishing from the surface side of the substrate to remove the excess amount of the precursor of the wiring pattern. In this step, the CMP method is particularly suitable as a method for removing the wiring pattern precursor.

  The method for manufacturing a wiring board according to the present invention can be implemented with various modifications within the scope of the present invention based on the above-described steps.

According to one aspect of the invention, the following steps:
Laminate insulating resin on the prepared board,
A seed layer made of a conductive metal is formed on the formed insulating resin layer,
Selectively removing the seed layer formed at the formation site of the wiring pattern layer from the substrate;
In the presence of the seed layer, the exposed region of the substrate is selectively removed to form a groove with a predetermined depth;
A wiring pattern forming material is deposited on the substrate and a wiring pattern forming material is filled in the groove to form a wiring pattern precursor, and an excess amount of the wiring pattern precursor is formed from the surface side of the substrate. The wiring board of the present invention can be advantageously manufactured by removing and forming a wiring board having a flat surface and exposing the wiring pattern layer.

  In this manufacturing method, the insulating resin layer forming step is performed by applying an insulating resin material such as a polyimide resin, an epoxy resin, or a phenol resin with a predetermined thickness on a prepared substrate and curing it. be able to. Note that this step may be omitted if the prepared substrate is made of an insulating resin material and satisfies the requirements of the present invention.

  Subsequently, a seed layer functioning as a power feeding layer for plating is formed on the formed insulating resin layer. The process for forming the seed layer is not particularly limited. For example, the seed layer uses any conductive metal, such as copper, nickel, chromium, gold, silver, aluminum or an alloy thereof, and any thin film forming method, such as metal foil lamination, electroless plating, sputtering, vacuum deposition, etc. Thus, it can be formed with a desired film thickness. Specific seed layer formation methods include, for example, lamination of an ultrathin copper foil having a thickness of about 1 to 2 μm, electroless copper plating, copper sputtering, and the like.

  Next, in the formed seed layer, only the seed layer formed at the site where the wiring pattern layer is formed is selectively removed from the substrate. Although the selective removal of the seed layer can be performed according to various techniques, it can be advantageously performed by soft etching in the presence of a resist mask formed by exposure and development of a resist material.

  First, a resist layer is formed by applying a resist material on the seed layer formed on the entire surface of the insulating resin layer. For example, a photoresist may be thinly applied at, for example, about 3 μm and cured to form a resist layer, or a thin dry film resist of, for example, about 10 μm is laminated to form a resist layer to increase resolution. May be.

  Next, pattern exposure is performed on the formed resist layer under predetermined conditions with an exposure source defined for the resist, and unnecessary portions are dissolved and removed with a predetermined developer. A resist pattern in which the underlying seed layer is exposed at the wiring pattern layer formation site is obtained.

  Thereafter, using the resist pattern as a mask, the exposed seed layer is selectively removed by so-called soft etching (also referred to as flash etching or light etching). Therefore, the seed layer in the wiring pattern layer formation site is removed by a normal etching line.

  Finally, the seed layer removal step is completed by peeling off and removing the used resist pattern from the substrate.

  As a result of selectively removing the seed layer as described above, the underlying insulating resin layer is exposed at the portion where the wiring pattern layer is formed. In this state, in the presence of the seed layer, the exposed region of the insulating resin layer is selectively removed to form a groove with a predetermined depth. As described above, this groove forming step can be advantageously performed by plasma etching having anisotropy.

  Subsequently, a wiring pattern forming material is deposited on the insulating resin layer, and a wiring pattern forming material is also filled in a groove formed in the insulating resin layer to form a wiring pattern precursor. As described above, this wiring pattern precursor forming step is advantageously performed by using a conductive metal such as copper as the wiring pattern forming material and depositing the conductive metal to a predetermined thickness by plating. Can do. In this process, electrolytic plating is suitable as a method for depositing the wiring pattern forming material. In particular, it is recommended to fill the concave groove with a conductive metal by combining electroless plating and electrolytic plating.

  Finally, an excessive amount of the wiring pattern precursor is removed from the surface side of the substrate to form a wiring substrate having a flat surface and exposing the wiring pattern layer. As described above, this wiring pattern layer forming step can be advantageously performed by polishing in the depth direction from the surface side of the substrate to remove an excessive amount of the precursor of the wiring pattern. In this step, the CMP method is particularly suitable as a method for removing the wiring pattern precursor.

According to another aspect of the invention, the following steps:
Laminate insulating resin on the prepared board,
A resist layer is formed on the formed insulating resin layer,
Selectively removing the resist layer formed at the formation site of the wiring pattern layer from the substrate;
In the presence of the formed resist pattern layer, the exposed region of the substrate is selectively removed to form a groove with a predetermined depth,
A wiring pattern forming material is deposited on the substrate and a wiring pattern forming material is filled in the groove to form a wiring pattern precursor, and an excess amount of the wiring pattern precursor is formed from the surface side of the substrate. The wiring board of the present invention can be advantageously manufactured by removing and forming a wiring board having a flat surface and exposing the wiring pattern layer.

  This manufacturing method is a modified example of the embodiment described above. A resist pattern layer is formed at an early stage of the process, and the resist pattern layer is used as a mask in place of the seed layer. Etching is performed in the presence to form a concave groove in the underlying substrate (insulating resin layer). In the case of this method, it is not necessary to form a seed layer, so that the process can be simplified.

  In this manufacturing method, the insulating resin layer forming step is performed by applying an insulating resin material such as a polyimide resin, an epoxy resin, or a phenol resin with a predetermined thickness on a prepared substrate and curing it. be able to. Note that this step may be omitted if the prepared substrate is made of an insulating resin material and satisfies the requirements of the present invention.

  Subsequently, a resist layer is formed on the formed insulating resin layer. The resist layer may be formed, for example, by applying and curing a photoresist, or may be formed by laminating a dry film resist. In either case, the resist layer is preferably formed with a relatively thick film in order to secure a level difference that can withstand the subsequent etching process.

  Next, the resist layer formed at the wiring pattern layer forming portion is selectively removed from the substrate. This selective removal process of the resist layer can be performed by exposure and development of the resist layer. For example, the formed resist layer is subjected to pattern exposure under a predetermined condition with an exposure source defined for the resist, and unnecessary portions are dissolved and removed with a predetermined developer. A resist pattern layer is obtained in which the underlying insulating resin layer is exposed at the portion where the wiring pattern layer is formed.

  Thereafter, using the resist pattern layer as a mask, the exposed region of the insulating resin layer is selectively removed to form a groove with a predetermined depth. As described above, this groove forming step can be advantageously performed by plasma etching having anisotropy. After the grooves are formed, the used resist pattern layer is peeled off.

  Subsequently, a wiring pattern forming material is deposited on the insulating resin layer, and a wiring pattern forming material is also filled in a groove formed in the insulating resin layer to form a wiring pattern precursor. As described above, this wiring pattern precursor forming step is advantageously performed by using a conductive metal such as copper as the wiring pattern forming material and depositing the conductive metal to a predetermined thickness by plating. Can do. In this process, electrolytic plating is suitable as a method for depositing the wiring pattern forming material. In particular, it is recommended to fill the concave groove with a conductive metal by combining electroless plating and electrolytic plating.

  Finally, an excessive amount of the wiring pattern precursor is removed from the surface side of the substrate to form a wiring substrate having a flat surface and exposing the wiring pattern layer. As described above, this wiring pattern layer forming step can be advantageously performed by polishing in the depth direction from the surface side of the substrate to remove an excessive amount of the precursor of the wiring pattern. In this step, the CMP method is particularly suitable as a method for removing the wiring pattern precursor.

According to yet another aspect of the invention, the following steps:
An inner wiring pattern layer made of a conductive metal is formed on the prepared substrate,
Laminating an insulating resin on the inner wiring pattern layer,
Form a through hole in the filled via formation site of the formed insulating resin layer,
A resist layer is formed on the insulating resin layer in which the through hole is formed,
From the substrate, selectively remove the resist layer formed in the formation site of the wiring pattern layer,
In the presence of the resist layer, selectively removing exposed areas of the substrate to form grooves at a predetermined depth;
A wiring pattern forming material is deposited on the substrate and a wiring pattern forming material is filled in the groove to form a wiring pattern precursor, and an excess amount of the wiring pattern precursor is formed from the surface side of the substrate. The wiring board of the present invention can be advantageously manufactured by removing and forming a wiring board having a flat surface and exposing the wiring pattern layer.

  This manufacturing method is a modification of the above-described embodiment. In addition to simplifying the process, a wiring board having a multilayer structure can be manufactured by forming vias in advance. .

  In this manufacturing method, an inner wiring pattern layer made of a conductive metal is formed on a prepared substrate. Here, the substrate is usually made of an insulating resin material, but may be made of other insulating materials if necessary. The inner wiring pattern layer can be formed according to a conventional method. For example, any conductive metal, such as copper, nickel, chromium, gold, silver, aluminum, or an alloy thereof may be formed using any thin film forming method, such as metal foil lamination, electroless plating, sputtering, vacuum deposition, etc. After forming on the substrate with a film thickness, the desired inner wiring pattern layer (wiring circuit) can be obtained by selectively removing it by etching or the like according to the desired wiring pattern.

  The insulating resin layer forming step is performed by applying an insulating resin material such as a polyimide resin, an epoxy resin, or a phenol resin with a predetermined thickness on the substrate after the inner wiring pattern layer is formed, and curing it. Can be implemented. Note that this step may be omitted if the prepared substrate is made of an insulating resin material and satisfies the requirements of the present invention.

  Next, a through hole is formed in the filled via formation portion of the formed insulating resin layer. Formation of the through-hole can be advantageously performed using conventional techniques such as laser drilling. The size of the through hole can be arbitrarily changed according to the size of the target filled via.

  Thereafter, a resist layer is formed on the insulating resin layer in which the through holes are formed. The resist layer may be formed, for example, by applying and curing a photoresist, or may be formed by laminating a dry film resist. In either case, the resist layer is preferably formed with a relatively thick film in order to secure a level difference that can withstand the subsequent etching process.

  Subsequently, the resist layer formed at the site where the wiring pattern layer is formed is selectively removed from the substrate. This selective removal process of the resist layer can be performed by exposure and development of the resist layer. For example, the formed resist layer is subjected to pattern exposure under a predetermined condition with an exposure source defined for the resist, and unnecessary portions are dissolved and removed with a predetermined developer. A resist pattern layer is obtained in which the underlying insulating resin layer is exposed at the portion where the wiring pattern layer is formed.

  Next, using the resist pattern layer as a mask, the exposed region of the insulating resin layer is selectively removed to form a groove with a predetermined depth. As described above, this groove forming step can be advantageously performed by plasma etching having anisotropy. After the grooves are formed, the used resist pattern layer is peeled off.

  Thereafter, a wiring pattern forming material is deposited on the insulating resin layer, and a wiring pattern forming material is also filled in a groove formed in the insulating resin layer to form a wiring pattern precursor. As described above, this wiring pattern precursor forming step is advantageously performed by using a conductive metal such as copper as the wiring pattern forming material and depositing the conductive metal to a predetermined thickness by plating. Can do. In this process, electrolytic plating is suitable as a method for depositing the wiring pattern forming material. In particular, it is recommended to fill the concave groove with a conductive metal by combining electroless plating and electrolytic plating.

  Finally, an excessive amount of the wiring pattern precursor is removed from the surface side of the substrate to form a wiring substrate having a flat surface and exposing the wiring pattern layer. As described above, this wiring pattern layer forming step can be advantageously performed by polishing in the depth direction from the surface side of the substrate to remove an excessive amount of the precursor of the wiring pattern. In this step, the CMP method is particularly suitable as a method for removing the wiring pattern precursor.

  The present invention further resides in an electronic device comprising the wiring board of the present invention and at least one electronic component mounted on the wiring board. Here, the electronic components to be mounted on the wiring board are not limited to those listed below. For example, as described above, semiconductor elements such as IC chips and LSI chips, capacitor elements, and reactor elements And inductor elements. Of course, these electronic components may be mounted on the surface of the wiring board, may be mounted inside the wiring board, or may be mounted in combination with the surface and inside. These electronic components may be used alone or in combination of two or more depending on the desired function. Furthermore, the respective electronic components can be electrically connected to each other by a flip chip method, a wire bonding method, or the like, or can be electrically connected to a wiring pattern layer or an external connection terminal of the wiring board.

  Subsequently, several embodiments of the present invention will be described with reference to the accompanying drawings. Needless to say, the present invention is not limited to these examples.

  FIG. 1 is a cross-sectional view showing a preferred embodiment of a wiring board according to the present invention. The wiring substrate 10 includes a substrate 1 made of a phenolic resin laminate and an insulating resin layer 2 made of an epoxy resin laminated on one side of the substrate. As shown in the figure, the insulating resin layer 2 includes a wiring pattern layer (wiring circuit) 6 with the upper surface exposed. The wiring pattern layer 6 is formed by filling a concave groove formed in the insulating resin layer 2 with copper by electrolytic plating and then removing the excessively deposited copper plating by upper polishing. Since the upper polishing is performed to form the wiring substrate 10, the surface of the insulating resin layer 2 and the surface of the wiring pattern layer 6 are at the same level. Therefore, the wiring substrate 10 has a flat surface. Yes.

  As can be understood from the following description, the illustrated wiring board 10 can be formed without using a semi-additive method that is generally used conventionally. Therefore, resolution and adhesion problems caused by the use of photoresist caused by conventional methods can be solved to form finer wiring, and problems such as resist pattern collapse and resist residue between lines can be solved. it can. In addition, since the groove to be the wiring can be formed by etching, there is no need to change the thickness of the insulating resin layer according to the wiring density. Furthermore, since the wiring pattern layer has a flat surface, it is easy to manage the thickness of the layer, for example, when an insulating resin layer is further laminated thereon, and the characteristic impedance can be improved.

  The wiring board shown in FIG. 1 can be advantageously manufactured by, for example, the method shown in order in FIG. 3 and FIG.

  First, as shown in step (A), an insulating resin layer 2 is formed by laminating an epoxy resin on one side of a phenolic resin laminate 1 prepared as a substrate. The lamination of the epoxy resin can be performed by, for example, a lamination press.

  Next, as shown in step (B), a seed layer 3 is formed on the insulating resin layer 2. The seed layer 3 can be formed, for example, by laminating metal foil, electroless plating, sputtering, vacuum deposition, or the like. In this example, the seed layer 3 is formed by laminating an ultrathin copper foil having a thickness of about 1.5 μm. Layer 3 was formed.

  After the seed layer 3 is formed, the patterning process is performed. This is because in the formed seed layer 3, only the seed layer formed at the site where the wiring pattern layer is formed is selectively removed from the substrate.

  First, as shown in step (C), a photoresist is applied on the seed layer 3 to a thickness of about 10 μm and cured. The photoresist used in this example was “PMER (trade name)” manufactured by Tokyo Ohka Kogyo Co., Ltd. A thin resist layer 4 covering the entire surface of the seed layer 3 is formed.

  Next, pattern exposure is performed on the formed resist layer 4 under a predetermined condition with an exposure source defined for the photoresist, and unnecessary portions are dissolved and removed with a predetermined developer. As shown in step (D), a resist pattern 4 is obtained in which the underlying seed layer 3 is exposed at the wiring pattern layer forming portion 14. Since the resist layer 4 is thin, fine patterning is possible.

  Thereafter, using the resist pattern 4 as a mask, the exposed seed layer 3 is selectively removed by so-called soft etching. The etching solution used in this example was “VE-7100 (trade name)” manufactured by MEC. As a result of the soft etching, as shown in step (E), the seed layer 3 in the wiring pattern layer forming portion 14 is removed by a normal etching line.

  Finally, the used resist pattern is peeled off from the substrate. As shown in the step (F), the substrate 1 having the patterned seed layer 3 on the insulating resin layer 2 is obtained.

  After selectively removing the seed layer as described above, the exposed region of the insulating resin layer 2 is etched to a predetermined depth using the patterned seed layer 3 as a mask, as shown in step (G). Thus, the concave groove 12 is formed. In this example, the groove 12 was formed by plasma etching having anisotropy. The conditions for plasma etching are as follows.

Reactive gas: O ₂ = 900 sccm; CF ₄ = 100 sccm
Output: 1,500W
Etching depth (insulating resin layer): about 10 μm

  In this example, since the anisotropic plasma etching was performed, the concave groove 12 could be formed with a desired profile. For reference, referring to FIG. 5, if etching is performed in the direction of the arrow without anisotropy as in step (A), as etching progresses, as shown in step (B) The bottom surface a of the groove 12 to be formed is roughened, and side etching is caused on the side surface b of the groove 12. In other words, by performing plasma etching having anisotropy according to the present invention, it is possible to accurately form the fine groove 12 having a narrow line spacing.

  After the concave groove for forming the wiring pattern layer is formed as described above, a wiring pattern forming material is deposited by plating to form a wiring pattern precursor. In the case of this example, this wiring pattern precursor formation process was implemented using copper as a wiring pattern forming material.

  First, as shown in the step (H), the electroless copper plating layer 5 is formed with a thickness of about 1 μm on the surface of the insulating resin layer 2 provided with the grooves 12. The electroless copper plating solution used in this example was “Sulcup PEA (trade name)” manufactured by Uemura Kogyo Co., Ltd. Although omitted in the figure for simplification, the patterned seed layer formed in the previous step also remains under the electroless copper plating layer 5.

  Subsequently, electrolytic copper plating is performed using the formed electroless copper plating layer 5 as a power feeding layer. As a result of this electrolytic copper plating, as shown in step (I), a thick electrolytic copper plating layer 6 filled with the concave grooves 12 of the insulating resin layer 2 is formed. Although omitted in the drawing for simplification, the electroless copper plating layer 5 formed in the previous step also remains below the electrolytic copper plating layer 6.

  Finally, as shown in the step (J), the upper part of the electrolytic copper plating layer 6 formed of a thick film (excessive amount of copper plating; indicated by a dotted line in the figure) is polished from the surface side of the substrate 1. To remove. The polishing method used in this example is a CMP method. As a result of polishing, a wiring substrate 10 having a flat surface and exposing the wiring pattern layer 6 is obtained.

  According to another method, the wiring board shown in FIG. 1 can be advantageously manufactured also by the method shown in order in FIGS. In the case of this method, since the photoresist is used as an etching mask, the process can be shortened and simplified as compared with the method described above with reference to FIGS.

  First, as shown in step (A), an insulating resin layer 2 is formed by laminating an epoxy resin on one side of a phenolic resin laminate 1 prepared as a substrate.

  Next, as shown in step (B), a resist layer 7 is formed on the insulating resin layer 2. Since the resist layer 7 is preferably formed with a relatively thick film in order to secure a level difference that can withstand a subsequent etching process, in this example, a dry film resist having a thickness of about 15 μm (manufactured by Nichigo Morton) is used. A resist layer 7 was formed from “ALPHA (trade name)”.

  Next, as shown in step (C), the resist layer 7 formed at the wiring pattern layer forming portion 17 is selectively removed from the substrate. In this step, the resist layer 7 is subjected to pattern exposure under a predetermined condition with an exposure source defined for the dry film resist, and unnecessary portions are dissolved and removed with a predetermined developer. As shown in the figure, a resist pattern layer 7 is obtained in which the underlying insulating resin layer 2 is exposed at the wiring pattern layer forming portion 17.

  After forming the resist pattern layer as described above, as shown in step (D), the exposed region of the insulating resin layer 2 is etched to a predetermined depth using the resist pattern layer 7 as a mask to form a concave shape. A groove 12 is formed. In this example, the groove 12 was formed by plasma etching having anisotropy. The conditions for plasma etching are as follows.

Reactive gas: O ₂ = 900 sccm; CF ₄ = 100 sccm
Output: 1,500W
Etching depth (insulating resin layer): about 10 μm

  After the plasma etching is completed, the used resist pattern layer is peeled off. As shown in the step (E), the substrate 1 provided with the concave grooves 12 at the site where the wiring pattern layer is formed is obtained.

  After the concave groove for forming the wiring pattern layer is formed as described above, a wiring pattern forming material is deposited by plating to form a wiring pattern precursor. In the case of this example, this wiring pattern precursor formation process was implemented using copper as a wiring pattern forming material.

  First, as shown in step (F), the electroless copper plating layer 5 is formed with a thickness of about 1 μm on the surface of the insulating resin layer 2 provided with the grooves 12. The electroless copper plating solution used in this example was “Sulcup PEA (trade name)” manufactured by Uemura Kogyo Co., Ltd.

  Subsequently, electrolytic copper plating is performed using the formed electroless copper plating layer 5 as a power feeding layer. As a result of this electrolytic copper plating, as shown in step (G), a thick electrolytic copper plating layer 6 filled with the concave grooves 12 of the insulating resin layer 2 is formed.

  Finally, as shown in the step (H), the upper part of the electrolytic copper plating layer 6 formed of a thick film (excessive amount of copper plating; indicated by a dotted line in the figure) is polished from the surface side of the substrate 1. To remove. The polishing method used in this example is a CMP method. As a result of polishing, a wiring substrate 10 having a flat surface and exposing the wiring pattern layer 6 is obtained.

  FIG. 2 is a cross-sectional view showing another preferred embodiment of the wiring board according to the present invention. The wiring substrate 10 includes a substrate 1 made of a phenolic resin laminate and an insulating resin layer 2 made of an epoxy resin laminated on one side of the substrate. As shown in the figure, the insulating resin layer 2 includes an inner wiring pattern layer (wiring circuit) 8 and an outer wiring pattern layer (wiring circuit) 6 with the upper surface exposed. The wiring pattern layer 6 is formed by filling a concave groove formed in the insulating resin layer 2 with copper by electrolytic plating and then removing the excessively deposited copper plating by upper polishing. Since the upper polishing is performed to form the wiring substrate 10, the surface of the insulating resin layer 2 and the surface of the wiring pattern layer 6 are at the same level. Therefore, the wiring substrate 10 has a flat surface. Yes. Further, the wiring pattern layer 8 and the wiring pattern layer 6 are electrically connected through a filled via 9. As can be easily understood, the wiring board 10 of FIG. 2 has the same configuration as the wiring board 10 of FIG. 1 described above, but the wiring pattern layer 8 and the wiring pattern layer 6 are filled vias 9. Therefore, the wiring board can be multi-layered.

  The wiring board shown in FIG. 2 can be advantageously manufactured by the method shown in order in FIGS.

  First, as shown in step (A), an inner wiring pattern layer (wiring circuit) 8 and an insulating resin layer 2 are sequentially formed on one side of a phenolic resin laminate 1 prepared as a substrate. In the case of this example, after laminating the copper foil on the substrate 1, the inner wiring pattern layer 8 was obtained by etching unnecessary portions according to the desired wiring pattern. Moreover, the insulating resin layer 2 was obtained by apply | coating an epoxy resin on the board | substrate 1 after forming the inner layer wiring pattern layer 8, and making it harden | cure.

  Subsequently, as shown in step (B), a through hole 22 is formed in the filled via formation portion of the formed insulating resin layer 2. In the case of this example, the through hole 22 was formed using laser drilling. The through hole 22 terminates in the inner wiring pattern layer 8 as illustrated.

  Next, as shown in step (C), a resist layer 7 is formed on the insulating resin layer 2. Since the resist layer 7 is preferably formed with a relatively thick film in order to secure a level difference that can withstand a subsequent etching process, in this example, a dry film resist having a thickness of about 15 μm (manufactured by Nichigo Morton) is used. A resist layer 7 was formed from “ALPHA (trade name)”.

  Next, as shown in step (D), the resist layer 7 formed in the wiring pattern layer forming portion 17 is selectively removed from the substrate. In this step, the resist layer 7 is subjected to pattern exposure under a predetermined condition with an exposure source defined for the dry film resist, and unnecessary portions are dissolved and removed with a predetermined developer. As shown in the figure, a resist pattern layer 7 is obtained in which the insulating resin layer 2 or the inner wiring pattern layer 8 is exposed at the wiring pattern layer forming portion 17.

  After forming the resist pattern layer as described above, as shown in step (E), the exposed region of the insulating resin layer 2 is etched to a predetermined depth using the resist pattern layer 7 as a mask to form a concave shape. A groove 12 and a concave stepped groove 12 are formed. In the case of this example, each concave groove was formed by plasma etching having anisotropy. The conditions for plasma etching are as follows.

Reactive gas: O ₂ = 900 sccm; CF ₄ = 100 sccm
Output: 1,500W
Etching depth (insulating resin layer): about 10 μm

  After the plasma etching is completed, the used resist pattern layer is peeled off. As shown in the step (F), the substrate 1 provided with the concave groove 12 or the concave stepped groove 12 at the formation site of the wiring pattern layer is obtained.

  After the concave groove for forming the wiring pattern layer is formed as described above, a wiring pattern forming material is deposited by plating to form a wiring pattern precursor. In the case of this example, this wiring pattern precursor formation process was implemented using copper as a wiring pattern forming material.

  First, as shown in the step (G), the electroless copper plating layer 5 is formed with a thickness of about 1 μm on the surface of the insulating resin layer 2 provided with the grooves 12. The electroless copper plating solution used in this example was “Sulcup PEA (trade name)” manufactured by Uemura Kogyo Co., Ltd.

  Subsequently, electrolytic copper plating is performed using the formed electroless copper plating layer 5 as a power feeding layer. As a result of this electrolytic copper plating, as shown in step (H), a thick electrolytic copper plating layer 6 filled with the concave grooves 12 of the insulating resin layer 2 is formed.

  Finally, as shown in step (I), the upper part of the electrolytic copper plating layer 6 formed of a thick film (excessive amount of copper plating; indicated by a dotted line in the figure) is polished from the surface side of the substrate 1. To remove. The polishing method used in this example is a CMP method. As a result of polishing, a wiring substrate 10 having a flat surface and exposing the wiring pattern layer 6 is obtained. A part of the wiring pattern layer 6 is electrically connected to the inner wiring pattern layer 8 through a filled via 9 filled with copper.

  FIG. 10 is a cross-sectional view showing one embodiment of the semiconductor device of the present invention manufactured using the wiring board of FIG. The semiconductor device 20 includes a wiring board 10 on which two semiconductor elements (LSI chips in the figure) 21 are mounted. The wiring substrate 10 includes a substrate 1 made of a phenolic resin laminate and an insulating resin layer 2 made of an epoxy resin laminated on one side of the substrate. The insulating resin layer 2 includes a copper wiring pattern layer 6 whose upper surface is exposed. Since the surface of the wiring board 10 including the copper wiring pattern layer 6 is flat, the LSI chip 21 is stably mounted. Each LSI chip 21 is connected to the copper wiring pattern layer 6 through a bonding wire 23. Although not shown, the LSI chip 21 is sealed with an insulating resin.

It is sectional drawing which showed one preferable form of the wiring board by this invention. It is sectional drawing which showed another preferable form of the wiring board by this invention. FIG. 2 is a cross-sectional view illustrating a manufacturing process (first half) of the wiring board of FIG. FIG. 3 is a cross-sectional view illustrating a manufacturing process (second half) of the wiring board of FIG. 1 in order. It is sectional drawing which showed the fault at the time of using the method other than this invention in the manufacturing process of the wiring board of FIG. FIG. 5 is a cross-sectional view illustrating another manufacturing process (first half) of the wiring board of FIG. 1 step by step. FIG. 5 is a cross-sectional view illustrating another manufacturing process (second half) of the wiring board of FIG. 1 in order. FIG. 3 is a cross-sectional view sequentially showing a manufacturing process (first half) of the wiring board of FIG. 2. FIG. 3 is a cross-sectional view illustrating a manufacturing process (second half) of the wiring board of FIG. 2 in order. It is sectional drawing which showed one form of the semiconductor device of this invention using the wiring board of FIG. It is sectional drawing which showed the conventional manufacturing process which manufactures a printed wiring board using a semi-additive method later on.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Insulating resin layer 3 Seed layer 4 Resist layer 5 Electroless plating layer 6 Electrolytic plating layer 7 Resist layer 8 Inner wiring pattern layer 9 Filled via 10 Wiring board 20 Semiconductor device

Claims (20)

A wiring board comprising a substrate and an exposed wiring pattern layer formed thereon,
After the wiring pattern layer is deposited in a groove formed at a predetermined depth in a predetermined position of the substrate, an excess amount of the wiring pattern precursor is removed from the surface side of the substrate. A wiring board formed by removing the wiring board, wherein the wiring board has a flat surface.   The wiring board according to claim 1, wherein the wiring pattern layer is formed without using a semi-additive method.   The wiring board according to claim 1, wherein the precursor of the wiring pattern is made of a conductive metal plating deposit.   The said groove | channel is an etching groove | channel formed in the formation site | part of the said wiring pattern layer as the thickness of the pattern layer or deeper than that, The one of Claims 1-3 characterized by the above-mentioned. Wiring board.   The wiring board according to claim 1, wherein the groove is formed by anisotropic etching.   The wiring board according to claim 1, further comprising an inner wiring pattern layer. A method of manufacturing a wiring board comprising a substrate and an exposed wiring pattern layer formed thereon,
Forming a groove at a predetermined depth in a predetermined position of the prepared substrate;
Depositing a wiring pattern forming material including the groove on the substrate to form a wiring pattern precursor;
Removing an excessive amount of the precursor of the wiring pattern from the surface side of the substrate to form a wiring substrate having a flat surface and exposing the wiring pattern layer. A method for manufacturing a wiring board.   The method for manufacturing a wiring board according to claim 7, wherein the wiring pattern forming material is made of a conductive metal, and the precursor of the wiring pattern is formed by plating.   9. The groove forming step, wherein the substrate is etched to form an etching groove at a position where the wiring pattern layer is formed, which is equal to or deeper than the thickness of the pattern layer. The manufacturing method of the wiring board as described.   The method for manufacturing a wiring board according to claim 9, wherein the etching is anisotropic etching.   The method for manufacturing a wiring board according to any one of claims 7 to 10, wherein polishing is performed from a surface side of the board to remove an excessive amount of the precursor of the wiring pattern. Laminate insulating resin on the prepared board,
A seed layer made of a conductive metal is formed on the formed insulating resin layer,
Selectively removing the seed layer formed at the formation site of the wiring pattern layer from the substrate;
In the presence of the seed layer, the exposed region of the substrate is selectively removed to form a groove with a predetermined depth;
A wiring pattern forming material is deposited on the substrate and a wiring pattern forming material is filled in the groove to form a wiring pattern precursor, and an excess amount of the wiring pattern precursor is formed from the surface side of the substrate. The method for manufacturing a wiring board according to claim 7, wherein the wiring board is removed to form a wiring board having a flat surface and exposing the wiring pattern layer.   13. The method of manufacturing a wiring board according to claim 12, wherein the step of selectively removing the seed layer is performed by soft etching in the presence of a resist mask formed by exposure and development of a resist material. Laminate insulating resin on the prepared board,
A resist layer is formed on the formed insulating resin layer,
From the substrate, selectively remove the resist layer formed in the formation site of the wiring pattern layer,
In the presence of the formed resist pattern layer, the exposed region of the substrate is selectively removed to form a groove with a predetermined depth,
A wiring pattern forming material is deposited on the substrate and a wiring pattern forming material is filled in the groove to form a wiring pattern precursor, and an excess amount of the wiring pattern precursor is formed from the surface side of the substrate. The method for manufacturing a wiring board according to claim 7, wherein the wiring board is removed to form a wiring board having a flat surface and exposing the wiring pattern layer.   The method for manufacturing a wiring board according to claim 14, wherein the step of selectively removing the resist layer is performed by exposing and developing the resist layer. An inner wiring pattern layer made of a conductive metal is formed on the prepared substrate,
Laminating an insulating resin on the inner wiring pattern layer,
Form a through hole in the filled via formation site of the formed insulating resin layer,
A resist layer is formed on the insulating resin layer in which the through hole is formed,
From the substrate, selectively remove the resist layer formed in the formation site of the wiring pattern layer,
In the presence of the formed resist pattern layer, the exposed region of the substrate is selectively removed to form a groove with a predetermined depth,
A wiring pattern forming material is deposited on the substrate and a wiring pattern forming material is filled in the groove to form a wiring pattern precursor, and an excess amount of the wiring pattern precursor is formed from the surface side of the substrate. The method for manufacturing a wiring board according to claim 7, wherein the wiring board is removed to form a wiring board having a flat surface and exposing the wiring pattern layer.   The method for manufacturing a wiring board according to claim 16, wherein the step of selectively removing the resist layer is performed by exposing and developing the resist layer.   18. The method for manufacturing a wiring board according to claim 16, wherein the through hole is formed by a laser.   An electronic device comprising: the wiring board according to claim 1; and at least one type of electronic component mounted on the surface and / or inside of the wiring board.   The electronic device according to claim 19, wherein the electronic component is a semiconductor element.

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