WO2002100142A1 - Wiring board and its production method - Google Patents

Wiring board and its production method Download PDF

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Publication number
WO2002100142A1
WO2002100142A1 PCT/JP2002/005162 JP0205162W WO02100142A1 WO 2002100142 A1 WO2002100142 A1 WO 2002100142A1 JP 0205162 W JP0205162 W JP 0205162W WO 02100142 A1 WO02100142 A1 WO 02100142A1
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WO
WIPO (PCT)
Prior art keywords
wiring
substrate
wiring board
hole
layer
Prior art date
Application number
PCT/JP2002/005162
Other languages
French (fr)
Japanese (ja)
Inventor
Yoshihide Yamaguchi
Takao Terabayashi
Hiroshi Hozoji
Hiroyuki Tenmei
Naoya Kanda
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO2002100142A1 publication Critical patent/WO2002100142A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/0949—Pad close to a hole, not surrounding the hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1581—Treating the backside of the PCB, e.g. for heating during soldering or providing a liquid coating on the backside
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching

Definitions

  • the present invention relates to a wiring board and a method for manufacturing the same.
  • ceramic wiring boards have been widely used as multilayer wiring boards having through holes. That is, after forming through holes in a ceramic green sheet (hereinafter sometimes referred to as a green sheet) in which ceramic raw material powders are bound with an organic resin as a binder, a wiring pattern is formed by screen printing using a conductive paste. At the same time, the conductive paste is filled into the through holes connecting the wiring patterns on each sheet. Then, a predetermined number of green sheets on which a wiring pattern is formed are stacked, pressure-bonded, and fired to produce a ceramic wiring board.
  • a ceramic green sheet hereinafter sometimes referred to as a green sheet
  • a wiring pattern is formed by screen printing using a conductive paste.
  • the conductive paste is filled into the through holes connecting the wiring patterns on each sheet.
  • a predetermined number of green sheets on which a wiring pattern is formed are stacked, pressure-bonded, and fired to produce a ceramic wiring board.
  • the ceramic wiring board undergoes firing and cooling steps during its manufacture. At this time, the binder is delaminated and pressed while removing the binder from the green sheet and the conductive paste. However, since their deformation rates are different, there is a problem that the wiring is likely to be deformed in a fine wiring pattern. In addition, the ceramic substrate and the wiring material also undergo thermal deformation in the process of cooling from the sintering temperature after the completion of the compression bonding, so that it was difficult to calculate the thermal deformation of the entire substrate.
  • the binder volatilizes during firing of the ceramic substrate, the surface of the ceramic substrate becomes uneven, and it is difficult to form a fine wiring pattern as it is.
  • a multilayer wiring substrate having a core substrate a glass substrate or a silicon substrate
  • glass substrates or silicon substrates are not widely used as multilayer wiring substrates with through holes because the substrates are fragile.
  • Japanese Patent Application No. Hei 8-5-274989 discloses a glass substrate on which a semiconductor chip is mounted.
  • the glass substrate has a semiconductor chip mounted on one surface, and does not have a wiring layer composed of an insulating layer and a conductor layer formed on both surfaces of the glass substrate.
  • Japanese Patent Application Laid-Open No. H10-224206 discloses a substrate in which a through hole is formed in a photosensitive glass using an exposure and development process.
  • This board when a bare chip is mounted, has both a function as an inspection board at the time of panning and a function as an interposer (material connecting the bare chip and external terminals) for connection to a board such as a printed circuit board.
  • this does not mean that a wiring layer composed of an insulating layer and a conductor layer is formed in multiple layers on a core substrate.
  • the through holes are formed by sandblasting.
  • Japanese Patent Application Laid-Open No. H11-2443267 discloses a wiring board in which wiring is formed on an insulating substrate having a through hole.
  • the insulating substrate is formed by a ceramic sintered body such as a glass ceramic sintered body.
  • the ceramic green sheet is subjected to an appropriate punching process. It is disclosed that it is manufactured by forming a predetermined shape and firing at a high temperature.
  • the diameter of the through hole is gradually increased from the center of the substrate toward both ends of the opening.
  • the insulating substrate is a glass ceramic, is not a glass substrate, and does not have a multilayer wiring layer composed of an insulating layer and a conductor layer formed on the insulating substrate.
  • An object of the present invention is to provide a low-cost wiring board capable of high-density wiring.
  • Another object of the present invention is to provide a multi-layer wiring board having a substrate having a through hole and a thin film wiring layer formed on the surface of the substrate, the wiring board having high reliability and capable of high-density wiring. At low cost.
  • a method for manufacturing a wiring board comprising: a step of forming a wiring layer having a conductor layer and an insulating layer on a glass substrate in multiple layers; and a first step of forming a wiring layer formed on one surface of the glass substrate. Forming a hole, performing a sand blast on the glass substrate from a position where the first hole is formed, forming a second hole in the glass substrate, and an inner wall surface of the second hole. And forming a wiring on the outermost surface of the wiring layer.
  • a method for manufacturing a wiring board comprising: forming a hole in a glass substrate by sand plast; forming a wiring on at least one surface of the glass substrate and an inner wall surface of the hole.
  • FIG. 1 is a cross-sectional view of a wiring board in which wiring is formed on an insulating substrate having a through hole.
  • FIG. 2 is a diagram showing one embodiment of the wiring board according to the present invention.
  • FIG. 3 is a view showing one embodiment of a multi-chip module having a wiring board according to the present invention.
  • FIG. 4 is a view showing a state where a semiconductor module is mounted on a mounting board.
  • FIG. 5 is a perspective view showing one embodiment of the semiconductor module according to the present invention.
  • Figure 6 is a photograph showing through holes formed in a glass substrate by sand plasting and photoetching.
  • FIG. 7 is a diagram showing one embodiment of the wiring board according to the present invention.
  • FIG. 8 is a diagram showing a state in which a multichip module having a wiring board according to the present invention is mounted on a mounting board.
  • FIG. 9 is a diagram showing one embodiment of a wiring board according to the present invention.
  • FIG. 10 is a diagram showing a state in which a multichip module having a wiring board according to the present invention is mounted on a mounting board.
  • FIG. 11 is a view showing an embodiment of a manoret chip module having a wiring board according to the present invention.
  • FIG. 12 is a diagram showing an example of a combination of semiconductor chips mounted on a multilayer wiring board.
  • FIG. 13 is a flowchart of the manufacturing process of the wiring board according to the present invention.
  • FIGS. 14a, 14b and 14c are views showing an example of the manufacturing process of the wiring board according to the present invention.
  • FIGS. 15a and 15b are views showing an example of the manufacturing process of the wiring board according to the present invention.
  • FIG. 16 is a diagram illustrating an example of a manufacturing process of the wiring board according to the present invention.
  • FIG. 17 is a diagram showing the relationship between the wiring and the position at which particles by sandblasting strike.
  • FIG. 18 is a flowchart of the manufacturing process of the wiring board according to the present invention.
  • FIGS. 19, 19b, and 19c are views showing an example of the manufacturing process of the wiring board according to the present invention.
  • 20a, 20b and 20c are views showing an example of the manufacturing process of the wiring board according to the present invention.
  • FIG. 21 is a photograph showing a state where an unfilled portion is formed when the through hole is filled.
  • 22a, 22b and 22c are views showing an example of the manufacturing process of the wiring board according to the present invention.
  • FIGS. 23a and 23b are views showing an example of the manufacturing process of the wiring board according to the present invention.
  • FIG. 24 is a schematic view of a through hole formed in a substrate by sand plast.
  • FIG. 25 is a diagram showing through-holes formed in an insulating substrate to which members are applied by sandplast.
  • FIGS. 26a, 26b, 26c and 26d are diagrams showing a method of forming a wiring in a through hole of a substrate.
  • FIG. 27 is a diagram of an experimental result showing the relationship between the glass transition temperature (Tg) and the coefficient of linear expansion.
  • FIG. 28 is a diagram illustrating a state in which a large number of wiring substrates are formed using a glass substrate or a ceramic substrate. ⁇
  • FIG. 29 is a diagram showing one embodiment of the wiring board according to the present invention.
  • FIGS. 30a, 30b, 30c, 30d, 30e, 30f, 308 and 311 are diagrams showing a method for manufacturing a gyroscope.
  • Figures 31a, 31b, 31c, 31d, and 31e are views showing the formation of through holes in the substrate by the sand-plast method.
  • FIG. 32 is a diagram showing one embodiment of the wiring board according to the present invention.
  • FIG. 33 is a view showing one embodiment of the wiring board according to the present invention.
  • FIG. 34 is a diagram showing one embodiment of the wiring board according to the present invention.
  • FIG. 35 is a diagram showing the relationship between the wiring and the position at which particles by sandblasting strike.
  • FIG. 1 is a cross-sectional view of a part of a wiring board in which a wiring 120 is formed on a substrate 1 (core substrate 1) having a through hole 100.
  • FIG. 2 shows a multilayer wiring board having a substrate 1 having a through hole 100, a multilayer wiring layer 3, an insulating layer 5 for stress relaxation (stress relaxation layer 5), and the like.
  • FIG. 6 is a sectional view showing a part of FIG.
  • FIG. 3 is a cross-sectional view showing a part of a multi-chip module in which a semiconductor device 9 (hereinafter, also referred to as a semiconductor element or a semiconductor chip) or the like is mounted on a multilayer wiring board 6 as an electronic device using the multilayer wiring board.
  • FIG. 3 is a cross-sectional view taken along aa ′ of FIG.
  • FIG. 4 is a cross-sectional view showing a state in which the multichip module is mounted on a mounting board (user board) 10.
  • FIG. 5 is a perspective view of an example of the multichip module.
  • the multilayer wiring layer 3 includes a plurality of thin film wiring layers 2, and the thin film wiring layer 2 has a wiring 120 and an interlayer insulating layer 110.
  • the wiring 120 includes the wiring inside the via and the wiring pad.
  • the stress relaxation layer 5 is not always necessary, and may be formed as necessary.
  • an insulating layer may be formed between the outermost wirings of the multilayer wiring layer 3 and the stress relaxation layer 5.
  • the multilayer wiring substrate 6 itself may be a substrate having external connection terminals, for example, the solder bumps 7, or may be a substrate having no external connection terminals.
  • a glass substrate or a silicon substrate is used as the substrate 1 (also referred to as a core substrate 1 or an insulating substrate 1). Since the silicon material itself is conductive (semiconductor to conductor), when a silicon substrate is used as the insulating substrate 1, it is necessary to form an insulating film on its surface.
  • Glass or silicon substrates have better smoothness than conventional ceramic substrates Therefore, a finer wiring pattern can be formed on a glass substrate or a silicon substrate than on a conventional ceramic substrate.
  • the thermal expansion coefficient of the glass or silicon substrate is about 3 ppm / ° C to about 5 ppm / ° C.Since the thermal expansion of the substrate is smaller than that of a conventional ceramic substrate, short-circuiting of wiring due to thermal expansion may occur. And fine wiring can be formed.
  • the thermal expansion coefficient of a glass substrate or a silicon substrate is closer to that of the silicon of the semiconductor element (semiconductor chip) mounted on the substrate than the ceramic substrate, so that between the glass substrate or the silicon substrate and the semiconductor device, The stress generated due to the difference in thermal expansion coefficient between the substrate and the semiconductor element is small, and the connection reliability between the multilayer wiring substrate and the semiconductor device is improved.
  • the thermal expansion coefficient is about 3 ppm / ° C, and the thermal expansion coefficient is almost equal to that of the semiconductor element 9. Does not occur.
  • the silicon substrate has excellent thermal conductivity, so that the heat treatment in the manufacturing process is uniform and high yields can be obtained. Further, when used as a wiring board, it is advantageous from the viewpoint of heat radiation characteristics.
  • the silicon material itself is conductive (semiconductor to conductor), when a silicon substrate is used as an insulating substrate, it is necessary to form an insulating film on the surface thereof.
  • the insulating film include a thermal oxide film formed on the surface by heating in steam and an organic resin film.
  • the thermal expansion coefficient is slightly larger than that of the silicon substrate, about 5.0, but the thermal stress generated between the semiconductor device and the multilayer wiring substrate is sufficiently small.
  • glass has an insulating property
  • the surface of the glass substrate or the inner surface of the through hole is filled with a conductive substance, or the wiring is formed by plating or the like. There is no need to form an insulating film again, and the manufacturing process can be simplified.
  • suitable glass compositions for this embodiment include soda glass, low alkali glass, non-alkali glass, and ion-strengthened glass. It is appropriately selected in consideration of the above.
  • alkali-free glass or low-strength glass is preferable. This is because a glass having a lower Li-ion content generally has a lower linear expansion coefficient. In other words, since the linear expansion coefficient of silicon in a semiconductor device is as small as about 3 pp mZ ° C, the glass having a lower Al-ion ratio has a closer linear expansion coefficient between the insulating substrate and the semiconductor device, and the semiconductor device 9 and the multilayer wiring substrate This is because the thermal stress during 6 becomes smaller.
  • the connection reliability between the semiconductor device 9 and the multilayer wiring board 6 depends not only on the characteristics of the glass material but also on the connection structure between the two and the selection of the underfill material. The glass material is selected in consideration of the above.
  • connection reliability between the entire semiconductor module 100 and the mounting substrate 100 soda glass having a large alkali content is preferable. Since the linear expansion coefficient of the mounting substrate 10 is as large as 10 to 20 ppm / ° C, the difference in linear expansion coefficient between the multilayer wiring substrate 6 and the mounting substrate 10 increases as the alkali content of the glass increases. This is because the thermal stress is small.
  • the connection reliability between the multilayer wiring board 6 and the mounting board 10 depends not only on the characteristics of the glass material but also on the material and structure of the stress relieving layer provided on the surface of the multilayer wiring board 6. Thickness, area, etc.), so select the glass material in consideration of these factors.
  • Low alkali glass which has an intermediate alkali ion content between soda lime and non-alkali glass, is preferred.
  • the thickness of the insulating substrate 1 is preferably from 100 to 100 / m, more preferably from about 300 to 500 Atm. If the thickness of the insulating substrate 1 is 1000 Aim or more, the cost of through-hole processing increases, which is not practical. On the other hand, if it is less than l OO / zm, handling properties such as transport in the substrate manufacturing process are inferior, and when the through hole 100 is formed, the strength of the insulating substrate 1 may be reduced and the insulating substrate 1 may be damaged. Confuse.
  • This insulating substrate 1 has a through hole 100 formed by sand plast. You.
  • the through holes 100 allow interconnections formed on both sides of the substrate to be interconnected and maintained.
  • sandblasting as shown in FIG. 31, a film having anti-sandplast resistance is formed on a glass substrate (a), and an opening is formed in the film by using a photolithography technique (b) to form a mask. . Thereafter, abrasive particles are sprayed on the mask layer (c) to form a through hole while crushing the glass in the opening in minute units (d). Thereafter, by removing the mask (e), the insulating substrate 1 having the through holes is formed.
  • the diameter of the through hole 100 is often different between one opening end and the other opening end.
  • through-holes through-holes of almost constant diameter are easily formed, whereas in sand blasting, the surface of the substrate where sand blasting has started (the processing start surface) is the other.
  • the diameter of the through hole 100 gradually decreases toward the (processing end surface).
  • the reason for this shape is that if the hole becomes deeper as the processing proceeds, the pressure of the air carrying the processing powder decreases (pressure loss) and the efficiency of the processing powder itself decreases. .
  • crushed powder of the glass to be processed is also generated, and since the direction of movement is opposite to that of the processed powder, a collision occurs that erases the kinetic energy of the processed powder. It is easier. It is also possible to make the opening diameters of the through-holes formed in the multilayer wiring board 6 the same on both sides as long as sand-blasting is performed from both sides. However, in that case, it is necessary to control the processing end point.
  • FIG. 6 shows a through hole 100 formed by sandplast and a through hole formed by photoetching.
  • the wiring on the inner wall of the through hole 100 has strong adhesion strength.
  • plated wiring can be precisely formed on the inner surface of the through hole 100 after the formation of the power supply film.
  • In order to adjust the angle of the taper there are methods such as changing the particle size of the particles used for the sand plast as the processing progresses and adjusting the wind pressure. You.
  • the shape of the through-hole may be widened from the center of the insulating substrate toward the outside by sand branding from both sides.
  • the time required for forming the through hole is shorter than when the through hole is opened from one side, and the diameter of the through hole at the opening end can be reduced.
  • an insulating substrate having a through-hole in which the direction of the taper is opposite can be formed. If the taper direction of the through holes is the same, the insulating substrate may warp due to stress.However, if the direction of the taper of the through hole is different, the warping of the insulating substrate can be prevented, and then fine wiring is placed on the insulating substrate. Can be formed.
  • the multilayer wiring board according to the present embodiment can be used, for example, as an interposer of a multi-chip module.
  • FIG. 4 shows that the semiconductor device 9 is mounted on the surface of the insulating substrate 1 where the through hole 100 has a small opening diameter (primary side of the substrate), and the surface with the large opening diameter (secondary side of the substrate) is The figure shows a semiconductor module mounted on a mounting board 10 on which a semiconductor module is mounted. This allows semiconductor devices to be mounted and connected at a narrow pitch on the primary side of the substrate.
  • the secondary side opening diameter of the through hole 100 is from 100 to 100 / m, and is desirably about 1/10 to 10 times the thickness of the insulating substrate 1. If the secondary opening diameter exceeds about 10 times the thickness of the insulating substrate 1, the mechanical strength at that portion of the insulating substrate 1, for example, the bending strength cannot be maintained. Conversely, when the secondary opening diameter is smaller than about 1Z10, which is the thickness of the insulating substrate 1, approximately 90 degrees, at least 88 degrees, is required to form a hole penetrating to the primary side. Since a taper angle is required, it is likely to be difficult to form wiring on the wall of the through hole. In addition, it becomes difficult for the processing powder to reach the inside of the hole, and as a result, the speed of sandblasting is reduced.
  • the secondary side opening diameter of the through hole is from 200 ⁇ m to 300 ⁇ m, and is about / to about 1 times the thickness of the insulating substrate 1.
  • the through-hole interior The wiring layout for interconnecting the wiring and the solder bumps 7 is also easy.
  • the opening diameter on the primary side is from 5 im to 300 / im, more preferably from 10 ⁇ m to 100 um, and the thickness of the insulating substrate 1 is about 1 Z 50 force to about 1 / 5 times.
  • the wiring of the multilayer wiring layer 3 on the primary side needs to have a narrow pitch, and a smaller opening diameter is desirable. That is, if the opening diameter on the primary side of the through hole 100 is reduced, more wiring channels can pass between the through holes, and as a result, the wiring of the thin film wiring layer 2 having a smaller number of layers can be formed. This is because the bow I can be turned.
  • a conductive material exists on the inner surface of the through hole 100 that enables electrical connection on both surfaces of the insulating substrate 1.
  • the copper wiring 101 is formed by forming a power supply film, for example, Cr / Cu on the inner surface of the through hole 100 by sputtering or the like, and thereafter, by electroplating. Note that an insulating material may be filled after the copper wiring 101 is formed.
  • the through hole 100 is filled with a conductive material by paste printing or the like.
  • the solder material may be melted and poured.
  • a thin film wiring layer 2 composed of a wiring 120 and an interlayer insulating layer 110 such as a polyimide or polybenzobutene is formed, and each interlayer insulating layer 110 (a thin film wiring layer) is formed. 2) needs to be thick enough to ensure wiring insulation between layers and between lines. In the present invention, it is generally in the range of about 5 to 50 m, but more preferably about 10 to 20 ⁇ m.
  • the interlayer insulating layer 110 is made of a high heat resistant resin.
  • the diameter of the opening of the through hole 100 is small, and on the side (primary side), two thin film wiring layers 2 are formed.
  • One thin-film wiring layer 2 is formed on the side (secondary side) where the diameter of the opening of 100 is large.
  • the number of the thin film wiring layers 2 formed on both surfaces of the insulating substrate 1 is arbitrary, and can be freely set according to the design of the semiconductor module.
  • the thin film wiring layers 2 may be formed one by one and laminated. That is, a wiring pattern is formed on the insulating substrate 1, and then the interlayer insulating layer 110 is formed. At this time, if a wiring is formed by a semi-additive plating process using a photolithography technique, high-density wiring can be achieved. Also, the wiring may be formed using a method such as screen printing. Then, a wiring pattern is formed on the interlayer insulating layer 110 formed as necessary, and a re-formed interlayer insulating layer 110 is formed. ⁇
  • the insulating substrate 1 is a glass substrate or a silicon substrate, has a smoother property than the ceramic substrate, has a smaller thermal expansion coefficient, and has a thermal expansion coefficient close to that of the semiconductor device 9. Therefore, a fine wiring pattern can be formed on the substrate.
  • the wiring pitch on a glass substrate is about 2 to 200 ⁇ . If the wiring pitch exceeds 200 micrometer, the number of layers cannot be reduced effectively. If the wiring pitch is less than 2 micrometers, the electrical resistance of the wiring will increase.
  • the coefficient of thermal expansion of the glass substrate used in this example is about 5 pp mZ ° C, while the coefficient of thermal expansion of the interlayer insulating layer 110 made of a resin such as polyimide / polybenzocyclobutene is several 10 ppm. / ° C, thermal stress is generated due to the difference in thermal expansion coefficient.
  • the interlayer insulating layer 110 is manufactured without considering the relative ratio of the thickness of the glass substrate 1 to the thickness of the interlayer insulating layer 110, the multilayer wiring board 6 will be warped or bent due to the density of the wiring pattern.
  • the relationship between the thickness of the glass substrate and the thickness of the interlayer insulating layer 110 is adjusted so as to be about 30 to 50 times the thickness. Can be kept small.
  • the coefficient of thermal expansion is smaller than that of polyimide-polybenzocyclobutene, which is advantageous from the viewpoint of suppressing substrate warpage.
  • a fine wiring pattern can be formed on the substrate. Further, since fine wiring can be formed on a glass or silicon substrate, the number of thin film wiring layers 2 on the insulating substrate 1 can be reduced as compared with a conventional ceramic substrate, and the multilayer wiring substrate can be thinned.
  • the wiring (first wiring) formed immediately above the insulating substrate 1 exchanges signals between the user substrate and the semiconductor device 9.
  • the second wiring formed on the first interlayer insulating layer is the power supply line or the duland line
  • the third wiring formed on the second interlayer insulating layer is the semiconductor wiring. It may be formed as a signal line for exchanging signals between the body devices 9 (LSI).
  • the multilayer wiring layer 3 into at least a two-layer structure, three wiring layers can be formed, and signal lines between the semiconductor device 9 and the user substrate 10 and signals between the semiconductor devices 9 are formed. Wiring, power supply wiring and ground wiring can be separated, high-speed and fine wiring patterns can be formed, and it is also effective in preventing signal noise and the like. Needless to say, due to restrictions on wiring patterns, it is not necessary to form all of the wiring for exchanging signals between the semiconductor devices 9 (LSI) on the second interlayer insulating layer. It suffices that the number of wirings for exchanging signals between the devices 9 (LSIs) be larger on the outermost surface of the multilayer wiring board than on other wiring layers.
  • a power line or a ground line is formed in the wiring (first wiring) formed immediately above the insulating substrate 1, and the second wiring formed on the first interlayer insulating layer 110 is formed. If the signal wiring for exchanging signals between the user board and the semiconductor device 9 and the signal lines for exchanging signals between the semiconductor devices 9 (LSI) are arranged together in the wiring, the multilayer wiring is formed.
  • Layer 3 can be a single layer.
  • the multilayer wiring layer 3 is a single layer, or whether two or more layers are required depends on the logic scale of the semiconductor device 9, its layout, required high-speed signal characteristics, and the like.
  • the role of wiring formed on each interlayer insulating layer is changed, it is effective to change the wiring width and wiring shape for each layer.
  • the stress relaxation layer 5 is formed on the secondary side of the board mounted on the user board.
  • the insulating substrate 1 is made of low-strength glass, its linear expansion coefficient is about 5 ppm / ° C, while the linear expansion coefficient of the semiconductor chip 9 is about 3 pp mZ ° C.
  • the linear expansion coefficient of the whole module is almost equal to the linear expansion coefficient of the glass substrate, and is about 5 ppmZ ° C. Therefore, thermal stress generated between the insulating substrate 1 and the semiconductor device 9 is small.
  • the linear expansion coefficient of the mounting substrate 10 on which the semiconductor module 100 About 10 to 20 ppm ⁇ C. In the case of the most common glass epoxy substrate, it is about 15 to 18 pp mZ. C. Therefore, the thermal stress generated between the semiconductor module 100 and the mounting substrate 10 is large.
  • the thick insulating layer 5 stress relieving layer
  • the thickness of the stress relaxation layer 5 is from about 1/10 to about 1/2 of the thickness of the insulating substrate 1, or the diagonal length of the insulating substrate. On the other hand, it is preferably about 1/300 to about 1/20.
  • the thickness of the insulating substrate 1 is about 100 ⁇ m to about 100 ⁇ m
  • the thickness of the stress relaxation layer 5 is preferably about 100 to 500 ⁇ m
  • the insulating substrate 1 When the thickness is about 300 micrometers to about 500 micrometers, it is about 30 to 250 micrometers. The thickness and physical properties of the stress relaxation layer will be described later.
  • the stress relieving layer 5 is formed on the insulating substrate 1 or by screen printing using a mask, but a spray coating / dispense, a force render / co-photolithography technique or the like may be used.
  • the stress relaxation layer when mask printing (screen printing) is performed on the stress relaxation layer 5, the stress relaxation layer can be formed at a desired position. Also, an inclined portion can be formed at the end of the stress relaxation layer. Depending on the material of the stress relaxation layer, etc., it is possible to prevent the inclined portion from being formed, and it is also possible to control the angle of the inclined portion.
  • the stress relieving layer is formed by stamping
  • an insulating material for stress relieving is applied to a stamping die, and the shape of the insulating material is cured to transfer the shape of the stress relieving layer onto the substrate. It is possible to select an insulating material that does not change. In this case, there is a feature that the shape of the end portion is more likely to be constant than in the printing method.
  • the spray coating and the dispensing method do not use a print mask or a stamping mold
  • the shape at the time of forming the stress relaxation layer has a degree of freedom, and if the nozzle shape is selected appropriately, the print mask and stamping mold do not It is possible to form a stress relaxation layer that is difficult to form.
  • the thickness of the stress relaxation layer can be adjusted by adjusting the spray amount, and the range of the thickness adjustment can be widened. The method of attaching a semi-cured or uncured resin sheet allows the formation of a thick film stress relaxation layer and uses a sheet-like insulating resin in advance, so the surface of the stress relaxation layer has excellent flatness. .
  • the stress relaxation layer may be formed by combining these methods instead of using these methods alone.
  • a through hole 100 is also formed in the stress relaxation layer 5.
  • This through hole 100 is formed by not only sand blasting but also laser processing or photo etching.
  • the stress relaxation layer 5 is formed in a place where the through hole is not formed in the wiring board, and the surface of the stress relaxation layer is formed. (Including inclined surfaces) to form wiring.
  • screen printing in which printing is performed using a metal mask or the like, is effective.
  • the stress relieving layer 5 is not an essential component of the multilayer wiring board 6, and the stress relieving layer 5 may be formed on the multilayer wiring board 6 as long as the thermal stress generated by the semiconductor module 100 and the user board 10 is within an allowable range. There is no need to form 5.
  • thermal stress occurs between the semiconductor module 100 and the user substrate 100, reliability may be ensured by using an underfill instead of the stress relaxation layer 5.
  • an underfill may be used if the user desires higher reliability.
  • the material of the interlayer insulating layer 110 is used.
  • the linear expansion coefficient can be changed in the thickness direction of the multilayer wiring board 6. That is, on the primary side of the insulating substrate 1, an inter-layer insulating layer is formed of a material having a small coefficient of linear expansion to approximate the coefficient of linear expansion of the semiconductor device to be mounted.
  • an interlayer insulating layer is formed of a material having a large coefficient of linear expansion so that the coefficient of linear expansion approaches the substrate on which it is mounted.
  • the thin film wiring layers 2 are formed one by one and laminated, it is possible to easily change the linear expansion coefficient of the thin film wiring layers as necessary. it can.
  • the thermal stress between the semiconductor device 9 and the mounting substrate 10 can be reduced by the multi-layer wiring substrate without specially providing the stress relaxation layer 5, and the connection reliability can be ensured.
  • the insulating substrate 1, which is the core substrate of the multilayer wiring board is not limited to a glass or silicon substrate, but may be a conventional ceramic substrate or a metal core substrate. Is also good.
  • the through holes may be formed not only by sandblasting but also by laser processing or photolithographic etching.
  • a multilayer wiring board having no insulating substrate 1 and laminated thin film wiring layers having different linear expansion coefficients may be used.
  • the multilayer wiring board can reduce the thermal stress between the semiconductor device 9 and the mounting board 10 to secure the connection reliability. Since the thickness of the insulating substrate 1 can be omitted, a thinner and multilayer wiring substrate can be realized. Therefore, by using such a multilayer wiring board, a thinner electronic device can be realized.
  • a semiconductor chip such as LSI is mounted on the primary side of the multilayer wiring board 6.
  • the semiconductor device 9 may be a semiconductor device such as a semiconductor chip, a BGA, a CSP, a wafer-level CSP, or a lead-type semiconductor device such as a QFP or a TSOP. Further, the semiconductor device 9 itself may have a layer for relaxing a stress generated between the semiconductor device and a substrate on which the semiconductor device is mounted.
  • an insulating layer 50 (underfill layer) may be filled between the semiconductor device 9 and the substrate on which the semiconductor device 9 is mounted.
  • the semiconductor chips 9 to be mounted are not limited to the same type, and for example, a plurality of different types of semiconductor chips may be mounted on the multilayer wiring board 6 as shown in FIG.
  • A may be a microcomputer
  • B may be a flash memory
  • C may be a DRAM
  • D may be a combination of individual components such as capacitors.
  • FIG. 11 shows a cross section a—a ′ of FIG.
  • semiconductor packages such as QFPCSP and passive parts such as resistors and capacitors It may contain one or more products. It is desirable that the semiconductor chips, semiconductor packages, and passive components used here are of the surface mount type. If different types of semiconductor chips are mounted on the multilayer wiring board 6, the wiring required to connect the different semiconductor chips is made in the uppermost layer of the multilayer wiring layer 3, and the lower wiring layer is ground wiring or The signal wiring is formed. Furthermore, only the wires that need to be finally electrically connected to the user board may be connected through the through holes 100 of the insulating board 1.
  • the combination of different semiconductor chips includes DRAM and microcomputer, DRAM and microcomputer and DSP, DRAM and microcomputer and ROM, DRAM and flash memory, DRAM and SRAM and flash memory, ASIC and DRAM. and so on.
  • a combination of a microcomputer with a built-in flash, an ASIC, and a DRAM is used.
  • a microcomputer and flash memory, a microcomputer with built-in flash and DRAM, or a combination of microcomputer, flash memory and DRAM are suitable. Flash memory is used to reduce power consumption, but if flash memory alone does not have enough memory capacity, use a highly integrated DRAM. Chips may be stacked as needed.
  • Mobile terminals for example, mobile phones use the same configuration as digital still cameras, but mobile phones require lower power consumption than digital still cameras. Often set equal to or greater than capacity! / ,.
  • the semiconductor element 9 (semiconductor chip) and the multilayer wiring board 6 are connected by external connection terminals such as bumps 300.
  • the semiconductor element 9 having the bump 300 is mounted on the multilayer wiring board 6 and connected by reflow.
  • bumps 300 may be formed on the multilayer wiring board 6.
  • bare chip semiconductor element that is not packaged
  • the bump 300 may be made of a wire such as gold formed into a convex shape by an ultrasonic bonding device, or a metal such as tin, lead, copper, silver, bismuth, zinc, and indium, alone or in combination of two or more.
  • the mixed alloy can be used as the solder bump 300 Wear.
  • a resin containing a conductive material such as silver or gold can be used as the bump 300.
  • Solder bumps 300 are prepared by mixing fine particles of solder with a material such as rosin, printing them on the electrodes of a semiconductor device using an appropriate mask, and then heating the solder to a temperature higher than the melting temperature of the solder. It can also be formed by melting.
  • the paste-like resin material is printed on an electrode of a semiconductor device using an appropriate mask, and is cured or semi-cured by heating. Bump formation is also possible by a method. Furthermore, an oxide film on the surface of the electrode is removed, a flux having an appropriate tackiness is applied on the electrode, and a solder pole having an appropriate particle size is aligned on the electrode using a mask or the like, and the solder is removed by a reflow oven or the like. Bumps can also be formed by heating above the melting temperature. Of course, these can also be applied to the formation of the external connection terminal 7.
  • the electrodes provided on the semiconductor device 9 to be connected to the bumps 300 are made of aluminum or copper electrodes formed in a process called a pre-process, or after the pre-process, and further from the electrodes such as wafer level CSP, copper is applied to the surface of the semiconductor device. It is possible to use an electrode formed after rewiring is performed using such wiring. By performing a surface treatment such as nickel and gold on the surface of the electrode, the wettability between the bump and the electrode surface is improved, and the bump material remains in the electrode during a heating step such as mounting a semiconductor module on an external substrate, which will be described later. The diffusion can prevent a decrease in bonding strength between the bump and the electrode portion.
  • the solder is a so-called lead-free solder such as Sn—Zn, Sn—Ag, or Sn—Ag—Cu, for example, Sn—3.0.
  • OA g—0.5 Cu may be used.
  • solder bump since lead-free solder is harder than conventionally used lead solder, it is difficult to reduce thermal stress generated between the semiconductor device 9 and the multilayer wiring board 6 by the solder bump.
  • the semiconductor device 9 and the multilayer wiring substrate 6 can be used. Connection reliability can be ensured.
  • the physical property values of the interlayer insulating layer for example, the coefficient of thermal expansion and the elastic coefficient are changed in the thickness direction of the multilayer wiring board. Specifically, the interlayer insulating layer on the outermost surface on the primary side and the multilayer wiring board By reducing the thermal stress generated by approaching the coefficient of thermal expansion of the semiconductor chip 9 mounted on the board 6 and reducing the generated thermal stress, even when lead-free solder is used, the Connection reliability can be ensured.
  • the melting point of the solder bump used for the connection on the primary side must be higher than that of the solder on the secondary side when the solder is used for the connection on the secondary side. In other words, on the primary side and the secondary side, it is necessary to change the temperature of the solder connection and establish a temperature hierarchy.
  • An external connection terminal 7 is formed on the secondary side of the multilayer wiring board 6 to establish connection with the user board 10.
  • the external connection terminal 7 may be made of a resin or the like containing conductive particles in addition to the solder hole, similarly to the bump 300. Depending on the connection method with the external board, it can be used without forming balls or terminals.
  • solder bumps are formed as external connection terminals 7, the distance between adjacent bumps (bump pitch) is about 500 ⁇ m to 800 im, but the pitch of the connection terminals on the user board is inevitable. Is restricted to. In general, as the connection terminal pitch becomes narrower, the price of the user board increases, so the connection pitch is determined in consideration of the cost of the entire module.
  • a typical connection pitch is about 500 to 800 mm as described above, but there are cases where the connection pitch exceeds 100 mm.
  • the diameter of the solder bump 7 is appropriately selected according to the bump pitch, but the diameter of the solder bump is at most about 0% of the bump pitch.
  • ⁇ 3 such as Sn—Zn system, Sn—Ag system, or Sn—Ag—Cu system, and free solder, for example, Sn— 3.
  • OA g-0.5 Cu may be used.
  • lead-free solder is harder than conventional lead solder, so when using lead-free solder, the thermal stress generated between the multi-chip module and the mounting board 1 It is difficult to ease yourself.
  • a stress relaxation layer is provided, By changing the coefficient of thermal expansion of the interlayer insulating layer in the thickness direction of the multilayer wiring board to relieve the stress, even when lead-free solder is used, the multi-chip module and the mounting board 10 Connection reliability can be ensured.
  • the multilayer wiring board 6 in the present embodiment not only plays a role as an interposer of the semiconductor chip but also occurs between the semiconductor device 9 (semiconductor chip, LSI, etc.) and the multilayer wiring board 6 and the mounting board 10. Relieve thermal stress. Furthermore, if the thermal stress generated between the semiconductor module 100 and the user substrate 100 can be reduced by means such as a stress relaxation layer, the semiconductor module 100 may be mounted on the user substrate 100. Need not be filled with underfill.
  • an underfill may be formed between the semiconductor module and the mounting board 10 (user board).
  • the resin used as the underfill may be epoxy resin, phenol resin, silicone resin, etc.
  • a filler such as silicon dioxide and aluminum aluminum oxide, a coupling agent, a coloring agent, a flame retardant, and the like may be added to a mixture of two or more kinds as necessary.
  • a glass substrate or a silicon substrate having a through hole is used as a semiconductor module
  • wiring can be formed at a high density on an insulating substrate. Therefore, since the number of thin film wiring layers can be reduced, the multilayer wiring board can be formed thin, and the semiconductor module can be reduced in thickness and size.
  • the fact that the number of thin film wiring layers 2 is small means that the wiring length from the semiconductor chip 9 such as LSI to the user substrate 10 becomes shorter, so that higher-speed signals can be exchanged.
  • the multi-chip module has a mechanism to relieve stress, it is possible to omit the underfill when mounting this multi-chip module on the user's board, and to reduce the work of the user who manufactures the electronic device. Can also be reduced.
  • a thick insulating layer serving as a stress relieving layer is formed on a glass or silicon substrate serving as an insulating substrate, and a through hole is formed in the insulating layer by sand plasting.
  • the multilayer wiring substrate 6 can be manufactured in a wafer state, or the substrate can be manufactured in a square thin plate shape.
  • FIG. 28 shows a state in which a large number of pieces are taken using a glass substrate or a silicon substrate 301.
  • a plurality of module circuits are formed on a glass substrate or a silicon substrate, and predetermined semiconductor devices 9 (semiconductor chips), resistors, capacitors, etc. are mounted, and solder balls as external connection terminals are mounted. Accordingly, the space between the semiconductor device and the substrate is filled with resin. Thereafter, each module portion can be cut out individually by a method similar to the dicing of a silicon wafer to obtain a desired semiconductor device. In the following, for the sake of simplicity, description will be made using a part of the structure of the multilayer wiring board.
  • FIG. 13 is a flowchart illustrating the manufacturing method according to the present embodiment.
  • the process for forming the external connection terminals (secondary bumps 7) on the secondary side of the multilayer wiring board is the method of manufacturing the multilayer wiring board.
  • the secondary side bump does not necessarily have to be formed.
  • FIG. 14, FIG. 15, and FIG. 16 are process diagrams illustrating a method for manufacturing a multilayer wiring board according to the present invention.
  • a glass substrate or a silicon substrate is prepared as the insulating substrate 1 used for the wiring substrate. If necessary, perform surface treatment and cleaning of the front and end surfaces. Appropriate edge surface treatment can reduce manufacturing defects.
  • Figs. 14, 15, and 16 show that in the case of a silicon substrate, the insulating film formed on the surface is integrated into an insulating substrate. Board 1 is displayed.
  • a wiring 120 is formed on the surface of the insulating substrate 1.
  • a semi-additive method can be used.
  • the wiring material is preferably Cu, Al, Ag, and Au from the viewpoint of conductivity, but Cu is desirable in consideration of corrosiveness, migration resistance, and price. Since Cu is a ductile material, it can be used as a mask for sandblasting.
  • an interlayer insulating layer 110 is formed on the wiring pattern.
  • the thickness of the interlayer insulating layer 110 is generally in the range of about 5 to 50 m, but is more preferably about 10 to 20 ⁇ m.
  • a polyamide resin, a polyimide resin, a polybenzocyclobutene resin, a polybenzoxazole resin, or the like can be used as the interlayer insulating layer 110.
  • the thin film wiring layers 2 are formed one by one on the insulating substrate 1, the number and thickness of the thin film wiring layers can be changed as necessary.
  • the thickness of the wiring layer and the thickness and material of the interlayer insulating material by utilizing the formation of each layer one by one. For example, by using materials having different dielectric properties for the insulating material A of the insulating layer between the ground layer and the signal layer and the insulating material B between the lines of the signal layer, the ground layer and the signal layer and the signal layer can be connected to each other. It is possible to adjust the strength of the electrical coupling of the wiring, and it is possible to respond to high-speed wiring. Also, by changing the material of each interlayer insulating layer, the coefficient of linear expansion can be changed in the thickness direction of the substrate.
  • Fig. 14b two wiring layers are formed on the surface (primary side) of the insulating substrate 1 on which the semiconductor chip is mounted, and 1 layer is formed on the surface (secondary side) on which the semiconductor module is mounted.
  • the wiring forming method may be different between the primary side and the secondary side of the insulating substrate.
  • the secondary side of the insulating board is connected to the mounting board (user board), so wiring with a narrower pitch than the primary side is not required. Therefore, for example, the photolithography
  • the secondary side wiring may be formed by printing due to the adhesion.
  • Fig. 17 and Fig. 35 show the wiring pattern on the secondary side on the insulating substrate 1.
  • c Of the pads shown in Fig. 17 and Fig. The barrel portion is indicated by oblique lines.
  • the pad in advance so as to surround the position where the through hole 100 is formed, it is possible to reduce the occurrence of microcracks on the surface of the insulating substrate 1 by sandblasting. The strength of the insulating substrate can be maintained.
  • a thick insulating layer 5 is formed on the surface (secondary side) of the insulating substrate 1 on which the semiconductor module is mounted on the user substrate by stencil printing / photolithography or the like.
  • the insulating layer 5 plays a role of a stress relaxation layer, and can relieve a thermal stress caused by a difference in linear expansion coefficient between the semiconductor module and the mounting substrate 10.
  • a method such as laser trimming after screen printing using a stencil mask.
  • through-holes 100 connecting the wiring layers on both surfaces of the insulating substrate 1 are formed by the steps shown in FIGS. 15A and 15B.
  • the material (hardness) of the stress relaxation layer 5 and the insulating substrate 1 are different, and it is difficult to form a through hole 100 in the stress relaxation layer 5 by sand blast. Therefore, a hole (dent) is formed in the stress relaxation layer 5 by laser processing or the like, and then a through hole 100 is formed in the insulating substrate 1 by sand blast.
  • the following is a typical example of a method for forming a mask for forming the through hole 100 in the multilayer arrangement and the substrate 6.
  • the first method is a method using a photolithography technique. Specifically, a blast resist serving as a mask during sandblasting is formed on the stress relaxation layer, and the blast resist and the stress relaxation layer are opened by photolithography. This opened blast resist becomes a mask for forming a through hole in the stress relaxation layer by the sand plast. In this method, both the blast resist and the stress relieving layer can be simultaneously opened. However, both the blast resist and the stress relieving layer must be photosensitive materials.
  • the second method is a method using laser processing.
  • a blast resist is formed on the stress relaxation layer, and the blast resist and the stress relaxation layer are formed.
  • the sum layer is collectively opened by laser processing.
  • the second method can be used irrespective of the photosensitivity of the blast resist and the stress relaxation layer. Further, since the plast resist used in the second method does not necessarily need resolution characteristics, a material having more excellent blast resistance than the first method can be selected.
  • a photosensitive blast resist is formed on the stress relaxation layer, and an opening pattern is formed in the blast resist by photolithography.
  • the stress relaxation layer is etched through the opening of the plast resist to form a hole (dent) in the stress / relaxation layer 5.
  • the blast resist needs to have heat resistance and sand plast resistance.
  • (1) apply a photosensitive resin having sand blast resistance to the thin film wiring layer 2, or (2) A method in which a photosensitive resin having sandplast resistance in the form of a dry film is attached to the photosensitive resin.
  • the mask pattern can be formed by screen printing depending on the opening diameter of the through holes, the hole pitch, and the positional accuracy. In such a case, if necessary, fine adjustment of the positional accuracy and the processing accuracy can be performed by additional processing using a photolithographic laser.
  • the shape shown in FIG. 15A is obtained by the above-described first to third methods. At this time, the formed recessed portion may reach the insulating substrate 1, but does not necessarily have to reach.
  • the conditions for forming the through-holes 100 must be appropriately selected according to the characteristics of the substrate material, particularly the elastic modulus and rupture toughness of the substrate, but when the specific gravity is 2.0 to 10.0, the bulk material is bent. It is desirable to use processed granules having a strength of 0.1 to 2. OGP a! The processing speed tends to increase as the grain size of the processed grains increases, but on the contrary, the problem of crack opening cracking and chipping described later tends to occur.
  • the particle size (#) of the processing powder is determined in consideration of the substrate material, the processing size (thickness, diameter) of the through hole, the desired processing speed, and the like. It is desirable to be within the range. In this embodiment, # 500, # 600, # 700, # 800, Any of # 900, # 10000, # 1100, # 1200, or a combination thereof was used as appropriate. Although the processed powder is circulated and reused, it collides with each other and shatters during use. Therefore, it is advisable to appropriately size the powder so that the particle size is maintained in the above range. In addition, crushed powder from the through-hole portion of the substrate is also mixed in. If necessary, this is removed.
  • the sandblasting machine used for forming the through-holes in the present embodiment has a circulation / reuse mechanism and a spheroid mechanism. It is practical to use a sandplast machine that is set up so that the recycle and spheroids are automatically operated in parallel with the processing of through holes.
  • resin processing residue may remain on the surface of the insulating substrate 1, but the resin processing residue may be removed during the sandblasting performed on the insulating substrate 1. Is done. Normally, when holes are formed in a resin by laser processing, resin residues (smears) that cause a reduction in wiring connection reliability are formed, and a process of desmearing by chemical treatment or the like is required. In the manufacturing process of the present embodiment, since the dent portion formed by the laser processing is sandblasted, the smear can be removed at the sandblasting stage, and there is no need to perform a chemical desmear process.
  • the through hole 100 is formed by sand plast, the diameter of the through hole 100 is formed to be different from one opening end to the other opening end. With this, the power supply film is easily formed on the inner surface of the through hole 100 by a film forming method such as sputtering and electroless plating.
  • the sandblast penetrates the insulating substrate 1 Later, it is possible to prevent the primary-side interlayer insulating layer 110 (thin film layer, second layer 2) from being cut by sandblasting.
  • the mask is removed by etching or the like.
  • microcracks generated around the through hole 100 of the insulating substrate 1 in the process of forming the through hole 100 are removed.
  • micro cracks generated in the insulating substrate 1 are roughly classified into two types, so-called median cracks and lateral cracks.
  • Median crack Cracks are cracks extending in the depth direction with respect to the side wall surface of the through hole, while lateral cracks extend in the creepage direction with respect to the side wall surface of the through hole.
  • the rate of occurrence of lateral cracks and median cracks is (1) hardness of processed grains, (2) shape of processed grains, (3) grain size of processed grains, (4) processed grains. It depends on the number of times the object collides with the workpiece in a unit time, (5) the angle at which the processed particles collide with the workpiece, and (6) the pressure of the gas transporting the processed particles. . Therefore, it is preferable to use a plast machine having a nozzle capable of adjusting the number of collisions per unit time, the collision angle, the pressure of the carrier gas, and the like. By selecting an appropriate blasting machine and processing conditions, both processing efficiency and substrate strength can be achieved.
  • the cracks in the microphone opening can be removed.
  • a method for heating the periphery of the through hole include a method such as laser annealing.
  • the entire glass substrate is heated and the mouth cracks are self-fused and then cooled slowly, Since the strain accumulated in the substrate is released, the failure rate due to substrate cracking can be reduced.
  • wiring is performed on the inner wall surface of the through hole 100 and the outermost surface of the multilayer wiring board. Is formed.
  • a power supply film is formed on the inner wall of the through hole 100 by a method such as sputtering CVD or vapor deposition.
  • a method such as sputtering CVD or vapor deposition.
  • the power supply film for example, a multilayer film of chromium Z copper is preferable, but any known and commonly used film configuration as a plating power supply film such as a titanium / copper multilayer film may be used.
  • the function of chromium is to ensure adhesion between the substrate and copper, and its film thickness is about 75 nanometers, and at most about 0.5 micrometer.
  • the thickness of the copper of the power supply film is about 0.5 ⁇ m, up to 1 ⁇ m.
  • FIG. 2 shows the state before the formation of the inter-wiring insulating film (inter-wiring insulating film) on the outermost surface of the substrate.
  • the second method uses a subtractive method for forming wiring.
  • the same method as in the first method up to the point where a multilayer film made of chromium / copper etc. is formed by sputtering as the wiring force.After that, plating is performed on the entire surface, and then etching resist is formed on the front and back of the insulating substrate. An etching mask pattern is formed by a lithography technique. After wiring is formed by etching, the resist is removed and an inter-line insulating film is formed.
  • the inside of the through hole is filled with a conductive material. For example, paste printing or the like is used for filling the conductive material.
  • a sputter film Prior to filling the conductive material, a sputter film may be formed on the inner wall of the through hole in the same manner as in the above two methods. Forming a sputtered film on the inner wall surface has the following effects: (1) improving the filling property by improving the smoothness of the inner wall surface; and (2) improving the adhesion between the filler and the insulating substrate.
  • the sputter film to be formed should have a large amount of copper / copper as in the first and second methods. It may be a layer film or a single layer film. If solder is used as the conductive material, laminate a film of chromium or titanium to ensure adhesion to the insulating substrate and a film of copper, nickel, or gold to ensure solder wettability. Desirably, it is a membrane. After filling the conductive material inside the through-hole, wiring is formed on the substrate surface by the semi-additive method or the subtractive method. Note that, depending on the wiring pattern, filling of the through-holes and formation of the wiring pattern may be achieved in a batch by paste printing.
  • a conductive wiring of a through hole connecting the front and back of the substrate and a wiring on the substrate surface (secondary side) are formed.
  • the wiring on the substrate surface is laminated in a required number of layers, but is preferably copper wiring from the viewpoint of electric resistance. If necessary, a heterogeneous metal may be formed on the copper surface from the viewpoint of adhesion reliability, insulation reliability, and the like.
  • the insulating substrate 1 is a glass substrate, since glass is a material having an insulating property, there is no problem if wiring or the like is formed so as to directly contact the inner wall of the through-hole. From the viewpoints of migration resistance, moisture resistance, and the like, an insulating layer may be formed so as to cover the surface of the inner wall surface of the through hole.
  • the insulating substrate 1 is a silicon substrate, since the silicon has conductivity, the inner wall surface of the through-hole should be covered before forming the wiring for connecting the front and back of the wiring substrate 1. It is necessary to provide an insulating layer on the surface.
  • the multilayer wiring board 6 having the through holes 100 can be formed.
  • the multilayer wiring board may be shipped in a state in which multiple boards can be obtained, or the multilayer wiring board may be diced and individually shipped.
  • dicing may be performed after mounting a semiconductor chip or the like to form a multi-chip module.
  • a semiconductor module 9 is formed by mounting a semiconductor device 9 and a capacitor on a multilayer wiring board 6 using an external connection terminal 300 such as a solder pump or the like and an anisotropic conductive sheet (ACF). .
  • external connection terminal 300 such as a solder pump or the like and an anisotropic conductive sheet (ACF).
  • ACF anisotropic conductive sheet
  • solder bars for secondary connection
  • solder bumps are formed on the primary side of the wiring board in accordance with the external terminal pitch of the semiconductor device 9.
  • the bump pitch is generally in the range of about 50 to 500 ⁇ .
  • the bump size is adjusted to be about 15 to 80%, preferably about 30 to 65% with respect to the bump pitch.
  • the semiconductor device 9 is mounted on the multilayer wiring board 6 using the formed primary bumps.
  • the pitch of the primary side bumps is about 50 to 500 ⁇ m.
  • an underfill agent is filled between the wiring substrate 6 and the semiconductor device 9 or potting is performed on the upper portion of the semiconductor device 9.
  • a material may be applied. If the bump size is as small as 200 micrometers or less, the mechanical strength may decrease due to the reduction in the volume of the bump. In this case, the underfill agent and the potting material must be used alone. Or, if used in combination, problems such as reduced reliability will not occur.
  • bumps 7 (secondary side bumps) for mounting the semiconductor module on the mounting board 10 are formed.
  • the wiring of the semiconductor device 9 is electrically connected to the primary-side bump 7, and a fine pitch is realized by the multilayer wiring board 6.
  • the bump 7 (secondary bump) for mounting the semiconductor module on the mounting substrate 10 is formed after the formation of the primary bump.
  • the primary side bump may be formed after the secondary side bump is formed.
  • the melting point of the solder bump 7 (secondary side bump) becomes When the melting point is lower than the melting point of the bump, perform the secondary connection after the primary connection. That is, after forming the solder bumps 300 and mounting the semiconductor chip 9, it is preferable to form the solder bumps 7 and mount the semiconductor module on the mounting board 10.
  • FIG. 3 although two semiconductor devices 9 are shown, the number of the semiconductor devices 9 is arbitrary, and a plurality of semiconductor devices 9 (semiconductor chips and the like) are mounted on the multilayer wiring board 6 to form a so-called multi-chip It goes without saying that modules can be formed.
  • the through-holes 100 are opened by the sandplast, it is not necessary to use a high-cost photosensitive glass as a substrate material.
  • a multilayer wiring board can be manufactured.
  • FIG. 18 is a flowchart illustrating the manufacturing method according to the present embodiment.
  • the main difference from the first embodiment is the order of the process of forming the through holes 100 in the insulating substrate 1.
  • a glass substrate or a silicon substrate is prepared as the insulating substrate 1 used for the wiring substrate, and if necessary, the surface and the end surface are subjected to surface conditioning treatment, cleaning treatment, and surface insulation treatment. I'll do it.
  • through holes 100 are formed only in the insulating substrate 1 by sandblasting as in the first embodiment. Due to this sand blast, microcracks are generated on the insulating substrate 1.
  • microcracks generated on the insulating substrate 1 are removed by the same method as in the first embodiment.
  • a hole 120 is formed on the through-hole 100 of the insulating substrate 1 and the insulating substrate 1. Similar to the first embodiment, the wiring can be formed by using a semi-additive method or a subtractive method.
  • a power supply film is formed on the inner surface of the through hole 100 and the three surfaces of the front and back surfaces (the primary surface and the secondary surface) of the insulating substrate 1.
  • the power supply film may be formed from both sides of the substrate at the same time, or may be formed on the primary surface and the secondary surface one by one. From the viewpoint of simultaneous formation on three surfaces, the electroless plating method is more efficient.
  • the power supply film is formed by sputtering, the film is formed on the front and back of the substrate, especially when the power supply film is formed on the secondary surface.
  • the formation of the power supply film on the inner wall of the through hole can be achieved.
  • the power supply film include a chromium film and a multilayer film of copper as in the first embodiment. There are the following two methods for forming wiring after forming the power supply film.
  • the first is a semi-additive process.
  • a resist is formed on the front and back surfaces (primary and secondary surfaces) of the insulating substrate 1, and a resist pattern that is the reverse pattern of the desired plating wiring is formed by photolithography technology, and then the wiring is formed by plating To form
  • the inner wall of the through-hole 100 and the front and back of the substrate can be collectively plated.
  • the pattern separation process as usual, the pattern can be separated at a stroke between the wiring on the inner wall of the through hole and the wiring on the front and back of the substrate.
  • the wiring material include Cu, Al, Ag, Au, and Ni.
  • the second method is a subtractive process.
  • the inner wall of the through-hole 100 and the front and back surfaces of the substrate can be collectively plated.
  • An etching resist is formed on the plating film, and a resist pattern serving as a reverse pattern of a desired distribution is formed by a photolithography technique. Thereafter, the wiring is separated by etching.
  • the wiring material is Cu, A1, Ag, Au, Ni, etc., as in the first method.
  • the through-hole 100 is filled with a filler.
  • the filler need not necessarily be a conductive material, but may be an insulating material. It is desirable that the material has a high filling property that can be filled by a simple filling method such as paste printing. If it is not possible to fill the through hole 100 with one printing, it is necessary to print several times.
  • Figure 21 shows an unfilled part (hereinafter referred to as unfilled void 200) in the center of through-hole 100 when paste printing was performed 5 times to fill through-hole 100. This shows the appearance.
  • unfilled void 200 an unfilled part in the center of through-hole 100 when paste printing was performed 5 times to fill through-hole 100.
  • the inside of the void is changed. Since the expansion and contraction of air occurs, The wire may be easily broken, or the strain may accumulate inside the insulating substrate, and the strength of the insulating substrate 1 may be reduced.
  • unfilled voids 200 are formed in the first printing process, a part of the pressure on the paste will escape in the form of void compression during the second and subsequent printing, resulting in insufficient printing pressure. As a result, complete filling is not possible. Since the pressure loss is large near the primary end face of the insulating substrate 1 where the diameter of the opening is small, if the printing pressure is insufficient, an unfilled portion 201 may be formed near the primary end face. .
  • an interlayer insulating film such as polyimide / polybenzobutene or a line insulating film above the through hole including the unfilled void 200. This is because the void expands when heated in the process of curing the insulating film, and under the influence, the insulating layer present on the substrate surface and being cured is deformed.
  • Another solution is to apply a conductive material or the like to the hollow of the unfilled portion 201 generated near the primary end face before forming the wiring on the insulating substrate 1. By doing so, even if there is an unfilled portion 201, the surface on the insulating substrate 1 becomes flat. What is necessary is just to use silver paste etc. as a conductive material, and to print this in the hollow of the unfilled part 201.
  • a multilayer wiring layer 3 composed of a thin film wiring layer 2 having a wiring 120 and an interlayer insulating layer 110 is placed on an insulating substrate 1 filled with through holes 100.
  • the wiring forming process itself is essentially the same as in the first embodiment.
  • a stress relaxation layer 5 is formed as necessary, and a hole (via hole) is formed in the stress relaxation layer 5 by photo-etching or laser processing.
  • the process of forming the stress relaxation layer 5 is essentially the same as that of the first embodiment.
  • wiring is formed on the holes of the formed multilayer wiring layer 3 and the stress relaxation layer 5 and on the surface thereof to complete the multilayer wiring board 6.
  • the steps from the bump formation to the module formation after the completion of the multilayer wiring board 6 are essentially the same as those in the first embodiment.
  • the insulating substrate 1 is filled with the insulating substance, the strength of the insulating substrate 1 and the multilayer wiring board 6 is increased as compared with the case where the through holes 100 are not filled.
  • the wiring formation on the inner wall of the through hole 100 and the front and back surfaces of the substrate can be processed at one time, the number of steps of exposure, development, and plating can be greatly reduced.
  • a glass substrate or a silicon substrate is prepared as the insulating substrate 1 used for the wiring substrate, and if necessary, the surface or the end surface is trimmed, the surface is cleaned, and the surface is insulated. I have done.
  • FIG. 22A through holes 100 are formed in the insulating substrate 1 by sandblasting. Subsequently, microcracks generated on the insulating substrate 1 are removed. Subsequently, as shown in FIG. 22B, wiring is formed on the through hole 100 of the insulating substrate 1 and the insulating substrate 1. Wiring can be formed using the semi-additive method, the subtractive method, or the like in the same manner as in the first and second embodiments.
  • the front and back surfaces of the through hole 100 inner surface insulating substrate 1 (primary surface, secondary surface) The same as in Example 2 in that a power supply film is formed on the three surfaces.
  • the difference between the second embodiment and this embodiment is that the order of filling the through hole 100 of the insulating substrate 1 with an insulating substance and forming the interlayer insulating layer 110 (thin film wiring layer 2) on the insulating substrate 1 is different. It is in.
  • Example 2 the primary side end of the through hole 100 was left open when the wiring on the substrate surface was formed, and the inside of the through hole was filled in that state.
  • the opening end on the primary side of the insulating substrate 1 is closed by wiring. If the diameter of the through-hole is small, increasing the thickness of the plating allows the narrower end of the through-hole (primary opening) to be covered with the coating. Piercing After closing the through hole opening end, the multilayer wiring layer 3 is formed.
  • the through hole 100 whose primary side opening end is closed is filled.
  • the filling may be performed by paste printing of an insulating substance, or the filling of a conductive material may be performed.
  • a stress relaxation layer 5 is formed if necessary, and holes are formed in the stress and relaxation layer 5 by photoetching or laser calorie.
  • wiring is formed on the holes and on the surfaces of the formed multilayer wiring layer 3 and stress relaxation layer 5 in FIG. 23B to complete the multilayer wiring board 6.
  • the insulating hole 1 Since the wiring on the secondary side on the insulating substrate 1 closes the opening of the through hole 100, after forming the multi-layer wiring layer 3, the insulating hole 1 The substance can be filled. As a result, it is possible to effectively suppress the formation of the unfilled portion 201 near the primary end face of the insulating substrate 1. As a result, the flatness of the interlayer insulating layer formed in the next step can be ensured, and it becomes easier to form wiring with high density.
  • FIG. 6 shows an enlarged photograph of a through hole formed in a substrate by using sandblasting.
  • FIG. 24 shows a schematic diagram of the force.
  • the back side (primary side) of the side on which the sand is blown by the sandblasting of the insulating substrate (hereinafter, secondary side) is opened.
  • the hole has a constricted shape at the tip. That is, assuming that the secondary side opening diameter is dl, the primary side opening diameter is d3, and immediately before the primary side opening diameter is d2, dl>d3> d2.
  • this constricted shape has a size of only a few micrometers at the processing tip, but considering that the thickness of the power supply film is less than 1 micrometer, The concave shape of several micrometers has a great effect on the formation of the feed film.
  • the formation of the power supply film on the inner surface of the through-hole is likely to be insufficient by a method such as sputtering CVD or vapor deposition. Therefore, it becomes difficult to form a copper wiring by plating at that location.
  • Cr, Ti, and the like which are formed by sputtering in order to ensure the adhesion between the substrate and the wiring, tend to hardly wrap around.
  • a malleable metal such as copper
  • even a sputtered film can go around a few micrometers, but the adhesion film such as Cr, which should be originally formed underneath, is not precisely formed. Insufficient wiring adhesion is likely to occur.
  • the constriction at the tip of the opening is due to a median crack formed during sand blasting, as indicated by the fact that it is formed in the depth direction with respect to the wall surface of the through hole.
  • a first method there is a method in which after forming a through-hole, the substrate is polished or ground to a thickness where the constricted shape is formed, and the constricted shape is removed to flatten the substrate.
  • CMP chemical mechanical polishing
  • a third method as shown in Fig. 25, another member is applied to the primary side of the substrate, or a film or the like is attached to the primary side substrate, and after the through hole reaches the substrate, the member is used. Or there is a method of removing the film.
  • the member to be applied or adhered to the secondary side of the substrate is desirably a material having a bending elastic modulus equal to or higher than that of the insulating substrate 1, but is not limited thereto. It is also desirable that the primary side be in close contact with no gap.
  • a reinforcing film may be provided on the secondary surface of the insulating substrate 1 by using sputtering or the like.
  • the member to be applied may be, for example, wiring formed on a substrate.
  • sputtering is performed on the through-holes of the substrate while the constricted shape remains, by sputtering from both the primary side and the secondary side of the substrate.
  • chromium is sputtered from the secondary direction of the substrate, then the substrate is turned over, chromium is sputtered from the primary direction, and then copper is There is a method in which the substrate is turned over once again and copper is sputtered from the secondary direction of the substrate.
  • the power supply film (Cu / Cr) can be uniformly formed inside the through hole without removing the constricted shape of the substrate.
  • a highly reliable metal wiring can be formed in a through hole formed by sandblasting.
  • the above five methods are effective when plating wiring is applied to a through-hole formed by sandblasting.
  • the substrate on which the through-hole is formed is not limited to a glass or silicon substrate. Material, for example ceramic substrate This is also effective when plating wiring is formed in the through hole formed in the substrate.
  • the thickness of the stress relaxation layer 5 depends on the size of the semiconductor module, the elastic modulus of the stress relaxation layer 5, the thickness and the diagonal length of the insulating substrate 1, and cannot be unambiguously determined.
  • an acceptable stress relaxation layer 5 was obtained. It has been found that the film thickness range is preferably from 10 to 500 micrometers, more preferably from 30 to 250 micrometers. This corresponds to a thickness of about 1/10 to 1/2 of the thickness of the insulating substrate 1.
  • the film thickness is less than 30 micrometers, the desired stress relaxation cannot be obtained, and if the film thickness exceeds 250 micrometers, the internal stress of the stress relaxation layer 5 itself is reduced. As a result, the insulating substrate 1 may be warped and the substrate may be damaged, or the wiring may be disconnected.
  • the stress relaxation layer 5 is formed of a resin material having an elastic coefficient significantly smaller than that of the insulating substrate 1, for example, from 0.1 GPa to 10 GPa at room temperature. If the stress relaxation layer 5 has an elastic coefficient in this range, a reliable multilayer wiring board 6 can be provided. That is, in the case of the stress relaxation layer 5 having an elastic coefficient of less than 0.1 GPa, it is difficult to support the weight of the insulating substrate 1 itself, and the characteristics are not stable when used as the semiconductor module 100. Problems are easy to occur. On the other hand, if the stress relaxation layer 5 having an elastic modulus exceeding 10 GPa is used, the insulation substrate 1 may be warped due to the internal stress of the stress relaxation layer 5 5 itself, and the insulation substrate 1 may be broken. is there.
  • the material for forming the stress relaxation layer 5 used here is a paste-like polyimide, but is not necessarily limited to this.
  • the paste-like polyimide is composed of a polyimide precursor, a solvent, and a large number of polyimide fine particles dispersed therein.
  • the fine particles Specifically, fine particles having an average particle size of 1 to 2 micrometer and having a particle size distribution with a maximum particle size of about 10 micrometer were used. Since the polyimide precursor used in this example becomes the same material as the polyimide microparticles when cured, when the paste-like polyimide hardens, a uniform stress relaxation made of one type of material occurs.
  • the sum layer 5 is formed.
  • polyimide was used as the material for forming the stress relaxation layer 5, but in this embodiment, in addition to polyimide, amide imide resin, ester imide resin, ether imide resin, silicone resin, acrylic resin, polyester resin, and these are modified. It is also possible to use a resin which has been used. When a resin other than polyimide is used, a treatment for imparting compatibility to the surface of the polyimide microparticles described above, or a modification of the resin composition so as to improve the affinity with the polyimide microparticles should be performed. Is desirable.
  • resins having an imide bond such as polyimide, amide imide, ester imide, and ether imide
  • thermomechanical properties such as high-temperature strength
  • thermomechanical properties such as high-temperature strength
  • Silicone resin Polyacrylic resin, polyester resin, amide imide, ester imid, ether imide, etc.Resin with a portion condensed by a bond other than imide bond is slightly inferior in thermo-mechanical properties but advantageous in terms of processability and resin price
  • polyesterimide resin is generally easier to handle because it has a lower curing temperature than polyimide.
  • the material for forming the stress relaxation layer 5 is, for example, a resin such as epoxy, phenol, polyimide, or silicone, alone or in combination of two or more resins. And the like can be blended and used. In the present embodiment, these resins are appropriately used in consideration of price, thermo-mechanical properties, and the like from among these resins.
  • the thixotropic properties of the paste can be controlled by adjusting the composition of the fine particles. Can be improved.
  • the thixotropy characteristic of the paste suitable in the examples of the present application is a so-called thixotropy index obtained from the ratio of the viscosity at a rotation speed of 1 rpm and the viscosity at a rotation speed of 10 rpm measured using a rotational viscometer. Is preferably in the range of 10.0 to 10.0. In the case of a paste in which the thixotropy index has a temperature dependency, high performance can be obtained by printing in a temperature region where the thixotropy index is in the range of 1.0 to 10.0.
  • a predetermined film thickness can be obtained by repeating printing and curing of the material a plurality of times. For example, if a metal mask with a thickness of 65 ⁇ m is used using a paste with a solid concentration of 30 to 40%, it is possible to obtain a film thickness of about 50 ⁇ m after curing by two printings. I can do it.
  • the material for the stress relaxation layer 5 it is desirable to use a material having a curing temperature of 100 ° C. to 250 ° C. for the material for the stress relaxation layer 5. If the curing temperature is lower than this, it is difficult to control within the semiconductor module manufacturing process, and if the curing temperature is higher than this, there is a concern that the stress of the isolated substrate 1 will increase due to heat shrinkage during curing and cooling. .
  • the glass transition temperature (T g) of the heat resistance is preferably more than 150 ° C. and not more than 400 ° C. or less, more preferably T g is more than 180 ° C. Preferably, T g is 200 ° C. or higher.
  • Figure 27 shows the experimental results showing the relationship between the glass transition temperature (T g) and the coefficient of linear expansion. From this, it can be seen that cracks did not occur when the glass transition temperature (T g) was 200 ° C. or higher.
  • the preferred linear expansion coefficient of the stress relaxation layer 5 material in this embodiment is in the range of 3 ppm / ° C to 300 ppmZ ° C. It is desirable. More preferably, it is in the range of 3 ppmZ ° C to 200 ppmZ ° C, and the most desirable linear expansion coefficient is in the range of 3 ppmZ ° C to 150 ppm / ° C.
  • the coefficient of linear expansion When the coefficient of linear expansion is large, it is desirable that the above-mentioned elastic coefficient is small. More specifically, the bullet It is recommended that the value of the product of the coefficient of thermal expansion (GPa) and the coefficient of linear expansion (ppm / ° C) be within a specific range.
  • the desirable range of this value varies depending on the size, thickness, and mounting form of the substrate, but generally, it is desirable that this value is generally in the range of 50 to 100,000.
  • the thermal decomposition temperature (T d) is desirably about 300 ° C. or higher, and more desirably, 350 ° C. or higher. If the Tg or Td is below these values, there is a risk that the resin will be deformed, deteriorated or decomposed during a thermal process in the process, for example, a sputter / sputter etch process. From the viewpoint of chemical resistance, it is desirable that resin aging such as discoloration and deformation does not occur when immersed in a 30% aqueous sulfuric acid solution or a 10% aqueous sodium hydroxide solution for 24 hours or more.
  • the solubility parameter (SP value) is desirably 5 to 30 (cal / cm3) 1Z2.
  • the material for the stress relaxation layer 5 is a material obtained by modifying some components to the base resin, it is desirable that most of the composition fall within the range of the solubility parameter. More specifically, it is desirable that a component having a solubility parameter (SP value) of less than 5 or more than 30 does not exceed 50% by weight.
  • the wiring board mainly made of glass and silicon, the multilayer wiring board using the same, and the multichip module using the same have been described in detail.
  • a wiring board and a method of manufacturing the wiring board according to the present invention are controlled by using a displacement sensor or the like to control the position and orientation of a moving object by detecting acceleration or angular velocity and a method of manufacturing the same. The case where the method is used will be described.
  • FIG. 30a the surface of the device wafer 400 is etched.
  • the device wafer 400 which has been etched onto a first substrate for protecting the device wafer 400, for example, a glass substrate, is joined (Ob in FIG. 3).
  • the device wafer 400 is re-etched to form devices such as fine vibration elements. (Figure 30c).
  • a second substrate 420 such as a glass substrate supporting the device wafer 400 is etched to form a concave portion (FIG. 30d). Subsequently, the device wafer on which the vibrating element and the like are formed and the second substrate 420 are joined (FIG. 30e).
  • a through-hole 430 is formed in the first substrate 410 by sand blast (FIG. 30f).
  • a through hole is formed in the first substrate, a depression (hole) may be formed at a position of the first substrate to be diced in a later individualization step.
  • the surface of the first substrate 410 and the through holes (contact holes) of the first substrate 410 are formed.
  • a conductor metal as shown in Fig. 30g is deposited and patterned inside the 400 to form wiring.
  • microsensor micro gyro
  • Fig. 3 Oh the microsensor formed on the second glass substrate 420 is diced and individualized. This completes the package for the microphone port sensor.
  • the wiring on the inner wall surface of the through hole may be formed before bonding to the device wafer, and the package substrate on which the wiring pattern is formed may be bonded to the device wafer.
  • the wiring on the inner wall surface of the through-hole may be formed by sputtering from both sides of the substrate as described in the above embodiment.
  • a constricted portion may be formed at the opening end of the through-hole as described above. Therefore, the package substrate is polished after the through-hole is formed.
  • Well is ,.
  • a layer for reducing thermal stress may be provided.
  • the micro gyro can be made smaller.
  • the through-hole is formed by sandblasting, the adhesion between the metal material forming the wiring and the package substrate is increased due to minute unevenness in the through-hole, and a short circuit or the like can be prevented. Also the book In the embodiment, short-circuiting of the wiring and the like can be prevented by removing the constricted portion of the through-hole which is not formed or the formed constricted portion by polishing.
  • the first and second it is possible to maintain a vacuum state in the cavity where the vibrating element is located between the substrate and the device wafer.
  • displacement sensors and inertial sensors are used in vehicle stability control systems, automotive systems, napige systems, camera shake prevention for cameras and small video cameras, etc. Used as a sensor required for
  • the present invention has been specifically described based on the embodiments.
  • the present invention is not limited to the embodiments, and various changes can be made without departing from the gist of the present invention.
  • a wiring board having high reliability and capable of high-density wiring can be manufactured.

Abstract

A multilayer wiring board (6) manufactured at low cost comprises an insulating sheet(1) having a through hole (100) and a thin-film wiring layer (2) formed on the insulating sheet. The board has a high reliability, and a high-density wiring can be provided on the board. A through hole is made in a glass sheet (1) by sand blasting, a wiring pattern (120) and an interlayer insulating layer (110) are formed on the glass sheet, and the through hole is filled with a plating wiring or a conductive material (101), thus fabricating a multilayer wiring board.

Description

明 細 書 配線基板およぴその製造方法 技術分野  Description Wiring board and its manufacturing method
本発明は、 配線基板およびその製造方法に関する。  The present invention relates to a wiring board and a method for manufacturing the same.
従来技術 Conventional technology
従来、 貫通孔を有する多層配線基板としては、 セラミック配線基板が広く利用 されていた。 すなわち、 セラミック原料粉末をバインダーである有機樹脂で結合 したセラミック生シート （以下、 グリーンシートと称することもある） に貫通孔 を加工した後、 導体ペーストを用いてスクリーン印刷法で配線パターンを形成す るとともに、 各シートの配線パターンを接続する貫通孔にも導体ペーストを充填 する。 そして、 配線パターンを形成したグリーンシートを所定枚数積み重ねて積 層圧着した後、 焼成してセラミック配線基板を作成していた。  Conventionally, ceramic wiring boards have been widely used as multilayer wiring boards having through holes. That is, after forming through holes in a ceramic green sheet (hereinafter sometimes referred to as a green sheet) in which ceramic raw material powders are bound with an organic resin as a binder, a wiring pattern is formed by screen printing using a conductive paste. At the same time, the conductive paste is filled into the through holes connecting the wiring patterns on each sheet. Then, a predetermined number of green sheets on which a wiring pattern is formed are stacked, pressure-bonded, and fired to produce a ceramic wiring board.
し力 し、 上記セラミック配線基板は、 その製造時において焼成および冷却とい う工程を経る。 この際にグリーンシートおょぴ導体ペーストからバインダーが脱 離しながら積層圧着されるが、 それらの変形率が異なるため、 微細な配線パター ンでは配線の変形が生じやすいという問題があった。 また、 圧着終了後に焼結温 度から冷却するが、 その過程でもセラミック基材と配線材がそれぞれ熱変形を起 こすため、 基板全体の熱変形を計算することは困難であった。  However, the ceramic wiring board undergoes firing and cooling steps during its manufacture. At this time, the binder is delaminated and pressed while removing the binder from the green sheet and the conductive paste. However, since their deformation rates are different, there is a problem that the wiring is likely to be deformed in a fine wiring pattern. In addition, the ceramic substrate and the wiring material also undergo thermal deformation in the process of cooling from the sintering temperature after the completion of the compression bonding, so that it was difficult to calculate the thermal deformation of the entire substrate.
また、 熱変形を予想すべく所定の計算を行う場合には、 配線パターンを変更す る毎に計算が必要となる。 配線パターンが微細化に伴って計算の精度が要求され るため、 熱変形を計算するための物性値の測定も高精度が要求されると共に、 そ の計算を実行するのに膨大な時間を要し、 1 0 0マイクロメータを下回るような 配線パターンを形成することは必ずしも実用的であるとは言えなかった。  In addition, when performing a predetermined calculation to predict thermal deformation, the calculation is required every time the wiring pattern is changed. Since the accuracy of calculation is required as wiring patterns become finer, the measurement of physical properties for calculating thermal deformation also requires high accuracy, and it takes enormous time to execute the calculation. However, it has not always been practical to form a wiring pattern that is less than 100 micrometers.
また、 セラミック基板は焼成時においてバインダーが揮発するため、 セラミツ ク基板の表面は凸凹となり、 そのままでは微細な配線パターンを形成することは 困難であった。  In addition, since the binder volatilizes during firing of the ceramic substrate, the surface of the ceramic substrate becomes uneven, and it is difficult to form a fine wiring pattern as it is.
一方、 コア基板を有する多層配線基板として、 ガラス基板またはシリコン基板 も考えられていたが、 ガラス基板またはシリコン基板は基板が脆弱で、 貫通孔を 有する多層配線基板としてはあまり用いられていなかった。 On the other hand, as a multilayer wiring substrate having a core substrate, a glass substrate or a silicon substrate However, glass substrates or silicon substrates are not widely used as multilayer wiring substrates with through holes because the substrates are fragile.
特願平 8— 5 2 7 4 8 9 (国際公開番号 WO/ 9 7 / 0 3 4 6 0 ) には、 半導 体チップを実装するガラス基板が開示されている。 し力 し、 ガラス基板は一方の 面に半導体チップを搭載するものであり、 ガラス基板の両面に絶縁層と導体層か らなる配線層を形成するものではない。  Japanese Patent Application No. Hei 8-5-274989 (International Publication No. WO / 97/0334600) discloses a glass substrate on which a semiconductor chip is mounted. However, the glass substrate has a semiconductor chip mounted on one surface, and does not have a wiring layer composed of an insulating layer and a conductor layer formed on both surfaces of the glass substrate.
特開平 1 0— 2 4 2 2 0 6には、 露光 .現像プロセスを用いて、 感光性ガラス に貫通孔を形成した基板が開示されている。 この基板は、 ベアチップを搭載時に、 パーンィン時の検査基板としての機能と、 プリント回路基板等の基板に接続する ためのインタポーザ （ベアチップと外部端子との間をつなぐ材料） としての機能 とを兼ね備えることを目的とするものであるが、 コァ基板の上に絶縁層と導体層 からなる配線層が多層に形成されたものではない。 また、 貫通孔をサンドブラス トによって形成することは開示されていない。  Japanese Patent Application Laid-Open No. H10-224206 discloses a substrate in which a through hole is formed in a photosensitive glass using an exposure and development process. This board, when a bare chip is mounted, has both a function as an inspection board at the time of panning and a function as an interposer (material connecting the bare chip and external terminals) for connection to a board such as a printed circuit board. However, this does not mean that a wiring layer composed of an insulating layer and a conductor layer is formed in multiple layers on a core substrate. Further, it is not disclosed that the through holes are formed by sandblasting.
特開平 1 1— 2 4 3 2 6 7には、 貫通孔を有する絶縁基板の上に配線が形成さ れた配線基板が開示されている。 この絶縁基板は、 ガラスセラミックス焼結体等 のセラミック焼結体によつて形成されており、 例えばセラミックグリーンシート (セラミック生シート) を形成した後、 前記セラミックグリーンシートに適当な 打ち抜き加工を施し、 所定形状となすとともに高温で焼成することによつて製作 されることが開示されている。 また、 絶縁基板の表面、 および貫通孔の内壁面に 断線しにくい配線を形成するために、 例えば貫通孔の径は基板の中心から両開口 端に向って、 順次広くなつている。 該貫通孔の形成方法としては、 三角形状のド リルやレーザ加工法等が開示されている。 し力 し、 絶縁基板はガラスセラミック であり、 ガラス基板ではなく、 また絶縁基板の上に絶縁層と導体層からなる配線 層が多層に形成されたものではない。  Japanese Patent Application Laid-Open No. H11-2443267 discloses a wiring board in which wiring is formed on an insulating substrate having a through hole. The insulating substrate is formed by a ceramic sintered body such as a glass ceramic sintered body. For example, after forming a ceramic green sheet (ceramic green sheet), the ceramic green sheet is subjected to an appropriate punching process. It is disclosed that it is manufactured by forming a predetermined shape and firing at a high temperature. Further, in order to form wiring that is hard to be disconnected on the surface of the insulating substrate and the inner wall surface of the through hole, for example, the diameter of the through hole is gradually increased from the center of the substrate toward both ends of the opening. As a method of forming the through hole, a triangular drill, a laser processing method, and the like are disclosed. However, the insulating substrate is a glass ceramic, is not a glass substrate, and does not have a multilayer wiring layer composed of an insulating layer and a conductor layer formed on the insulating substrate.
本発明の目的は、 高密度配線可能な配線基板を低コストに提供することである。 また、 本発明の他の目的は、 貫通孔を有する基板と、 その基板の表面に形成さ れた薄膜配線層とを有する多層配線基板において、 信頼性が高く、 高密度配線可 能な配線基板を低コストに提供することである。  An object of the present invention is to provide a low-cost wiring board capable of high-density wiring. Another object of the present invention is to provide a multi-layer wiring board having a substrate having a through hole and a thin film wiring layer formed on the surface of the substrate, the wiring board having high reliability and capable of high-density wiring. At low cost.
我々は、 これまでの研究開発により、 高密度配線可能な配線基板を低コストに 提供するためには、 表面平滑で熱膨張係数の小さなガラス基板を用いた配線基板 の構成おょぴその製造プロセスを工夫することが重要であることを明らカにした。 また、 その配線基板を用いた電子装置、 例えばマルチチップモジュールの接続 信頼性を向上させるには、 多層配線基板に応力を緩和する機構を持たせることが 重要であることを明らかにした。 We have achieved a low-cost wiring board capable of high-density wiring through our research and development. In order to provide this, it has been clarified that it is important to devise the structure of the wiring board using a glass substrate with a smooth surface and a small thermal expansion coefficient, and to devise the manufacturing process. In addition, it has been clarified that it is important to provide a multilayer wiring board with a mechanism to reduce stress in order to improve the connection reliability of an electronic device using the wiring board, for example, a multichip module.
上記目的を達成するために、 本願において開示される発明のうち、 代表的なも のの概要を簡単に説明すれば、 次の通りである。  The following is a brief description of an outline of typical inventions among the inventions disclosed in the present application to achieve the above object.
発明の開示 Disclosure of the invention
ガラス基板と、 該ガラス基板の上に形成された配線おょぴ絶縁層を含む多層配 線層とを有する配線基板であって、 該ガラス基板は該ガラス基板の両面で電気的 接続を取るための孔を有し、 該孔はサンドプラストにより形成されたものである。 貫通孔を備えた第一の基板と、 該第一の基板の一方の面に形成された第一の配 線おょぴ第一の絶縁層を有する第一の配線層と、 該第一の基板の他方の面に形成 された第二の配線おょぴ第二の絶縁層を有する第二の配線層とを有する配線基板 であって、 該第一の絶縁層と該第二の絶縁層の熱膨張係数が異なるものである。 貫通孔を備え、 かつ熱膨張係数が約 3 p p mZ°Cから約 5 p p mZ°Cである第 一の基板と、 該孔の開口端の径が小さレ、方の該第一の基板の面に形成された第一 の配線およぴ第一の絶縁層を有する第一の配線層と、 該孔の開口端の径が大きレヽ 方の該第一の基板の面に形成された第二の配線および第二の絶縁層を有する第二 の配線層と、 該第二の配線層の表面であって、 力っ該第一の基板の反対側に形成 された第三の絶縁層を有する配線基板であって、 該第三の絶縁層は該配線基板と 該配線基板が実装される実装基板の間に生じる熱応力を緩和するものである。 配線基板の製造方法であって、 ガラス基板の上に導体層およぴ絶縁層を有する 配線層を多層に形成する工程と、 該ガラス基板の一方の面に形成された配線層に 第一の孔を形成する工程と、 該第一の孔が形成された位置から該ガラス基板にサ ンドプラストを行って、 該ガラス基板に第二の孔を形成する工程と、 該第二の孔 の内壁面および該配線層の最表面に配線を形成する工程を有するものである。 配線基板の製造方法であって、 サンドプラストによりガラス基板に孔を形成す る工程と、 該ガラス基板の少なくとも一方の面、 およぴ該孔の内壁面に配線を形 成する工程と、 該ガラス基板おょぴ該ガラス基板の上に形成された酉己線の上に、 絶縁層および導体層を含む多層配線層を形成する工程を有するものである。 本発明の他の目的、 特徴及ぴ利点は添付図面に関する以下の本発明の実施例の 記載から明らかになるであろう。 A wiring substrate having a glass substrate and a multilayer wiring layer including a wiring and an insulating layer formed on the glass substrate, wherein the glass substrate is used for making electrical connection on both surfaces of the glass substrate. And the hole is formed by sandplast. A first substrate having a through hole; a first wiring formed on one surface of the first substrate; a first wiring layer having a first insulating layer; A wiring board having a second wiring formed on the other surface of the substrate and a second wiring layer having a second insulating layer, wherein the first insulating layer and the second insulating layer Have different coefficients of thermal expansion. A first substrate having a through hole and having a coefficient of thermal expansion of about 3 pp mZ ° C to about 5 pp mZ ° C; and a first substrate having a smaller diameter at the opening end of the hole. A first wiring layer having a first wiring and a first insulating layer formed on the surface; and a first wiring layer formed on the surface of the first substrate having a larger diameter at the opening end of the hole. A second wiring layer having a second wiring and a second insulating layer; and a third insulating layer formed on the surface of the second wiring layer and opposite to the first substrate. Wherein the third insulating layer relieves thermal stress generated between the wiring substrate and a mounting substrate on which the wiring substrate is mounted. A method for manufacturing a wiring board, comprising: a step of forming a wiring layer having a conductor layer and an insulating layer on a glass substrate in multiple layers; and a first step of forming a wiring layer formed on one surface of the glass substrate. Forming a hole, performing a sand blast on the glass substrate from a position where the first hole is formed, forming a second hole in the glass substrate, and an inner wall surface of the second hole. And forming a wiring on the outermost surface of the wiring layer. A method for manufacturing a wiring board, comprising: forming a hole in a glass substrate by sand plast; forming a wiring on at least one surface of the glass substrate and an inner wall surface of the hole. And a step of forming a multilayer wiring layer including an insulating layer and a conductor layer on the glass substrate and a roto wire formed on the glass substrate. Other objects, features and advantages of the present invention will become apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
図面の簡単な説明 BRIEF DESCRIPTION OF THE FIGURES
図 1は、 貫通孔を有する絶縁基板に配線を形成した配線基板の断面図である。 図 2は、 本発明に係る配線基板の一実施例を示す図である。  FIG. 1 is a cross-sectional view of a wiring board in which wiring is formed on an insulating substrate having a through hole. FIG. 2 is a diagram showing one embodiment of the wiring board according to the present invention.
図 3は、 本発明に係る配線基板を有するマルチチップモジュールの一実施例を 示す図である、 - 図 4は、 半導体モジュールを実装基板に実装した様子を示す図である。  FIG. 3 is a view showing one embodiment of a multi-chip module having a wiring board according to the present invention. FIG. 4 is a view showing a state where a semiconductor module is mounted on a mounting board.
図 5は、 本発明に係る半導体モジュールの一実施例を示す斜視図である。 図 6は、 ガラス基板にサンドプラストとフォトエッチングによって形成した貫 通孔を示す写真である。  FIG. 5 is a perspective view showing one embodiment of the semiconductor module according to the present invention. Figure 6 is a photograph showing through holes formed in a glass substrate by sand plasting and photoetching.
図 7は、 本発明に係る配線基板の一実施例を示す図である。  FIG. 7 is a diagram showing one embodiment of the wiring board according to the present invention.
図 8は、 本発明に係る配線基板を有するマルチチップモジュールを実装基板に 実装した様子を示す図である。  FIG. 8 is a diagram showing a state in which a multichip module having a wiring board according to the present invention is mounted on a mounting board.
図 9は、 本発明に係る配線基板の一実施例を示す図である。  FIG. 9 is a diagram showing one embodiment of a wiring board according to the present invention.
図 1 0は、 本発明に係る配線基板を有するマルチチップモジュールを実装基板 に実装した様子を示す図である。  FIG. 10 is a diagram showing a state in which a multichip module having a wiring board according to the present invention is mounted on a mounting board.
図 1 1は、 本発明に係る配線基板を有するマノレチチップモジュ一ルのー実施例 を示す図である。  FIG. 11 is a view showing an embodiment of a manoret chip module having a wiring board according to the present invention.
図 1 2は、 多層配線基板に実装される半導体チップの組合せの一例を示す図で ある。  FIG. 12 is a diagram showing an example of a combination of semiconductor chips mounted on a multilayer wiring board.
図 1 3は、 本発明に係る配線基板の製造工程のフローチャート図である。 図 1 4 a， 1 4 b及ぴ 1 4 cは、 本発明に係る配線基板の製造工程の一例を示 す図である。  FIG. 13 is a flowchart of the manufacturing process of the wiring board according to the present invention. FIGS. 14a, 14b and 14c are views showing an example of the manufacturing process of the wiring board according to the present invention.
図 1 5 a及び 1 5 bは、 本発明に係る配線基板の製造工程の一例を示す図であ る。  FIGS. 15a and 15b are views showing an example of the manufacturing process of the wiring board according to the present invention.
図 1 6は、 本発明に係る配線基板の製造工程の一例を示す図である。 図 1 7は、 配線とサンドブラストによる粒子があたる位置の関係を示す図であ る。 FIG. 16 is a diagram illustrating an example of a manufacturing process of the wiring board according to the present invention. FIG. 17 is a diagram showing the relationship between the wiring and the position at which particles by sandblasting strike.
図 1 8は、 本発明に係る配線基板の製造工程のフローチヤ一ト図である。 図 1 9， 1 9 b及び 1 9 cは、 本発明に係る配線基板の製造工程の一例を示す 図である。  FIG. 18 is a flowchart of the manufacturing process of the wiring board according to the present invention. FIGS. 19, 19b, and 19c are views showing an example of the manufacturing process of the wiring board according to the present invention.
図 20 a， 20 b及 20 cは、 本発明に係る配線基板の製造工程の一例を示す 図である。  20a, 20b and 20c are views showing an example of the manufacturing process of the wiring board according to the present invention.
図 2 1は、 貫通孔を充填したときに、 未充填の部分が形成された様子を示す写 真である。  FIG. 21 is a photograph showing a state where an unfilled portion is formed when the through hole is filled.
図 22 a， 22 b及ぴ 22 cは、 本発明に係る配線基板の製造工程の一例を示 す図である。  22a, 22b and 22c are views showing an example of the manufacturing process of the wiring board according to the present invention.
図 23 a及び 23 bは、 本発明に係る配線基板の製造工程の一例を示す図であ る。  FIGS. 23a and 23b are views showing an example of the manufacturing process of the wiring board according to the present invention.
図 24は、 サンドプラストにより基板に形成した貫通孔の模式図である。 図 2 5は、 サンドプラストにより部材をあてがった絶縁基板に形成した貫通孔 を示す図である。  FIG. 24 is a schematic view of a through hole formed in a substrate by sand plast. FIG. 25 is a diagram showing through-holes formed in an insulating substrate to which members are applied by sandplast.
図 26 a， 26 b, 26 c及び 26 dは、 基板の貫通孔へ配線を形成する方法 を示す図である。  FIGS. 26a, 26b, 26c and 26d are diagrams showing a method of forming a wiring in a through hole of a substrate.
図 2 7は、 ガラス転移温度 (Tg) と線膨張係数の関係を示す実験結果の図で ある。  FIG. 27 is a diagram of an experimental result showing the relationship between the glass transition temperature (Tg) and the coefficient of linear expansion.
図 28は、 ガラス基板やセラミック基板を用いて配線基板を多数個取りする状 態を示す図である。 ·  FIG. 28 is a diagram illustrating a state in which a large number of wiring substrates are formed using a glass substrate or a ceramic substrate. ·
図 2 9は、 本発明に係る配線基板の一実施例を示す図である。  FIG. 29 is a diagram showing one embodiment of the wiring board according to the present invention.
図 3 0 a， 30 b， 30 c， 30 d, 30 e， 30 f , 3 0 8及び3 1 11は、 ジャイロスコープの製造方法を示す図である。  FIGS. 30a, 30b, 30c, 30d, 30e, 30f, 308 and 311 are diagrams showing a method for manufacturing a gyroscope.
図 3 1 a， 3 1 b, 3 1 c， 3 1 d及び 3 1 eは、 サンドプラスト法により基 板に貫通孔を形成する様子を示す図である。  Figures 31a, 31b, 31c, 31d, and 31e are views showing the formation of through holes in the substrate by the sand-plast method.
図 3 2は、 本発明に係る配線基板の一実施例を示す図である。  FIG. 32 is a diagram showing one embodiment of the wiring board according to the present invention.
図 3 3は、 本発明に係る配線基板の一実施例を示す図である。 図 3 4は、 本発明に係る配線基板の一実施例を示す図である。 FIG. 33 is a view showing one embodiment of the wiring board according to the present invention. FIG. 34 is a diagram showing one embodiment of the wiring board according to the present invention.
図 3 5は、 配線とサンドブラストによる粒子があたる位置の関係を示す図であ る。  FIG. 35 is a diagram showing the relationship between the wiring and the position at which particles by sandblasting strike.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の配線基板およびそれをコア基板に用いた多層配線基板について、 図を参照しながら実施の形態とともに詳細に説明する。 なお、 実施の形態を説明 するための全図において、 同一の機能を有するものは同一符号を付け、 その繰り 返しの説明は省略する。  Hereinafter, a wiring board of the present invention and a multilayer wiring board using the same as a core board will be described in detail with reference to the drawings and embodiments. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the description thereof will not be repeated.
図 1は、 貫通孔 1 0 0を有する基板 1 (コア基板 1 ) に配線 1 2 0を形成した 配線基板の一部分の断面図である。 図 2は貫通孔 1 0 0を有する基板 1と多層配 線層 3と応力緩和するための絶縁層 5 (応力緩和層 5 ) 等を有する多層配線基板 FIG. 1 is a cross-sectional view of a part of a wiring board in which a wiring 120 is formed on a substrate 1 (core substrate 1) having a through hole 100. FIG. 2 shows a multilayer wiring board having a substrate 1 having a through hole 100, a multilayer wiring layer 3, an insulating layer 5 for stress relaxation (stress relaxation layer 5), and the like.
6の一部分を示す断面図である。 図 3は、 多層配線基板を用いた電子装置として、 多層配線基板 6に半導体装置 9 (以下、 半導体素子、 半導体チップということも ある） 等を実装したマルチチップモジュールの一部分を示す断面図である。 なお、 図 3は図 1 2の a— a ' の断面図を示す。 図 4は、 そのマルチチップモジュール を実装基板 （ユーザ基板） 1 0に実装した様子を示す断面図である。 図 5は、 マ ルチチップモジュールの一例の斜視図である。 FIG. 6 is a sectional view showing a part of FIG. FIG. 3 is a cross-sectional view showing a part of a multi-chip module in which a semiconductor device 9 (hereinafter, also referred to as a semiconductor element or a semiconductor chip) or the like is mounted on a multilayer wiring board 6 as an electronic device using the multilayer wiring board. . FIG. 3 is a cross-sectional view taken along aa ′ of FIG. FIG. 4 is a cross-sectional view showing a state in which the multichip module is mounted on a mounting board (user board) 10. FIG. 5 is a perspective view of an example of the multichip module.
ここで、 多層配線層 3は複数の薄膜配線層 2からなり、 その薄膜配線層 2は配 線 1 2 0および層間絶縁層 1 1 0を有する。 なお、 配線 1 2 0はビア内の配線お ょぴ配線パッドを含む。 また、 応力緩和層 5は必ずしも必要なく、 必要に応じて 形成すればよい。 また、 図示していないが、 多層配線層 3および応力緩和層 5の 最表面の各配線の間に絶縁層を形成してもよい。  Here, the multilayer wiring layer 3 includes a plurality of thin film wiring layers 2, and the thin film wiring layer 2 has a wiring 120 and an interlayer insulating layer 110. The wiring 120 includes the wiring inside the via and the wiring pad. Further, the stress relaxation layer 5 is not always necessary, and may be formed as necessary. Although not shown, an insulating layer may be formed between the outermost wirings of the multilayer wiring layer 3 and the stress relaxation layer 5.
また、 多層配線基板 6そのものは、 外部接続端子、 例えばはんだバンプ 7を有 する基板であつてもいいし、 有しない状態の基板であつてもよい。  Further, the multilayer wiring substrate 6 itself may be a substrate having external connection terminals, for example, the solder bumps 7, or may be a substrate having no external connection terminals.
本実施例においては、 基板 1 (コア基板 1、 絶縁基板 1ということもある） は ガラス基板またはシリコン基板を用いる。 シリコンの素材そのものは導電性 （半 導体〜導体） であるため、 シリコン基板を絶縁基板 1として用いる場合には、 そ の表面に絶縁性の膜を形成する必要がある。  In this embodiment, a glass substrate or a silicon substrate is used as the substrate 1 (also referred to as a core substrate 1 or an insulating substrate 1). Since the silicon material itself is conductive (semiconductor to conductor), when a silicon substrate is used as the insulating substrate 1, it is necessary to form an insulating film on its surface.
ガラス基板またはシリコン基板は従来のセラミック基板に比べ平滑性が優れて いるため、 ガラス基板またはシリコン基板上では従来のセラミック基板上より微 細に配線パターンを形成することができる。 Glass or silicon substrates have better smoothness than conventional ceramic substrates Therefore, a finer wiring pattern can be formed on a glass substrate or a silicon substrate than on a conventional ceramic substrate.
また、 ガラス基板またはシリコン基板の熱膨張係数は約 3 p p m/°Cから約 5 p p m/°Cであり、 従来のセラミック基板と比べて基板の熱膨張が小さいため、 熱膨張による配線の短絡を防止でき、 微細な配線を形成することができる。  In addition, the thermal expansion coefficient of the glass or silicon substrate is about 3 ppm / ° C to about 5 ppm / ° C.Since the thermal expansion of the substrate is smaller than that of a conventional ceramic substrate, short-circuiting of wiring due to thermal expansion may occur. And fine wiring can be formed.
さらに、 ガラス基板またはシリコン基板の熱膨張係数は、 セラミック基板と比 ベて、 基板に実装される半導体素子 （半導体チップ） のシリコンに近いため、 ガ ラス基板またはシリコン基板と半導体装置の間では、 基板と半導体素子の熱膨張 係数の差から生じる応力が小さく、 多層配線基板と半導体装置の接続信頼性が向 上する。  Furthermore, the thermal expansion coefficient of a glass substrate or a silicon substrate is closer to that of the silicon of the semiconductor element (semiconductor chip) mounted on the substrate than the ceramic substrate, so that between the glass substrate or the silicon substrate and the semiconductor device, The stress generated due to the difference in thermal expansion coefficient between the substrate and the semiconductor element is small, and the connection reliability between the multilayer wiring substrate and the semiconductor device is improved.
絶縁基板 1としてシリコンを用いた場合には、 熱膨張係数が約 3 p p m/°Cで、 半導体素子 9と熱膨張係数がほぼ等しいため、 多層配線基板との間で熱応力が実 質的に生じない。  When silicon is used as the insulating substrate 1, the thermal expansion coefficient is about 3 ppm / ° C, and the thermal expansion coefficient is almost equal to that of the semiconductor element 9. Does not occur.
また、 シリコン基板は熱伝導性に優れているため、 製造プロセスにおける熱ェ 程での処理が均一になり、 高歩留まりを得やすレ、。 さらに、 配線板として使用す る場合には、 放熱特性の観点で有利である。  In addition, the silicon substrate has excellent thermal conductivity, so that the heat treatment in the manufacturing process is uniform and high yields can be obtained. Further, when used as a wiring board, it is advantageous from the viewpoint of heat radiation characteristics.
なお、 シリコンの素材そのものは導電性 （半導体〜導体） であるため、 シリコ ン基板を絶縁基板として用いる場合には、 その表面に絶縁性の膜を形成する必要 がある。 絶縁性の膜として、 水蒸気中で加熱することによって表面に形成できる 熱酸化膜や、 有機樹脂膜などがある。  Since the silicon material itself is conductive (semiconductor to conductor), when a silicon substrate is used as an insulating substrate, it is necessary to form an insulating film on the surface thereof. Examples of the insulating film include a thermal oxide film formed on the surface by heating in steam and an organic resin film.
絶縁基板 1としてガラスを用いた場合には、 シリコン基板に比べ、 熱膨張係数 は約 5 . 0と若干大きくなるが、 半導体装置と多層配線基板との間で生じる熱応 力は十分に小さい。  When glass is used as the insulating substrate 1, the thermal expansion coefficient is slightly larger than that of the silicon substrate, about 5.0, but the thermal stress generated between the semiconductor device and the multilayer wiring substrate is sufficiently small.
また、 シリコン基板に比べ、 材料の入手が容易で安価である。 さらに、 ガラス は絶縁性を有するため、 ガラス基板を絶縁基板として用いる場合には、 ガラス基 板表面やその貫通孔内表面に導線性物質を充填、 または配線をめつき等により形 成する場合に、 改めて絶縁膜を形成する必要が無く、 製造工程が簡略化できる。 なお、 本実施例に好適なガラスの組成としては、 ソーダガラス、 低アルカリガ ラス、 無アルカリガラス、 イオン強化ガラスなどがあるが、 弾性率や線膨脹係数 などを考慮して適宜選択する。 Also, compared to silicon substrates, materials are easily available and inexpensive. Furthermore, since glass has an insulating property, when a glass substrate is used as an insulating substrate, the surface of the glass substrate or the inner surface of the through hole is filled with a conductive substance, or the wiring is formed by plating or the like. There is no need to form an insulating film again, and the manufacturing process can be simplified. Examples of suitable glass compositions for this embodiment include soda glass, low alkali glass, non-alkali glass, and ion-strengthened glass. It is appropriately selected in consideration of the above.
半導体装置 9と多層配線基板 6の間の接続信頼性を向上させる観点では、 無ァ ルカリガラスや低アル力リガラスが好ましい。 アル力リイオン含有量が少ないガ ラスほど、 一般には線膨脹係数が小さくなるためである。 すなわち、 半導体装置 のシリコンの線膨張係数は約 3 p p mZ°Cと小さいため、 アル力リィオン含有量 が少ないガラスほど絶縁基板と半導体装置の線膨張係数が近くなり、 半導体装置 9と多層配線基板 6の間の熱応力が小さくなるからである。 ただし、 半導体装置 9と多層配線基板 6との間の接続信頼性は、 ガラス材質の特性だけではなく、 両 者の間の接続構造やアンダーフィル材の選択にも依存しているので、 それらをも 考慮してガラス材質を選択する。  From the viewpoint of improving the connection reliability between the semiconductor device 9 and the multilayer wiring board 6, alkali-free glass or low-strength glass is preferable. This is because a glass having a lower Li-ion content generally has a lower linear expansion coefficient. In other words, since the linear expansion coefficient of silicon in a semiconductor device is as small as about 3 pp mZ ° C, the glass having a lower Al-ion ratio has a closer linear expansion coefficient between the insulating substrate and the semiconductor device, and the semiconductor device 9 and the multilayer wiring substrate This is because the thermal stress during 6 becomes smaller. However, the connection reliability between the semiconductor device 9 and the multilayer wiring board 6 depends not only on the characteristics of the glass material but also on the connection structure between the two and the selection of the underfill material. The glass material is selected in consideration of the above.
一方、 半導体モジュール 1 0 0 0全体と実装基板 1 0との接続信頼性の観点で は、 アルカリ含有量の大きなソーダガラスが好ましい。 実装基板 1 0の線膨張係 数は 1 0から 2 0 p p m/°C程度と大きいため、 アルカリ含有量の大きなガラス ほど、 多層配線基板 6と実装基板 1 0との間の線膨脹係数差が小さく、 熱応力が 小さくなるからである。 ただし、 本実施例においては多層配線基板 6と実装基板 1 0との間の接続信頼性は、 ガラス材質の特性だけではなく、 多層配線基板 6の 表面に設けた応力緩和層の材質、 構造 （厚み、 面積など） にも依存しているので、 これらをも考慮してガラス材質を選択する。  On the other hand, from the viewpoint of connection reliability between the entire semiconductor module 100 and the mounting substrate 100, soda glass having a large alkali content is preferable. Since the linear expansion coefficient of the mounting substrate 10 is as large as 10 to 20 ppm / ° C, the difference in linear expansion coefficient between the multilayer wiring substrate 6 and the mounting substrate 10 increases as the alkali content of the glass increases. This is because the thermal stress is small. However, in this embodiment, the connection reliability between the multilayer wiring board 6 and the mounting board 10 depends not only on the characteristics of the glass material but also on the material and structure of the stress relieving layer provided on the surface of the multilayer wiring board 6. Thickness, area, etc.), so select the glass material in consideration of these factors.
半導体装置 9と多層配線基板 6との間の熱膨張係数差と、 多層配線基板 6とそ れを実装する実装基板との間の熱膨張係数差とを両立させ、 かつ価格なども考慮 すると、 ソーダライムと無アルカリガラスの中間的なアルカリイオン含有量であ る低アルカリガラスが好ましい。  Considering both the thermal expansion coefficient difference between the semiconductor device 9 and the multilayer wiring board 6 and the thermal expansion coefficient difference between the multilayer wiring board 6 and the mounting board on which the multilayer wiring board 6 is mounted, and considering the price and the like, Low alkali glass, which has an intermediate alkali ion content between soda lime and non-alkali glass, is preferred.
絶縁基板 1の厚さは 1 0 0から 1 0 0 0 / mが望ましく、 より好ましくは約 3 0 0から 5 0 0 At mである。 絶縁基板 1の厚さが 1 0 0 0 Ai m以上であると、 貫 通孔加工のコストが増大して実用的ではないからである。 一方、 l O O /z m以下 であると、 基板の製造工程における搬送などハンドリング性に劣る上、 貫通孔 1 0 0を形成した場合に絶縁基板 1の強度が低下し、 破損するおそれがあるからで める。  The thickness of the insulating substrate 1 is preferably from 100 to 100 / m, more preferably from about 300 to 500 Atm. If the thickness of the insulating substrate 1 is 1000 Aim or more, the cost of through-hole processing increases, which is not practical. On the other hand, if it is less than l OO / zm, handling properties such as transport in the substrate manufacturing process are inferior, and when the through hole 100 is formed, the strength of the insulating substrate 1 may be reduced and the insulating substrate 1 may be damaged. Confuse.
この絶縁基板 1は、 サンドプラストにより形成された貫通孔 1 0 0を有してい る。 この貫通孔 1 0 0により、 基板の両面に形成される配線を相互に接続し、 か つその接続を維持できる。 サンドブラストでは、 図 3 1に示すように、 ガラス基 板上に耐サンドプラスト性を有する膜を形成し （a ) 、 該膜にフォトリソ技術を 用いて開口部を形成し （b ) 、 マスクとする。 その後、 研磨粒子をマスク層に吹 き付けることで （c ) 、 開口部にあるガラスを微小単位で破砕しながら貫通孔を 形成する （d ) 。 その後、 マスクを除去することにより （e ) 、 貫通孔を有する 絶縁基板 1が形成される。 This insulating substrate 1 has a through hole 100 formed by sand plast. You. The through holes 100 allow interconnections formed on both sides of the substrate to be interconnected and maintained. In sandblasting, as shown in FIG. 31, a film having anti-sandplast resistance is formed on a glass substrate (a), and an opening is formed in the film by using a photolithography technique (b) to form a mask. . Thereafter, abrasive particles are sprayed on the mask layer (c) to form a through hole while crushing the glass in the opening in minute units (d). Thereafter, by removing the mask (e), the insulating substrate 1 having the through holes is formed.
加工条件にもよるが、 サンドブラストにより貫通孔 1 0 0を形成すると、 図 1 にも示すように、 一方の開口端と他方の開口端とで貫通孔 1 0 0の径が異なるこ と多い。 すなわち、 フォトエッチング法またはレーザ加工では、 径がほぼ一定の 貫通孔 （スルーホール） が形成されやすいのに対して、 サンドブラストでは、 サ ンドプラストが開始された基板の表面 （加工開始面） からもう一方の基板の表面 Although depending on the processing conditions, when the through hole 100 is formed by sandblasting, as shown in FIG. 1, the diameter of the through hole 100 is often different between one opening end and the other opening end. In other words, in photo-etching or laser processing, through-holes (through-holes) of almost constant diameter are easily formed, whereas in sand blasting, the surface of the substrate where sand blasting has started (the processing start surface) is the other. Substrate surface
(加工終了面） に向って、 貫通孔 1 0 0の径の大きさは徐々に小さくなる。 このような形状になるのは、 加工が進むにつれて孔が深くなると加工粉体を搬 送している空気の圧力が低下 （圧損） して加工粉体そのものの到達効率が低下す るからである。 また、 加工が進むにつれ、 被加工物であるガラスの破砕粉も発生 し、 この運動方向が加工粉体とは逆であるために、 加工粉体の運動エネルギーを うち消すような衝突も発生しやすくなるからである。 なお、 両面からサンドプラ ストしさえすれば多層配線基板 6に形成した貫通孔の開口径を表裏で同じにする ことも可能である。 ただし、 その場合には加工終点の制御が必要となる。 The diameter of the through hole 100 gradually decreases toward the (processing end surface). The reason for this shape is that if the hole becomes deeper as the processing proceeds, the pressure of the air carrying the processing powder decreases (pressure loss) and the efficiency of the processing powder itself decreases. . In addition, as the processing progresses, crushed powder of the glass to be processed is also generated, and since the direction of movement is opposite to that of the processed powder, a collision occurs that erases the kinetic energy of the processed powder. It is easier. It is also possible to make the opening diameters of the through-holes formed in the multilayer wiring board 6 the same on both sides as long as sand-blasting is performed from both sides. However, in that case, it is necessary to control the processing end point.
図 6はサンドプラストによって形成された貫通孔 1 0 0と、 フォトエッチング 法によって形成された貫通孔を示したものである。 サンドブラストにより形成さ れた貫通孔 1 0 0の壁面の極表面には、 加工原理そのものに由来する微小の凹凸 が存在するため、 貫通孔 1 0 0の内壁面上の配線は強い密着強度が得られる。 ま た、 サンドブラストの加工条件を適宜選択して、 スパッタにより貫通孔 1 0 0の 内面に給電膜が形成され易くなるように壁面のテーパ角を調節することも容易で ある。 この結果として、 給電膜の形成後に貫通孔 1 0 0の内面にめっき配線を精 密に形成できる。 なお、 テーパの角度を調節するには、 加工が進むにつれてサン ドプラストに用いる粒子の粒径を変化させたり、 風圧を調整するなどの方法があ る。 FIG. 6 shows a through hole 100 formed by sandplast and a through hole formed by photoetching. On the very surface of the wall of the through hole 100 formed by sandblasting, there are minute irregularities derived from the processing principle itself, so the wiring on the inner wall of the through hole 100 has strong adhesion strength. Can be Further, it is also easy to appropriately select the processing conditions of the sand blast and to adjust the taper angle of the wall surface so that the power supply film is easily formed on the inner surface of the through hole 100 by sputtering. As a result, plated wiring can be precisely formed on the inner surface of the through hole 100 after the formation of the power supply film. In order to adjust the angle of the taper, there are methods such as changing the particle size of the particles used for the sand plast as the processing progresses and adjusting the wind pressure. You.
なお、 図 3 2に示すように、 両面からサンドブランドを行うことにより絶縁基 板の中央から外部に向って貫通孔の径が広がっていく形状としてもよレ、。 この場 合、 一方から貫通孔を開口する場合に比べ、 貫通孔形成までの時間が短縮される ため、 開口端での貫通孔の径は小さくすることができる。  In addition, as shown in FIG. 32, the shape of the through-hole may be widened from the center of the insulating substrate toward the outside by sand branding from both sides. In this case, the time required for forming the through hole is shorter than when the through hole is opened from one side, and the diameter of the through hole at the opening end can be reduced.
また、 図 3 3に示すように、 貫通孔の形成開始面を異.ならせることにより、 テ ーパの向きが逆方向の貫通孔を有する絶縁基板を形成することができる。 貫通孔 のテーバの向きが全て同じ場合、 応力により絶縁基板が反る場合があるが、 貫通 孔のテーパの向きを異ならせると、 絶縁基板の反りを防止でき、 その後絶縁基板 上に微細配線を形成することができる。  Further, as shown in FIG. 33, by making the formation start surface of the through-hole different, an insulating substrate having a through-hole in which the direction of the taper is opposite can be formed. If the taper direction of the through holes is the same, the insulating substrate may warp due to stress.However, if the direction of the taper of the through hole is different, the warping of the insulating substrate can be prevented, and then fine wiring is placed on the insulating substrate. Can be formed.
本実施例にかかる多層配線基板は、 例えばマルチチップモジュールのィンター ポーザとして用いることができる。 図 4は、 絶縁基板 1の貫通孔 1 0 0の開口径 が小さい面 （基板の 1次側） には、 半導体装置 9を搭載し、 開口径が大きい面 (基板の 2次側） は、 半導体モジュールを実装する実装基板 1 0に実装したもの を示している。 これにより、 基板の 1次側では、 半導体装置を狭ピッチに実装、 接続できる。  The multilayer wiring board according to the present embodiment can be used, for example, as an interposer of a multi-chip module. FIG. 4 shows that the semiconductor device 9 is mounted on the surface of the insulating substrate 1 where the through hole 100 has a small opening diameter (primary side of the substrate), and the surface with the large opening diameter (secondary side of the substrate) is The figure shows a semiconductor module mounted on a mounting board 10 on which a semiconductor module is mounted. This allows semiconductor devices to be mounted and connected at a narrow pitch on the primary side of the substrate.
貫通孔 1 0 0の 2次側開口径は、 1 0 0から 1 0 0 0 / mであり、 絶縁基板 1 の厚みに対して 1 / 1 0倍から 1 0倍程度となることが望ましい。 2次側開口径 が絶縁基板 1の厚みの約 1 0倍を越えると、 絶縁基板 1のその部分における機械 的強度、 例えば抗折強度が保てないからである。 逆に、 2次側開口径が絶縁基板 1の厚みの約 1 Z 1 0より小さくなると、 1次側にまで貫通する孔を形成するた めには、 ほぼ 9 0度、 少なくとも 8 8度のテーパ角が必要となるので、 貫通孔壁 面への配線形成が困難になりやすい。 また、 加工粉体が孔の奥にまで到達しにく くなり、 その結果としてサンドブラスト加工の速度が遅くなるからである。  The secondary side opening diameter of the through hole 100 is from 100 to 100 / m, and is desirably about 1/10 to 10 times the thickness of the insulating substrate 1. If the secondary opening diameter exceeds about 10 times the thickness of the insulating substrate 1, the mechanical strength at that portion of the insulating substrate 1, for example, the bending strength cannot be maintained. Conversely, when the secondary opening diameter is smaller than about 1Z10, which is the thickness of the insulating substrate 1, approximately 90 degrees, at least 88 degrees, is required to form a hole penetrating to the primary side. Since a taper angle is required, it is likely to be difficult to form wiring on the wall of the through hole. In addition, it becomes difficult for the processing powder to reach the inside of the hole, and as a result, the speed of sandblasting is reduced.
さらに好ましくは、 貫通孔の 2次側開口径は 2 0 0 μ mから 3 0 0 μ mであり、 絶縁基板 1の厚みに対して約 2 / 5倍から約 1倍である。 例えば、 貫通孔 1 0 0 の 2次側開口直径が 2 5 0 μ πιであるとき、 貫通孔 1 0 0と千鳥の位置関係にな るようにはんだバンプ 7を配置してやることによって、 貫通孔内部の配線とはん だバンプ 7とを相互に接続するための配線のレイアウトも容易である。 一方、 1次側の開口径は 5 i mから 3 0 0 /i mであり、 より好ましくは 1 0 μ mから 1 0 0 u mであり、 絶縁基板 1の厚みの約 1 Z 5 0力 ら約 1 / 5倍であ る。 More preferably, the secondary side opening diameter of the through hole is from 200 μm to 300 μm, and is about / to about 1 times the thickness of the insulating substrate 1. For example, when the secondary-side opening diameter of the through hole 1 0 0 is 2 5 0 μ πι, by'll arranged through-hole 1 0 0 bumps 7 solder so that such a positional relationship staggered, the through-hole interior The wiring layout for interconnecting the wiring and the solder bumps 7 is also easy. On the other hand, the opening diameter on the primary side is from 5 im to 300 / im, more preferably from 10 μm to 100 um, and the thickness of the insulating substrate 1 is about 1 Z 50 force to about 1 / 5 times.
多層配線基板 6の 1次側には半導体装置 9が搭載されるため、 1次側の多層配 線層 3の配線は狭ピッチが必要となり、 開口径は小さい方が望ましい。 すなわち、 貫通孔 1 0 0の 1次側の開口径を小さくすると、 貫通孔の間により多くの配線チ ヤンネルを通すことができ、 その結果として、 より層数の少ない薄膜配線層 2で 配線の弓 Iき回しが可能になるからである。  Since the semiconductor device 9 is mounted on the primary side of the multilayer wiring board 6, the wiring of the multilayer wiring layer 3 on the primary side needs to have a narrow pitch, and a smaller opening diameter is desirable. That is, if the opening diameter on the primary side of the through hole 100 is reduced, more wiring channels can pass between the through holes, and as a result, the wiring of the thin film wiring layer 2 having a smaller number of layers can be formed. This is because the bow I can be turned.
図 1乃至図 4では、 絶縁基板 1の両面において電気的接続を可能とする貫通孔 1 0 0の内面には、 導電性材料 （配線 1 0 1 ) が存在している。 例えば銅配線 1 0 1は、 貫通孔 1 0 0の内面にスパッタ等により給電膜、 例えば C r / C uを形 成し、 その後電気めつきにより形成する。 なお、 銅配線 1 0 1が形成された後に、 絶縁性の材料を充填してもよい。  In FIGS. 1 to 4, a conductive material (wiring 101) exists on the inner surface of the through hole 100 that enables electrical connection on both surfaces of the insulating substrate 1. For example, the copper wiring 101 is formed by forming a power supply film, for example, Cr / Cu on the inner surface of the through hole 100 by sputtering or the like, and thereafter, by electroplating. Note that an insulating material may be filled after the copper wiring 101 is formed.
また、 絶縁基板 1の両面間の電気的接続を取る方法として、 貫通孔 1 0 0の内 面に配線を形成する以外に、 ペースト印刷等により貫通孔 1 0 0を導電性材料で 充填する、 又ははんだ材料を溶融させて流し込むようにしてもよい。 適切に選択 した導電性材料を絶縁基板 1に充填した場合は、 貫通孔 1 0 0を有する絶縁基板 1の強度を高めることもできる。  In addition, as a method of establishing electrical connection between both surfaces of the insulating substrate 1, besides forming wiring on the inner surface of the through hole 100, the through hole 100 is filled with a conductive material by paste printing or the like. Alternatively, the solder material may be melted and poured. When the insulating substrate 1 is filled with an appropriately selected conductive material, the strength of the insulating substrate 1 having the through hole 100 can be increased.
絶縁基板 1の表面には、 配線 1 2 0とポリイミドゃポリベンゾシク口ブテン等 の層間絶縁層 1 1 0等からなる薄膜配線層 2が形成されており、 各層間絶縁層 1 1 0 (薄膜配線層 2 ) は層間および線間の配線絶縁が確保できる厚みが必要であ る。 本願発明では、 おおむね約 5〜 5 0 mの範囲であるが、 より好ましくは約 1 0から 2 0 μ mである。 なお、 層間絶縁層 1 1 0は高耐熱十生樹脂であることが 望ましい。  On the surface of the insulating substrate 1, a thin film wiring layer 2 composed of a wiring 120 and an interlayer insulating layer 110 such as a polyimide or polybenzobutene is formed, and each interlayer insulating layer 110 (a thin film wiring layer) is formed. 2) needs to be thick enough to ensure wiring insulation between layers and between lines. In the present invention, it is generally in the range of about 5 to 50 m, but more preferably about 10 to 20 μm. Preferably, the interlayer insulating layer 110 is made of a high heat resistant resin.
図 2乃至図 4では、 絶縁基板 1の面のうち、 貫通孔 1 0 0の開口部の径が小さ レ、側 （ 1次側） には 2層の薄膜配線層 2が形成され、 貫通孔 1 0 0の開口部の径 が大きい側 （2次側） には 1層の薄膜配線層 2が形成されている。 しかし、 絶縁 基板 1の両面に形成される薄膜配線層 2の層数は任意であり、 当該半導体モジュ ールの設計に応じて自由に設定できる。 また、 絶縁基板 1の 2次側において、 層 間絶縁層を形成せず応力緩和層のみ形成してもよレ、。 2 to 4, in the surface of the insulating substrate 1, the diameter of the opening of the through hole 100 is small, and on the side (primary side), two thin film wiring layers 2 are formed. One thin-film wiring layer 2 is formed on the side (secondary side) where the diameter of the opening of 100 is large. However, the number of the thin film wiring layers 2 formed on both surfaces of the insulating substrate 1 is arbitrary, and can be freely set according to the design of the semiconductor module. Also, on the secondary side of the insulating substrate 1, the layer It is also possible to form only the stress relaxation layer without forming the interlayer insulating layer.
本実施例においては、 例えば、 薄膜配線層 2は、 一層ずつ形成して積層しても よレ、。 すなわち、 絶縁基板 1の上に配線パターンを形成し、 その後層間絶縁層 1 1 0を形成する。 その際、 フォトリソグラフィ技術を用い、 セミアディティブめ つきプロセスにより配線形成すると配線高密度ィ匕が図れる。 また、 スクリーン印 刷などの方法を用いて配線形成しても構わない。 そして、 必要に応じて形成され た層間絶縁層 1 1 0の上に配線パターンを形成し、 再ぴ層間絶縁層 1 1 0を形成 する。 ·  In the present embodiment, for example, the thin film wiring layers 2 may be formed one by one and laminated. That is, a wiring pattern is formed on the insulating substrate 1, and then the interlayer insulating layer 110 is formed. At this time, if a wiring is formed by a semi-additive plating process using a photolithography technique, high-density wiring can be achieved. Also, the wiring may be formed using a method such as screen printing. Then, a wiring pattern is formed on the interlayer insulating layer 110 formed as necessary, and a re-formed interlayer insulating layer 110 is formed. ·
本実施例では、 絶縁基板 1はガラス基板またはシリコン基板であり、 セラミツ ク基板に比べ平滑性があり、 熱膨張係数が小さく、 さらに半導体装置 9と熱膨張 係数が近い。 従って、 基板上で微細な配線パターンを形成することができる。 具 体的には、 ガラス基板上の配線ピッチは約 2から 2 0 0 μ πιである。 2 0 0マイ クロメータを越える配線ピッチでは、 層数を効果的に低減できない。 2マイクロ メータ未満の配線ピッチでは、 配線の電気抵抗が大きくなつてしまう。  In the present embodiment, the insulating substrate 1 is a glass substrate or a silicon substrate, has a smoother property than the ceramic substrate, has a smaller thermal expansion coefficient, and has a thermal expansion coefficient close to that of the semiconductor device 9. Therefore, a fine wiring pattern can be formed on the substrate. Specifically, the wiring pitch on a glass substrate is about 2 to 200 μπι. If the wiring pitch exceeds 200 micrometer, the number of layers cannot be reduced effectively. If the wiring pitch is less than 2 micrometers, the electrical resistance of the wiring will increase.
本実施例で用いられるガラス基板の熱膨張係数は約 5 p p mZ°Cであり、 一方 ポリイミドゃポリベンゾシクロブテン等の樹脂からなる層間絶縁層 1 1 0の熱膨 張係数は数 1 0 p p m/°Cであるため、 熱膨張係数の差から熱応力が発生する。 ガラス基板 1と層間絶縁層 1 1 0の厚みの相対比を考慮せずに層間絶縁層 1 1 0 を作製すると、 配線パターンの粗密により、 多層配線基板 6の反りやたわみが発 生する。 本実施例ではガラス基板の厚みが層間絶縁層 1 1 0の厚さの関係を 3 0 倍から 5 0倍程度の厚みとなるように調整してレ、るので、 多層配線基板 6の反り は小さく抑えられる。 なお、 層間絶縁層 1 1 0として液晶性高分子を使用する場 合には、 熱膨張係数がポリイミ ドゃポリベンゾシクロブテンと比べて小さいため、 基板反りの抑制という観点では有利となる。  The coefficient of thermal expansion of the glass substrate used in this example is about 5 pp mZ ° C, while the coefficient of thermal expansion of the interlayer insulating layer 110 made of a resin such as polyimide / polybenzocyclobutene is several 10 ppm. / ° C, thermal stress is generated due to the difference in thermal expansion coefficient. If the interlayer insulating layer 110 is manufactured without considering the relative ratio of the thickness of the glass substrate 1 to the thickness of the interlayer insulating layer 110, the multilayer wiring board 6 will be warped or bent due to the density of the wiring pattern. In the present embodiment, the relationship between the thickness of the glass substrate and the thickness of the interlayer insulating layer 110 is adjusted so as to be about 30 to 50 times the thickness. Can be kept small. When a liquid crystalline polymer is used as the interlayer insulating layer 110, the coefficient of thermal expansion is smaller than that of polyimide-polybenzocyclobutene, which is advantageous from the viewpoint of suppressing substrate warpage.
このように、 ガラスまたはシリコン基板では、 基板上に微細な配線パターンを 形成することができる。 さらに、 ガラスまたはシリコン基板上には微細な配線を 形成できるため、 絶縁基板 1上の薄膜配線層 2の層数は従来のセラミック基板に 比べて少なくでき、 多層配線基板を薄くできる。  Thus, with a glass or silicon substrate, a fine wiring pattern can be formed on the substrate. Further, since fine wiring can be formed on a glass or silicon substrate, the number of thin film wiring layers 2 on the insulating substrate 1 can be reduced as compared with a conventional ceramic substrate, and the multilayer wiring substrate can be thinned.
続いて、 薄膜配線層 2の各層で配線の引回しの一実施例を説明する。 例えば、 図 2乃至図 4の一次側の 2層からなる薄膜配線層 2のうち、 絶縁基板 1のすぐ上 に形成される配線 （第一の配線） ではユーザ基板と半導体装置 9との信号をやり 取りする信号配線を、 1層目の層間絶縁層の上に形成される第二の配線では電源 線またはダランド線を、 2層目の層間絶縁層の上に形成される第 3の配線は半導 体装置 9 ( L S I ) 同士の信号のやり取りを行う信号線として形成してもよい。 このように、 多層配線層 3を少なくとも 2層構造とすることにより、 3層の配線 層を形成することができ、 半導体装置 9とユーザ基板 1 0との信号線、 半導体装 置 9同士の信号配線、 電源配線またはグランド配線を分けることができ、 高速か つ微細な配線パターンを形成でき、 また信号の雑音等の防止にも効果がある。 も ちろん、 配線パターンの制約等により、 半導体装置 9 ( L S I ) 同士の信号のや り取りする配線をすベてを 2層目の層間絶縁層の上に形成する必要はなく、 半導 体装置 9 ( L S I ) 同士の信号のやり取りする配線が、 他の配線層よりも多層配 線基板の最表面で多く行われていればよい。 Next, an embodiment of wiring routing in each layer of the thin film wiring layer 2 will be described. For example, In the thin-film wiring layer 2 composed of the two layers on the primary side in FIGS. 2 to 4, the wiring (first wiring) formed immediately above the insulating substrate 1 exchanges signals between the user substrate and the semiconductor device 9. The second wiring formed on the first interlayer insulating layer is the power supply line or the duland line, and the third wiring formed on the second interlayer insulating layer is the semiconductor wiring. It may be formed as a signal line for exchanging signals between the body devices 9 (LSI). As described above, by forming the multilayer wiring layer 3 into at least a two-layer structure, three wiring layers can be formed, and signal lines between the semiconductor device 9 and the user substrate 10 and signals between the semiconductor devices 9 are formed. Wiring, power supply wiring and ground wiring can be separated, high-speed and fine wiring patterns can be formed, and it is also effective in preventing signal noise and the like. Needless to say, due to restrictions on wiring patterns, it is not necessary to form all of the wiring for exchanging signals between the semiconductor devices 9 (LSI) on the second interlayer insulating layer. It suffices that the number of wirings for exchanging signals between the devices 9 (LSIs) be larger on the outermost surface of the multilayer wiring board than on other wiring layers.
あるいは、 絶縁基板 1のすぐ上に形成される配線 （第一の配線） では電源線ま たはグランド線を形成し、 1層目の層間絶縁層 1 1 0の上に形成される第二の配 線の中に、 ユーザ基板と半導体装置 9との信号をやり取りする信号配線と半導体 装置 9 ( L S I ) 同士の信号のやり取りを行う信号線とを一緒に配置して形成す れば、 多層配線層 3を 1層とすることができる。  Alternatively, a power line or a ground line is formed in the wiring (first wiring) formed immediately above the insulating substrate 1, and the second wiring formed on the first interlayer insulating layer 110 is formed. If the signal wiring for exchanging signals between the user board and the semiconductor device 9 and the signal lines for exchanging signals between the semiconductor devices 9 (LSI) are arranged together in the wiring, the multilayer wiring is formed. Layer 3 can be a single layer.
なお、 多層配線層 3を 1層とするか、 2層以上必要となるかは、 半導体装置 9 の論理規模やそのレイアウト、 要求される高速信号特性などによって決まる。 また、 各層間絶縁層の上に形成する配線の役割を変化させる場合、 各層毎に配 線幅や配線形状を変えることも有効である。  It should be noted that whether the multilayer wiring layer 3 is a single layer, or whether two or more layers are required depends on the logic scale of the semiconductor device 9, its layout, required high-speed signal characteristics, and the like. When the role of wiring formed on each interlayer insulating layer is changed, it is effective to change the wiring width and wiring shape for each layer.
本実施例では、 ユーザ基板に実装される基板の 2次側には、 応力緩和層 5が形 成されている。 絶縁基板 1が低アル力リガラスの場合、 その線膨張係数は約 5 p p m/°Cであり、 一方半導体チップ 9の線膨張係数は約 3 p p mZ°Cであり、 半導体チップが搭載された半導体モジュール全体の線膨張係数は、 ほぼガラス基 板の線膨脹係数に等しく約 5 p p mZ°Cである。 従って、 絶縁基板 1と半導体装 置 9の間で生じる熱応力は小さレ、。  In the present embodiment, the stress relaxation layer 5 is formed on the secondary side of the board mounted on the user board. When the insulating substrate 1 is made of low-strength glass, its linear expansion coefficient is about 5 ppm / ° C, while the linear expansion coefficient of the semiconductor chip 9 is about 3 pp mZ ° C. The linear expansion coefficient of the whole module is almost equal to the linear expansion coefficient of the glass substrate, and is about 5 ppmZ ° C. Therefore, thermal stress generated between the insulating substrate 1 and the semiconductor device 9 is small.
一方、 半導体モジュール 1 0 0◦が実装される実装基板 1 0の線膨張係数は、 約 1 0〜2 0 p p m ^Cである。 なお、 最も一般的なガラスエポキシ基板の場合 は約 1 5〜1 8 p p mZ。Cである。 従って、 半導体モジュール 1 0 0 0と実装基 板 1 0の間で生じる熱応力は大きレ、。 厚膜の絶縁層 5 (応力緩和層） は、 半導体 チップ 9を搭載した半導体モジュール 1 0 0 0と実装基板 1 0との熱膨張係数の 差から生じる応力を緩和することができる。 On the other hand, the linear expansion coefficient of the mounting substrate 10 on which the semiconductor module 100 About 10 to 20 ppm ^ C. In the case of the most common glass epoxy substrate, it is about 15 to 18 pp mZ. C. Therefore, the thermal stress generated between the semiconductor module 100 and the mounting substrate 10 is large. The thick insulating layer 5 (stress relieving layer) can relieve stress caused by a difference in thermal expansion coefficient between the semiconductor module 100 on which the semiconductor chip 9 is mounted and the mounting substrate 10.
この応力緩和層 5の厚さは、 応力緩和の観点からは絶縁基板 1の厚みに対して 約 1 / 1 0から約 1 / 2程度の厚みであるか、 あるいは絶縁基板の対角長さに対 して約 1 / 3 0 0〜約 1ノ 2 0であることが望ましい。 例えば、 絶縁基板 1の厚 さが約 1 0 0マイクロメートルから約 1 0 0 0マイクロメートルの場合は、 応力 緩和層 5の厚さは約 1 0から 5 0 0マイクロメートルが望ましく、 絶縁基板 1の 厚さが約 3 0 0マイクロメートルから約 5 0 0マイクロメ一トルの場合は、 約 3 0乃至 2 5 0マイクロメートルである。 応力緩和層の厚さおょぴ物性値について は後述する。  From the viewpoint of stress relaxation, the thickness of the stress relaxation layer 5 is from about 1/10 to about 1/2 of the thickness of the insulating substrate 1, or the diagonal length of the insulating substrate. On the other hand, it is preferably about 1/300 to about 1/20. For example, when the thickness of the insulating substrate 1 is about 100 μm to about 100 μm, the thickness of the stress relaxation layer 5 is preferably about 100 to 500 μm, and the insulating substrate 1 When the thickness is about 300 micrometers to about 500 micrometers, it is about 30 to 250 micrometers. The thickness and physical properties of the stress relaxation layer will be described later.
応力緩和層 5は、 絶縁基板 1上にまたはマスクを用いてスクリーン印刷するこ とにより形成されるが、 スプレー塗布ゃデイスペンス、 力レンダーコ一トゃフォ トリソグラフィ技術等を使用しても構わない。  The stress relieving layer 5 is formed on the insulating substrate 1 or by screen printing using a mask, but a spray coating / dispense, a force render / co-photolithography technique or the like may be used.
例えば、 応力緩和層 5をマスク印刷 （スクリーン印刷） する場合、 所望の位置 に応力緩和層を形成することができる。 また、 応力緩和層の端部で傾斜部が形成 することもできる。 応力緩和層の材質等により、 傾斜部が形成されないようにす ることもできるし、 また傾斜部の角度を制御することもできる。  For example, when mask printing (screen printing) is performed on the stress relaxation layer 5, the stress relaxation layer can be formed at a desired position. Also, an inclined portion can be formed at the end of the stress relaxation layer. Depending on the material of the stress relaxation layer, etc., it is possible to prevent the inclined portion from being formed, and it is also possible to control the angle of the inclined portion.
一方、 スタンビングで応力緩和層を形成する場合、 スタンビング用の型に応力 緩和用の絶縁材料を塗布し、 基板上に応力緩和層の形状を転写するため絶縁材料 硬化時の端部の形状変化が生じない絶縁材料の選択が可能となる。 この場合、 印 刷方式に比べ端部の形状が一定になり易いという特徴がある。  On the other hand, when the stress relieving layer is formed by stamping, an insulating material for stress relieving is applied to a stamping die, and the shape of the insulating material is cured to transfer the shape of the stress relieving layer onto the substrate. It is possible to select an insulating material that does not change. In this case, there is a feature that the shape of the end portion is more likely to be constant than in the printing method.
さらに、 スプレー塗布やディスペンス方式では、 印刷マスクあるいはスタンピ ング金型を用いないため、 応力緩和層形成時の形状に自由度あり、 ノズル形状を 適当に選択すれば、 印刷マスクゃスタンビング金型では形成し難い応力緩和層の 形成が可能となる。 また、 印刷方式やスタンビング方式に比べ、 吹き付け量の調 整で応力緩和層の厚さを調整でき、 厚さ調整の範囲も広くなる。 半硬化あるいは未硬化の樹脂シートを貼り付ける方式では、 厚膜の応力緩和層 の形成が可能となり予めシート状の絶縁樹脂を用いるため、 応力緩和層表面の平 ±旦性に優れるという特徴がある。 Furthermore, since the spray coating and the dispensing method do not use a print mask or a stamping mold, the shape at the time of forming the stress relaxation layer has a degree of freedom, and if the nozzle shape is selected appropriately, the print mask and stamping mold do not It is possible to form a stress relaxation layer that is difficult to form. In addition, compared to the printing method and the stamping method, the thickness of the stress relaxation layer can be adjusted by adjusting the spray amount, and the range of the thickness adjustment can be widened. The method of attaching a semi-cured or uncured resin sheet allows the formation of a thick film stress relaxation layer and uses a sheet-like insulating resin in advance, so the surface of the stress relaxation layer has excellent flatness. .
なお、 これらの方法を単一で用いるのではなく、 組み合せて応力緩和層を形成 してもよいことはいうまでもない。  It is needless to say that the stress relaxation layer may be formed by combining these methods instead of using these methods alone.
絶縁基板 1と同じように、 応力緩和層 5の両面においても電気的に接続をとる 必要がある。 そのための 1つの方法として、 応力緩和層 5にも貫通孔 1 0 0が形 成されている。 この貫通孔 1 0 0は、 サンドブラストのみならずレーザ加工、 ま たはフォトエッチングなどにより形成される。 応力緩和層 5において電気的接続 をとる別の方法としては、 図 2 9のように、 配線基板の貫通孔が形成されていな いところに応力緩和層 5を形成し、 その応力緩和層の表面 （傾斜表面も含む） に 密着して配線を形成するという方法がある。 このように所定の位置に応力緩和層 を形成するには、 メタルマスク等を用いて印刷形成する、 いわゆるスクリーン印 刷が有効である。  As in the case of the insulating substrate 1, it is necessary to electrically connect both sides of the stress relaxation layer 5. As one method for this, a through hole 100 is also formed in the stress relaxation layer 5. This through hole 100 is formed by not only sand blasting but also laser processing or photo etching. As another method of making electrical connection in the stress relaxation layer 5, as shown in FIG. 29, the stress relaxation layer 5 is formed in a place where the through hole is not formed in the wiring board, and the surface of the stress relaxation layer is formed. (Including inclined surfaces) to form wiring. In order to form the stress relieving layer at a predetermined position in this way, so-called screen printing, in which printing is performed using a metal mask or the like, is effective.
なお、 応力緩和層 5は多層配線基板 6に必須の構成ではなく、 半導体モジユー ル 1 0 0 0とユーザ基板 1 0によって生じる熱応力が許容できる範囲であれば、 多層配線基板 6に応力緩和層 5を形成する必要はない。 また、 半導体モジュール 1 0 0 0とユーザ基板 1 0の熱応力が生じたときに、 応力緩和層 5ではなくアン ダーフィルを用いて信頼性を確保してもよい。 また、 応力緩和層 5を形成した半 導体モジュールであっても、 ユーザがより高い信頼性を望む場合はアンダーフィ ルを用いてもよいことはいうまでもない。  The stress relieving layer 5 is not an essential component of the multilayer wiring board 6, and the stress relieving layer 5 may be formed on the multilayer wiring board 6 as long as the thermal stress generated by the semiconductor module 100 and the user board 10 is within an allowable range. There is no need to form 5. When thermal stress occurs between the semiconductor module 100 and the user substrate 100, reliability may be ensured by using an underfill instead of the stress relaxation layer 5. Also, it goes without saying that even if the semiconductor module has the stress relaxation layer 5 formed thereon, an underfill may be used if the user desires higher reliability.
また、 他の実施例として、 絶縁基板の二次側に応力を緩和するための絶縁層を 特別に設けるのではなく、 図 7、 図 8に示すように、 層間絶縁層 1 1 0の材料を 変えることにより、 多層配線基板 6の厚さ方向で線膨張係数を変化させることも 可能である。 すなわち、 絶縁基板 1の 1次側では、 線膨張係数が小さい材料で層 間絶縁層を形成し、 実装される半導体装置の線膨張係数に近づける。 一方、 絶縁 基板 1の 2次側では、 線膨張係数が大きい材質で層間絶縁層を形成し、 実装され る基板に線膨張係数を近づける。 特に、 薄膜配線層 2を一層ずつ形成して積層す る場合は、 必要に応じて、 容易に、 薄膜配線層の線膨張係数を変化させることが できる。 このように形成することにより、 応力緩和層 5を特別設けなくても、 多 層配線基板により、 半導体装置 9と実装基板 1 0の間の熱応力を緩和し、 接続信 賴性を確保することができる。 多層配線基板 6の厚さ方向で線膨張係数を変化さ せる場合は、 多層配線基板のコア基板である絶縁基板 1はガラスまたはシリコン 基板に限定されず、 従来のセラミック基板、 メタルコア基板であってもよい。 ま た、 この多層配線基板 6の厚さ方向で、 線膨張係数を変化させる場合は、 貫通孔 形成はサンドブラストのみならずレーザ加工、 フォトリソエッチング加工であつ てもよい。 Further, as another embodiment, instead of providing an insulating layer for relaxing stress on the secondary side of the insulating substrate, as shown in FIGS. 7 and 8, the material of the interlayer insulating layer 110 is used. By changing, the linear expansion coefficient can be changed in the thickness direction of the multilayer wiring board 6. That is, on the primary side of the insulating substrate 1, an inter-layer insulating layer is formed of a material having a small coefficient of linear expansion to approximate the coefficient of linear expansion of the semiconductor device to be mounted. On the other hand, on the secondary side of the insulating substrate 1, an interlayer insulating layer is formed of a material having a large coefficient of linear expansion so that the coefficient of linear expansion approaches the substrate on which it is mounted. In particular, when the thin film wiring layers 2 are formed one by one and laminated, it is possible to easily change the linear expansion coefficient of the thin film wiring layers as necessary. it can. By forming in this way, the thermal stress between the semiconductor device 9 and the mounting substrate 10 can be reduced by the multi-layer wiring substrate without specially providing the stress relaxation layer 5, and the connection reliability can be ensured. Can be. When the coefficient of linear expansion is changed in the thickness direction of the multilayer wiring board 6, the insulating substrate 1, which is the core substrate of the multilayer wiring board, is not limited to a glass or silicon substrate, but may be a conventional ceramic substrate or a metal core substrate. Is also good. When the coefficient of linear expansion is changed in the thickness direction of the multilayer wiring board 6, the through holes may be formed not only by sandblasting but also by laser processing or photolithographic etching.
また、 他の実施例として、 図 9、 1 0のように絶縁基板 1を有さず、 線膨張係 数が異なる薄膜配線層が積層された多層配線基板であつてもよい。 このような構 造にすれば、 多層配線基板により、 半導体装置 9と実装基板 1 0の間の熱応力を 緩和し、 接続信頼性を確保することができ、 さらに多層配線基板のコア基板であ る絶縁基板 1の厚さを省略できるため、 より薄レ、多層配線基板が実現できる。 従 つて、 かかる多層配線基板を用いれば、 より薄膜化した電子装置を実現できる。 この多層配線基板 6の 1次側には、 L S I等の半導体チップを実装する。 半導 体装置 9には、 半導体チップ、 B G A、 C S P、 ウェハーレベル C S Pなどの他、 Q F P、 T S O Pなどのリードタイプの半導体装置も使用しても良い。 また、 半 導体装置 9自身が、 半導体装置とそれが実装される基板との間に生じる応力を緩 和する層を有するものであってもよい。  Further, as another embodiment, as shown in FIGS. 9 and 10, a multilayer wiring board having no insulating substrate 1 and laminated thin film wiring layers having different linear expansion coefficients may be used. With such a structure, the multilayer wiring board can reduce the thermal stress between the semiconductor device 9 and the mounting board 10 to secure the connection reliability. Since the thickness of the insulating substrate 1 can be omitted, a thinner and multilayer wiring substrate can be realized. Therefore, by using such a multilayer wiring board, a thinner electronic device can be realized. On the primary side of the multilayer wiring board 6, a semiconductor chip such as LSI is mounted. The semiconductor device 9 may be a semiconductor device such as a semiconductor chip, a BGA, a CSP, a wafer-level CSP, or a lead-type semiconductor device such as a QFP or a TSOP. Further, the semiconductor device 9 itself may have a layer for relaxing a stress generated between the semiconductor device and a substrate on which the semiconductor device is mounted.
なお、 絶縁基板 1にガラス基板またはシリコン基板を用いた場合は、 半導体チ ップと絶縁基板との間に生じる応力は小さい、 または実質的に生じないが、 ユー ザがより高い信頼性を望む場合は、 図 1 1に示すように、 半導体装置 9とそれが 実装される基板との間に絶縁層 5 0 (アンダーフィル層） を充填してもよい。 実装される半導体チップ 9は、 同種のものに限らず、 例えば図 1 2に示すよう に、 異種の複数の半導体チップを多層配線基板 6上に実装してもよい。 例えば、 Aはマイコン、 Bはフラッシュメモリ、 Cは D R AM、 Dはコンデンサ等の個別 部品という組合せでもよい。 図 1 1は図 1 2の断面 a— a ' を表している。 ある いは動作電圧の異なる複数の半導体チップを組み合わせて使用することもできる。 また、 Q F P C S Pなどの半導体パッケージや抵抗やコンデンサなどの受動部 品を 1つ以上含んでいても構わない。 なお、 ここで使用される半導体チップ、 半 導体パッケージ、 受動部品は表面実装型であることが望ましい。 異種の半導体チ ップを多層配線基板 6上に実装した場合は、 異なる半導体チップ間を接続するた めに必要な配線を多層配線層 3の最上層で行い、 下位の配線層ではグランド配線 または信号配線を形成するようにする。 さらに、 最終的にユーザ基板と電気的に 接続する必要のある配線のみを絶縁基板 1の貫通孔 1 0 0を通じて接続するよう にしてもよい。 In addition, when a glass substrate or a silicon substrate is used as the insulating substrate 1, stress generated between the semiconductor chip and the insulating substrate is small or substantially not generated, but users desire higher reliability. In this case, as shown in FIG. 11, an insulating layer 50 (underfill layer) may be filled between the semiconductor device 9 and the substrate on which the semiconductor device 9 is mounted. The semiconductor chips 9 to be mounted are not limited to the same type, and for example, a plurality of different types of semiconductor chips may be mounted on the multilayer wiring board 6 as shown in FIG. For example, A may be a microcomputer, B may be a flash memory, C may be a DRAM, and D may be a combination of individual components such as capacitors. FIG. 11 shows a cross section a—a ′ of FIG. Alternatively, a plurality of semiconductor chips having different operating voltages can be used in combination. Also, semiconductor packages such as QFPCSP and passive parts such as resistors and capacitors It may contain one or more products. It is desirable that the semiconductor chips, semiconductor packages, and passive components used here are of the surface mount type. If different types of semiconductor chips are mounted on the multilayer wiring board 6, the wiring required to connect the different semiconductor chips is made in the uppermost layer of the multilayer wiring layer 3, and the lower wiring layer is ground wiring or The signal wiring is formed. Furthermore, only the wires that need to be finally electrically connected to the user board may be connected through the through holes 100 of the insulating board 1.
異なる半導体チップの糸且合せとしては、 D RAMとマイコン、 D R AMとマイ コンと D S P、 D RAMとマイコンと R OM、 D RAMとフラッシュメモリ、 D R AMと S RAMとフラッシュメモリ、 A S I Cと D R AMなどがある。 例えば、 カーナビゲーションシステムではフラッシュ内蔵マイコンと A S I Cと D RAM の組み合せなどが使われる。 デジタルスチルカメラゃデジタルビデオ力メラでは マイコンとフラッシュメモリ、 フラッシュ内蔵マイコンと D RAM、 あるいはマ イコンとフラッシュメモリーと D R AMの組み合せなどが好適である。 低電力化 のためにフラッシュメモリーが使用されるが、 フラッシュメモリーだけではメモ リー容量が不足する場合に、 高集積 D R AMを組み合わせる。 必要に応じてチッ プを積層してもかまわない。 携帯端末、 例えば、 携帯電話にはデジタルスチルカ メラと同様の構成が使用されるが、 携帯電話ではデジタルスチルカメラよりも低 消費電力が要求されるため、 一般に、 フラシュメモリーの容量を D RAMの容量 と同等以上に設定することが多！/、。  The combination of different semiconductor chips includes DRAM and microcomputer, DRAM and microcomputer and DSP, DRAM and microcomputer and ROM, DRAM and flash memory, DRAM and SRAM and flash memory, ASIC and DRAM. and so on. For example, in a car navigation system, a combination of a microcomputer with a built-in flash, an ASIC, and a DRAM is used. For digital still cameras and digital video cameras, a microcomputer and flash memory, a microcomputer with built-in flash and DRAM, or a combination of microcomputer, flash memory and DRAM are suitable. Flash memory is used to reduce power consumption, but if flash memory alone does not have enough memory capacity, use a highly integrated DRAM. Chips may be stacked as needed. Mobile terminals, for example, mobile phones use the same configuration as digital still cameras, but mobile phones require lower power consumption than digital still cameras. Often set equal to or greater than capacity! / ,.
半導体素子 9 (半導体チップ） と多層配線基板 6は、 バンプ 3 0 0等の外部接 続端子により接続される。 例えば、 バンプ 3 0 0を有する半導体素子 9を多層配 線基板 6に実装し、 リフローすることにより接続される。 また、 図 3 4に示すよ うに、 多層配線基板の 1実施例として、 バンプ 3 0 0を多層配線基板 6に形成し ておいてもよい。 この場合には、 いわゆるベアチップ （パッケージされていない 半導体素子） を多層配 ,線基板に実装することができる。  The semiconductor element 9 (semiconductor chip) and the multilayer wiring board 6 are connected by external connection terminals such as bumps 300. For example, the semiconductor element 9 having the bump 300 is mounted on the multilayer wiring board 6 and connected by reflow. As shown in FIG. 34, as an example of the multilayer wiring board, bumps 300 may be formed on the multilayer wiring board 6. In this case, a so-called bare chip (semiconductor element that is not packaged) can be mounted on a multilayer circuit board.
バンプ 3 0 0には、 金等の線材を超音波ボンディング装置により凸型の形状を 形成したものや、 スズ、 鉛、 銅、 銀、 ビスマス、 亜鉛、 インジウム等の金属を単 独あるいは 2種類以上混合した合金をはんだバンプ 3 0 0として用いることがで きる。 さらに、 銀や金等の導電性材料を配合した樹脂をバンプ 3 0 0として用い ることも可能である。 はんだバンプ 3 0 0は、 はんだの微粒子をロジン等からな る材料に配合し、 適当なマスクを用いて半導体装置の電極上に印刷し、 その後は んだの溶融温度以上に加熱してはんだを溶融させることにより形成することもで きる。 導電性の粒子を配合した樹脂を用いた場合も同様に、 ペースト状の前記樹 脂材料を適当なマスクを用いて半導体装置の電極上に印刷し、 加熱により硬化あ るいは半硬化状態とする方法によってもバンプ形成が可能である。 さらに、 電極 表面の酸化膜を除去し適度な粘着性を有するフラックスを当該電極上に塗布し、 適当な粒子径のはんだポールをマスク等により該電極上に整列し、 リフロ炉等に よりはんだの溶融温度以上に加熱することによりバンプを形成することもできる。 これらは当然、 外部接続端子 7の形成にも適用することができる。 The bump 300 may be made of a wire such as gold formed into a convex shape by an ultrasonic bonding device, or a metal such as tin, lead, copper, silver, bismuth, zinc, and indium, alone or in combination of two or more. The mixed alloy can be used as the solder bump 300 Wear. Further, a resin containing a conductive material such as silver or gold can be used as the bump 300. Solder bumps 300 are prepared by mixing fine particles of solder with a material such as rosin, printing them on the electrodes of a semiconductor device using an appropriate mask, and then heating the solder to a temperature higher than the melting temperature of the solder. It can also be formed by melting. Similarly, when a resin containing conductive particles is used, the paste-like resin material is printed on an electrode of a semiconductor device using an appropriate mask, and is cured or semi-cured by heating. Bump formation is also possible by a method. Furthermore, an oxide film on the surface of the electrode is removed, a flux having an appropriate tackiness is applied on the electrode, and a solder pole having an appropriate particle size is aligned on the electrode using a mask or the like, and the solder is removed by a reflow oven or the like. Bumps can also be formed by heating above the melting temperature. Of course, these can also be applied to the formation of the external connection terminal 7.
バンプ 3 0 0と接続する半導体装置 9に設けた電極は、 前工程と呼ばれる工程 で形成されたアルミニウムや銅の電極や、 前工程の後さらにウェハーレベル C S Pのような電極から半導体装置表面に銅等の配線で再配線を行った後に形成され る電極を用いることが可能である。 この電極表面にニッケルや金等の表面処理を 行うことにより、 バンプと電極表面のぬれ性を向上させたり、 後述する半導体モ ジュールを外部基板に搭載する等の加熱工程においてバンプ材料が電極中に拡散 しバンプと電極部の接合強度の低下を防止させることができる。  The electrodes provided on the semiconductor device 9 to be connected to the bumps 300 are made of aluminum or copper electrodes formed in a process called a pre-process, or after the pre-process, and further from the electrodes such as wafer level CSP, copper is applied to the surface of the semiconductor device. It is possible to use an electrode formed after rewiring is performed using such wiring. By performing a surface treatment such as nickel and gold on the surface of the electrode, the wettability between the bump and the electrode surface is improved, and the bump material remains in the electrode during a heating step such as mounting a semiconductor module on an external substrate, which will be described later. The diffusion can prevent a decrease in bonding strength between the bump and the electrode portion.
バンプ 3 0 0がはんだバンプの場合、 はんだとして、 S n— Z n系、 S n— A g系、 または S n— A g— C u系等のいわゆる鉛フリーはんだ、 例えば S n— 3 . O A g— 0 . 5 C uを用いてもよレ、。  When the bump 300 is a solder bump, the solder is a so-called lead-free solder such as Sn—Zn, Sn—Ag, or Sn—Ag—Cu, for example, Sn—3.0. OA g—0.5 Cu may be used.
しかし、 鉛フリーはんだは、 従来使用されていた鉛はんだに比べて固いため、 半導体装置 9と多層配線基板 6との間で生じる熱応力をはんだバンプで緩和する ことが困難である。  However, since lead-free solder is harder than conventionally used lead solder, it is difficult to reduce thermal stress generated between the semiconductor device 9 and the multilayer wiring board 6 by the solder bump.
そこで、 本実施例のように、 絶縁基板 1にガラスゃシリコン基板を用いれば、 発生する熱応力が小さくなり、 鉛フリーはんだを用いた場合であっても、 半導体 装置 9と多層配線基板 6との接続信頼性を確保することができる。  Therefore, when a glass-silicon substrate is used for the insulating substrate 1 as in the present embodiment, the generated thermal stress is reduced, and even when the lead-free solder is used, the semiconductor device 9 and the multilayer wiring substrate 6 can be used. Connection reliability can be ensured.
また、 層間絶縁層の物性値、 例えば熱膨張係数や弾性係数を多層配線基板の厚 さ方向で変化させる、 具体的には、 一次側の最表面の層間絶縁層と、 多層配線基 板 6に実装される半導体チップ 9との熱膨張係数と近づけて、 発生する熱応力を 小さくすることにより、 鉛フリーはんだを用いた場合であっても、 半導体装置 9 と多層配線基板 6との接続信頼性を確保することができる。 Further, the physical property values of the interlayer insulating layer, for example, the coefficient of thermal expansion and the elastic coefficient are changed in the thickness direction of the multilayer wiring board. Specifically, the interlayer insulating layer on the outermost surface on the primary side and the multilayer wiring board By reducing the thermal stress generated by approaching the coefficient of thermal expansion of the semiconductor chip 9 mounted on the board 6 and reducing the generated thermal stress, even when lead-free solder is used, the Connection reliability can be ensured.
ところで、 一次側の接続に用いられるはんだバンプの融点は、 二次側の接続に はんだを用いた場合には、 二次側のはんだよりも高くなくてはならない。 すなわ ち、 一次側おょぴ二次側において、 はんだ接続の温度を変化させて、 温度階層を 設けることが必要である。  Incidentally, the melting point of the solder bump used for the connection on the primary side must be higher than that of the solder on the secondary side when the solder is used for the connection on the secondary side. In other words, on the primary side and the secondary side, it is necessary to change the temperature of the solder connection and establish a temperature hierarchy.
例えば、 半導体素子と多層配線基板の一次接続には高温系鉛フリ一はんだを、 マルチチップモジュールと実装基板 1 0との 2次接続には低温系鉛フリ一はんだ を用いることが望ましい。  For example, it is desirable to use high-temperature lead-free solder for the primary connection between the semiconductor element and the multilayer wiring board, and to use low-temperature lead-free solder for the secondary connection between the multi-chip module and the mounting board 10.
多層配線基板 6の 2次側には、 ユーザ基板 1 0との接続を取るため、 外部接続 端子 7が形成されている。 外部接続端子 7は、 バンプ 3 0 0と同様に、 はんだポ ール以外にも、 導電性の粒子を配合した樹脂などにより構成しても良い。 外部基 板との接続方法によっては、 ボールや端子形成を行わずに使用しても良レ、。 外部接続端子 7として、 はんだバンプを形成した場合、 隣り合うバンプ間の距 離 （バンプピッチ） は 5 0 0 μ mから 8 0 0 i m程度であるが、 必然的にユーザ 基板の接続端子のピッチに制約されている。 一般的に、 接続端子ピッチが狭くな るとユーザ基板の価格が増大するため、 モジュール全体のコストを勘案して接続 ピッチが決まっている。 典型的な接続ピッチは前述の通り 5 0 0〜8 0 O mm程 度であるが、 1 0 0 0 mmを越える接続ピッチとなる場合もある。 バンプピッチ にあわせてはんだバンプ 7の直径を適宜選択するが、 はんだバンプの直径は最大 でバンプピッチの約 Ί 0 %の大きさとなる。  An external connection terminal 7 is formed on the secondary side of the multilayer wiring board 6 to establish connection with the user board 10. The external connection terminal 7 may be made of a resin or the like containing conductive particles in addition to the solder hole, similarly to the bump 300. Depending on the connection method with the external board, it can be used without forming balls or terminals. When solder bumps are formed as external connection terminals 7, the distance between adjacent bumps (bump pitch) is about 500 μm to 800 im, but the pitch of the connection terminals on the user board is inevitable. Is restricted to. In general, as the connection terminal pitch becomes narrower, the price of the user board increases, so the connection pitch is determined in consideration of the cost of the entire module. A typical connection pitch is about 500 to 800 mm as described above, but there are cases where the connection pitch exceeds 100 mm. The diameter of the solder bump 7 is appropriately selected according to the bump pitch, but the diameter of the solder bump is at most about 0% of the bump pitch.
外部接続端子 7がはんだバンプの場合、 はんだとして、 S n— Z n系、 S n— A g系、 または S n— A g— C u系等のいわゆる^ 3、フリーはんだ、 例えば S n— 3 . O A g - 0 . 5 C uを用いてもよい。  When the external connection terminal 7 is a solder bump, so-called ^ 3 such as Sn—Zn system, Sn—Ag system, or Sn—Ag—Cu system, and free solder, for example, Sn— 3. OA g-0.5 Cu may be used.
上述したように、 従来用いられていた鉛はんだに比べ、 鉛フリ一はんだは固い ので、 鉛フリーはんだを用いた場合は、 マルチチップモジュールと実装基板 1◦ との間で生じる熱応力をはんだバンプ自身で緩和することが困難である。  As described above, lead-free solder is harder than conventional lead solder, so when using lead-free solder, the thermal stress generated between the multi-chip module and the mounting board 1 It is difficult to ease yourself.
しかし、 本実施例のように、 応力緩和層を設けたり、 マルチチップモジュール の層間絶縁層の熱膨張係数を多層配線基板の厚さ方向で変化させて、 応力を緩和 することにより、 鉛フリーはんだを用いた場合であっても、 マルチチップモジュ ールと実装基板 1 0との接続信頼性を確保できる。 However, as in this embodiment, a stress relaxation layer is provided, By changing the coefficient of thermal expansion of the interlayer insulating layer in the thickness direction of the multilayer wiring board to relieve the stress, even when lead-free solder is used, the multi-chip module and the mounting board 10 Connection reliability can be ensured.
すなわち、 本実施例における多層配線基板 6は、 半導体チップのィンターポー ザとしての役割を果たすのみならず、 半導体装置 9 (半導体チップ、 L S I等） および多層配線基板 6と実装基板 1 0の間に生じる熱応力を緩和する。 さらに、 応力緩和層等の手段により半導体モジュール 1 0 0 0とユーザ基板 1 0の間に生 じる熱応力を緩和することができれば、 半導体モジュール 1 0 0 0をユーザ基板 1 0に実装する場合にアンダーフィルを充填する必要がなくなる。  That is, the multilayer wiring board 6 in the present embodiment not only plays a role as an interposer of the semiconductor chip but also occurs between the semiconductor device 9 (semiconductor chip, LSI, etc.) and the multilayer wiring board 6 and the mounting board 10. Relieve thermal stress. Furthermore, if the thermal stress generated between the semiconductor module 100 and the user substrate 100 can be reduced by means such as a stress relaxation layer, the semiconductor module 100 may be mounted on the user substrate 100. Need not be filled with underfill.
なお、 本実施例に説明した半導体モジュールであっても、 ユーザがより高い信 頼性を望む場合は、 半導体モジュールと実装基板 1 0 (ユーザ基板） の間にアン ダーフィルを形成してもよいことはいうまでもない。 アンダーフィルとして用い る樹脂は、 エポキシ樹脂、 フエノール樹脂、 シリコーン樹脂等を単独、 あるいは Note that, even in the semiconductor module described in this embodiment, if the user desires higher reliability, an underfill may be formed between the semiconductor module and the mounting board 10 (user board). Needless to say. The resin used as the underfill may be epoxy resin, phenol resin, silicone resin, etc.
2種類以上混合したものに、 二酸化珪素、 酸ィヒアルミニウム等の充填材ゃ、 カツ プリング剤、 着色剤、 難燃剤等を必要に応じて配合しても良い。 A filler such as silicon dioxide and aluminum aluminum oxide, a coupling agent, a coloring agent, a flame retardant, and the like may be added to a mixture of two or more kinds as necessary.
このように、 半導体モジュールとして、 貫通孔を有するガラス基板またはシリ コン基板を用いると、 絶縁基板上に高密度に配線を形成できる。 従って、 薄膜配 線層の層数を少なくできるため、 多層配線基板を薄く形成でき、 半導体モジユー ルを薄型化、 小型化することができる。  Thus, when a glass substrate or a silicon substrate having a through hole is used as a semiconductor module, wiring can be formed at a high density on an insulating substrate. Therefore, since the number of thin film wiring layers can be reduced, the multilayer wiring board can be formed thin, and the semiconductor module can be reduced in thickness and size.
また、 薄膜配線層 2の層数が少ないということは、 L S I等の半導体チップ 9 からユーザ基板 1 0への配線長が短くなるため、 より高速な信号をやり取りする ことができる。  In addition, the fact that the number of thin film wiring layers 2 is small means that the wiring length from the semiconductor chip 9 such as LSI to the user substrate 10 becomes shorter, so that higher-speed signals can be exchanged.
また、 このマルチチップモジュールを実装した電気機器、 例えば携帯電話等の 携帯端末 (情報送受信端末) やパソコン、 カーナビゲーシヨン、 デジタル zアナ ログカメラまたはビデオ等をより小型化、 高性能にすることができる。  In addition, electrical equipment equipped with this multi-chip module, such as mobile terminals (information transmission / reception terminals) such as mobile phones, personal computers, car navigation systems, digital z analog cameras, and videos, must be made smaller and have higher performance. it can.
また、 マルチチップモジュールは応力を緩和する機構を有するため、 このマル チチップモジュールをユーザの基板に実装する場合に、 アンダーフィルを省略す ることも可能であり、 電子装置を製造するユーザの作業を軽減することも可能と なる。 続いて、 多層配線基板 6および半導体モジュール 1 0 0 0の製造方法の一例に ついて説明する。 本実施例では、 絶縁基板であるガラス又はシリコン基板に応力 緩和層となる厚膜の絶縁層を形成し、 サンドプラストによって該絶縁層に貫通孔 を形成している。 Also, since the multi-chip module has a mechanism to relieve stress, it is possible to omit the underfill when mounting this multi-chip module on the user's board, and to reduce the work of the user who manufactures the electronic device. Can also be reduced. Next, an example of a method for manufacturing the multilayer wiring board 6 and the semiconductor module 100 will be described. In this embodiment, a thick insulating layer serving as a stress relieving layer is formed on a glass or silicon substrate serving as an insulating substrate, and a through hole is formed in the insulating layer by sand plasting.
基板 1として、 ガラスやシリコンを用いた場合には、 ウェハ状態で多層配線基 板 6を製作することも可能であるし、 角型の薄板状で基板製作することも可能で ある。  When glass or silicon is used as the substrate 1, the multilayer wiring substrate 6 can be manufactured in a wafer state, or the substrate can be manufactured in a square thin plate shape.
図 2 8は、 ガラス基板やシリコン基板 3 0 1を用いて多数個取りする状態を示 す。 ガラス基板やシリコン基板上に複数個のモジュール回路を形成し、 所定の半 導体装置 9 (半導体チップ） 、 抵抗、 コンデンサ等を搭載し、 外部接続端子とな るはんだボールを搭載し、 さらに必要に応じて半導体装置と基板間を樹脂で充填 する。 その後、 シリコンウェハのダイシングと同様な方法により、 各モジュール 部分を個々に切り出し所望の半導体装置を得ることが可能である。 なお、 下記で は説明を容易にするため、 多層配線基板の一部の構造を用いて説明する。  FIG. 28 shows a state in which a large number of pieces are taken using a glass substrate or a silicon substrate 301. A plurality of module circuits are formed on a glass substrate or a silicon substrate, and predetermined semiconductor devices 9 (semiconductor chips), resistors, capacitors, etc. are mounted, and solder balls as external connection terminals are mounted. Accordingly, the space between the semiconductor device and the substrate is filled with resin. Thereafter, each module portion can be cut out individually by a method similar to the dicing of a silicon wafer to obtain a desired semiconductor device. In the following, for the sake of simplicity, description will be made using a part of the structure of the multilayer wiring board.
図 1 3は、 本実施例にかかる製造方法をフローチャートで表したものである。 なお、 本実施例では、 多層配線基板の二次側の外部接続端子 (二次側バンプ 7 ) までを形成する工程を多層配線基板の製造方法としているが、 多層配線基板とし て出荷、 販売等する場合には、 二次側バンプは必ずしも形成されていなくてもよ レ、。  FIG. 13 is a flowchart illustrating the manufacturing method according to the present embodiment. In this embodiment, the process for forming the external connection terminals (secondary bumps 7) on the secondary side of the multilayer wiring board is the method of manufacturing the multilayer wiring board. In such a case, the secondary side bump does not necessarily have to be formed.
図 1 4、 図 1 5、 図 1 6は本発明による多層配線板の製造方法を説明した工程 図である。  FIG. 14, FIG. 15, and FIG. 16 are process diagrams illustrating a method for manufacturing a multilayer wiring board according to the present invention.
まず、 配線基板に用いられる絶縁基板 1として、 ガラス基板またはシリコン基 板を用意する。 必要に応じ、 表面や端面の整面処理や清浄化処理をおこなってお く。 適切な端面処理をおこなうことにより、 製造上の不良を低減できる。  First, a glass substrate or a silicon substrate is prepared as the insulating substrate 1 used for the wiring substrate. If necessary, perform surface treatment and cleaning of the front and end surfaces. Appropriate edge surface treatment can reduce manufacturing defects.
なお、 シリコンの素材そのものは導電性 （半導体〜導体） であるため、 これを 絶縁基板として用いる場合には、 その表面に絶縁性の膜を形成する必要がある。 このような膜としては、 例えば、 水蒸気中で加熱することによって表面に形成で きる熱酸化膜や、 有機樹脂膜などがある。 図 1 4、 図 1 5、 図 1 6では簡便化の ために、 シリコン基板の場合は、 その表面に形成した絶縁膜を一体化して絶縁基 板 1と表示している。 Since the silicon material itself is conductive (semiconductor to conductor), when it is used as an insulating substrate, it is necessary to form an insulating film on its surface. Examples of such a film include a thermal oxide film that can be formed on the surface by heating in steam and an organic resin film. For simplicity, Figs. 14, 15, and 16 show that in the case of a silicon substrate, the insulating film formed on the surface is integrated into an insulating substrate. Board 1 is displayed.
次に、 図 1 4 aに示すように、 絶縁基板 1の表面に配線 1 2 0を形成する。 配 線形成は例えばセミアディティブ法を用いることができる。 セミアディティブ法 で配線形成する場合、 めっき種膜を成膜する前に絶縁基板 1の表面をスパッタエ ツチ等によって清浄ィヒしておくと良い。 これにより、 基板表面と配線との密着性 を確保できる。 配線材料は導電性の観点から、 C u、 A l、 A g、 A uがよいが、 腐食性、 マイグレーション耐性、 価格を考慮すると C uが望ましい。 C uは延性 を有する材料であるため、 サンドブラスト加工のマスクとして使用することもで さる。  Next, as shown in FIG. 14A, a wiring 120 is formed on the surface of the insulating substrate 1. For the wiring formation, for example, a semi-additive method can be used. When wiring is formed by the semi-additive method, it is preferable to clean the surface of the insulating substrate 1 by sputtering or the like before forming the plating seed film. Thereby, the adhesion between the substrate surface and the wiring can be ensured. The wiring material is preferably Cu, Al, Ag, and Au from the viewpoint of conductivity, but Cu is desirable in consideration of corrosiveness, migration resistance, and price. Since Cu is a ductile material, it can be used as a mask for sandblasting.
続いて、 図 1 4 bに示すように、 配線パターンの上に層間絶縁層 1 1 0を形成 する。 層間絶縁層 1 1 0の厚みはおおむね約 5〜 5 0 mの範囲であるが、 より 好ましくは約 1 0から 2 0 μ mである。 層間絶縁層 1 1 0としてはポリアミド樹 脂、 ポリイミド樹脂、 ポリベンゾシク口ブテン樹脂、 ポリベンズォキサゾール樹 脂等を用いることができる。 絶縁基板 1上に薄膜配線層 2を 1層ずつ形成する場 合、 その薄膜配線層の層数および層の厚さは必要に応じて変化させることができ る。 各層を 1層ずつ形成することを利用して、 配線層の厚さや層間絶縁材料の厚 さ、 材質などを調整することにより、 配線の電気特性を向上させることも可能で ある。 例えば、 グランド層と信号層との間の絶縁層の絶縁材料 Aと信号層の線間 の絶縁材料 Bとで異なる誘電特性を有する材料を使用することにより、 グランド 層と信号層、 信号層同士の電気的結合の強度を調節することができ、 高速配線へ の対応が可能となる。 また、 各層間絶縁層の材質を変えることにより、 基板の厚 さ方向で線膨張係数を変化させることもできる。  Subsequently, as shown in FIG. 14b, an interlayer insulating layer 110 is formed on the wiring pattern. The thickness of the interlayer insulating layer 110 is generally in the range of about 5 to 50 m, but is more preferably about 10 to 20 μm. As the interlayer insulating layer 110, a polyamide resin, a polyimide resin, a polybenzocyclobutene resin, a polybenzoxazole resin, or the like can be used. When the thin film wiring layers 2 are formed one by one on the insulating substrate 1, the number and thickness of the thin film wiring layers can be changed as necessary. It is also possible to improve the electrical characteristics of the wiring by adjusting the thickness of the wiring layer and the thickness and material of the interlayer insulating material by utilizing the formation of each layer one by one. For example, by using materials having different dielectric properties for the insulating material A of the insulating layer between the ground layer and the signal layer and the insulating material B between the lines of the signal layer, the ground layer and the signal layer and the signal layer can be connected to each other. It is possible to adjust the strength of the electrical coupling of the wiring, and it is possible to respond to high-speed wiring. Also, by changing the material of each interlayer insulating layer, the coefficient of linear expansion can be changed in the thickness direction of the substrate.
図 1 4 bでは、 半導体チップが搭載される絶縁基板 1の面 （ 1次側） には 2層 の配線層が形成されて、 この半導体モジュールが実装される面 （2次側） には 1 層の配線層が形成された場合を示す。 なお、 絶縁基板の 1次側と 2次側で配線の 形成方法を異ならせてもよい。 すなわち、 絶縁基板の 1次側には半導体チップが 搭載されるため、 狭ピッチの配線パターンが要求される。 一方、 絶縁基板の 2次 側は実装基板 （ユーザ基板） に接続されるため、 1次側ほど狭ピッチの配線は要 求されない。 従って、 例えば狭ピッチが要求される 1次側配線ではフォトリソぉ よびめつきにより、 2次側配線を印刷によつて形成してもよレ、。 In Fig. 14b, two wiring layers are formed on the surface (primary side) of the insulating substrate 1 on which the semiconductor chip is mounted, and 1 layer is formed on the surface (secondary side) on which the semiconductor module is mounted. This shows a case where a wiring layer is formed. Note that the wiring forming method may be different between the primary side and the secondary side of the insulating substrate. In other words, since a semiconductor chip is mounted on the primary side of the insulating substrate, a narrow pitch wiring pattern is required. On the other hand, the secondary side of the insulating board is connected to the mounting board (user board), so wiring with a narrower pitch than the primary side is not required. Therefore, for example, the photolithography The secondary side wiring may be formed by printing due to the adhesion.
図 1 7、 図 3 5は、 絶縁基板 1上の 2次側の配線パターンを示したものである c 図 1 7、 図 3 5のパッドの部分のうち、 サンドプラストするときに研磨粒子があ たる部分を斜線で示している。 このように、 貫通孔 1 0 0が形成される位置を取 り巻くように鲖パッドをあらかじめ設けておくことにより、 サンドブラストによ つて絶縁基板 1の表面にマイクロクラックが生じにくくすることができ、 絶縁基 板の強度を維持することができる。 Fig. 17 and Fig. 35 show the wiring pattern on the secondary side on the insulating substrate 1. c Of the pads shown in Fig. 17 and Fig. The barrel portion is indicated by oblique lines. As described above, by providing the pad in advance so as to surround the position where the through hole 100 is formed, it is possible to reduce the occurrence of microcracks on the surface of the insulating substrate 1 by sandblasting. The strength of the insulating substrate can be maintained.
続いて、 図 1 4 cでは、 半導体モジュールがユーザ基板に実装される絶縁基板 1の面 （ 2次側） に、 ステンシル印刷ゃフォトリソグラフィ等により厚膜の絶縁 層 5を形成する。 この絶縁層 5は応力緩和層の役割を果たし、 半導体モジュール と実装基板 1 0の線膨張係数の差から生じる熱応力を緩和することができる。 な お、 所定の位置に精度良く絶縁層を形成したい場合は、 ステンシルマスクを用い てスクリーン印刷した後にレーザトリミングするなどの方法がある。  Subsequently, in FIG. 14c, a thick insulating layer 5 is formed on the surface (secondary side) of the insulating substrate 1 on which the semiconductor module is mounted on the user substrate by stencil printing / photolithography or the like. The insulating layer 5 plays a role of a stress relaxation layer, and can relieve a thermal stress caused by a difference in linear expansion coefficient between the semiconductor module and the mounting substrate 10. In order to form an insulating layer at a predetermined position with high accuracy, there is a method such as laser trimming after screen printing using a stencil mask.
次に、 図 1 5 a、 図 1 5 bの工程により、 絶縁基板 1の両面の配線層を接続す る貫通孔 1 0 0を形成する。 このとき、 応力緩和層 5と絶縁基板 1は材質 （硬 度） が異なり、 サンドプラストによって、 応力緩和層 5に貫通孔 1 0 0を形成す ることは困難である。 従って、 レーザ加工等によって応力緩和層 5に穴 （窪み部 分） を形成し、 その後サンドプラストによつて絶縁基板 1に貫通孔 1 0 0を形成 する。  Next, through-holes 100 connecting the wiring layers on both surfaces of the insulating substrate 1 are formed by the steps shown in FIGS. 15A and 15B. At this time, the material (hardness) of the stress relaxation layer 5 and the insulating substrate 1 are different, and it is difficult to form a through hole 100 in the stress relaxation layer 5 by sand blast. Therefore, a hole (dent) is formed in the stress relaxation layer 5 by laser processing or the like, and then a through hole 100 is formed in the insulating substrate 1 by sand blast.
多層配,锒基板 6に貫通孔 1 0 0を形成するためのマスクを形成する方法の代表 例は次の通りである。 第 1の方法は、 フォトリソグラフィ技術を用いる方法であ る。 具体的には、 サンドブラスト加工の際にマスクとなるブラストレジストを応 力緩和層の上に成膜し、 このプラストレジストと応力緩和層をフォトリソグラフ ィ技術により開孔する。 この開孔されたブラストレジストは、 サンドプラストに より、 応力緩和層に貫通孔を形成するためのマスクとなる。 この方法では、 ブラ ストレジストと応力緩和層の両方を一括して開孔することができる。 し力 し、 プ ラストレジストおよび応力緩和層の両方が感光性材料であることが条件である。 第 2の方法は、 レーザ加工を用いる方法である。 具体的には、 第 1の方法と同 様に、 ブラストレジストを応力緩和層の上に成膜し、 ブラストレジストと応力緩 和層をレーザ加工により一括で開孔する。 第 2の方法では、 ブラストレジスト及 び応力緩和層の感光性有無に関わらず用いることができる。 また、 この第 2の方 法で使用するプラストレジストには解像特性が必ずしも必要ではないため、 第 1 の方法と比べてブラスト耐性がより優れた材料を選択できる。 The following is a typical example of a method for forming a mask for forming the through hole 100 in the multilayer arrangement and the substrate 6. The first method is a method using a photolithography technique. Specifically, a blast resist serving as a mask during sandblasting is formed on the stress relaxation layer, and the blast resist and the stress relaxation layer are opened by photolithography. This opened blast resist becomes a mask for forming a through hole in the stress relaxation layer by the sand plast. In this method, both the blast resist and the stress relieving layer can be simultaneously opened. However, both the blast resist and the stress relieving layer must be photosensitive materials. The second method is a method using laser processing. Specifically, as in the first method, a blast resist is formed on the stress relaxation layer, and the blast resist and the stress relaxation layer are formed. The sum layer is collectively opened by laser processing. The second method can be used irrespective of the photosensitivity of the blast resist and the stress relaxation layer. Further, since the plast resist used in the second method does not necessarily need resolution characteristics, a material having more excellent blast resistance than the first method can be selected.
第 3の方法は、 第 1の方法と同様に、 感光性のブラストレジストを応力緩和層 の上に成膜し、 フォトリソグラフィにより、 ブラストレジストに開孔パターンを 形成する。 次に、 プラストレジストの開孔部を通して応力緩和層をエッチングし て応力,锾和層 5に穴 （窪み部分） を形成する。  In the third method, as in the first method, a photosensitive blast resist is formed on the stress relaxation layer, and an opening pattern is formed in the blast resist by photolithography. Next, the stress relaxation layer is etched through the opening of the plast resist to form a hole (dent) in the stress / relaxation layer 5.
上記ブラストレジストは耐熱性おょぴ耐サンドプラスト性を有することが必要 であるが、 その成膜には、 （1) 耐サンドブラスト性を有する感光性樹脂を薄膜 配線層 2上に塗布するか、 （2) 耐サンドプラスト性を有する感光性樹脂をドラ ィフィルム状としたものを貼り付ける、 などの方法がある。 なお、 貫通孔の開孔 径ゃ孔ピッチ、 およびその位置精度次第で、 マスクのパターンをスクリーン印刷 によって形成することも可能である。 その場合、 必要に応じてフォトリソグラフ ィゃレーザによる追加加工で位置精度、 加工精度の微調整することもできる。 上記第 1から第 3などの方法により、 図 1 5 aに示す形状となるが、 このとき、 形成された窪み部分が絶縁基板 1に達していてもよいが、 必ずしも達していなく ても良い。  The blast resist needs to have heat resistance and sand plast resistance. To form the film, (1) apply a photosensitive resin having sand blast resistance to the thin film wiring layer 2, or (2) A method in which a photosensitive resin having sandplast resistance in the form of a dry film is attached to the photosensitive resin. The mask pattern can be formed by screen printing depending on the opening diameter of the through holes, the hole pitch, and the positional accuracy. In such a case, if necessary, fine adjustment of the positional accuracy and the processing accuracy can be performed by additional processing using a photolithographic laser. The shape shown in FIG. 15A is obtained by the above-described first to third methods. At this time, the formed recessed portion may reach the insulating substrate 1, but does not necessarily have to reach.
続いて、 図 15 bに示すように、 同じマスクを用いて、 その応力緩和層 5の穴 (窪み部分） に対してサンドプラストを行い、 絶縁基板 1に貫通孔 100を形成 する。  Subsequently, as shown in FIG. 15B, using the same mask, sand-plasting is performed on the holes (recessed portions) of the stress relaxation layer 5 to form through holes 100 in the insulating substrate 1.
貫通孔 100を形成する条件は、 基板材質の特性、 特に基板の弾性率や破壌靭 性に応じて適宜選択する必要があるが、 比重が 2. 0~10. 0でバルク材の曲 げ強度が 0. 1〜2. OGP aとなるような加工粒体を使用することが望まし!/、。 加工粒体の粒径が大きくなるほど加工速度は速くなりやすいが、 逆に後述するマ イク口クラックゃチッピングの問題が発生しゃすレ、傾向がある。  The conditions for forming the through-holes 100 must be appropriately selected according to the characteristics of the substrate material, particularly the elastic modulus and rupture toughness of the substrate, but when the specific gravity is 2.0 to 10.0, the bulk material is bent. It is desirable to use processed granules having a strength of 0.1 to 2. OGP a! The processing speed tends to increase as the grain size of the processed grains increases, but on the contrary, the problem of crack opening cracking and chipping described later tends to occur.
本実施例では、 基板材質や貫通孔の加工寸法 （厚み、 径） 、 所望の加工速度な どを考慮して加工粉体の粒径 （#) を決定するが、 # 1 50〜 # 2000の範囲 であることが望ましい。 本実施例では # 500、 # 600、 # 700、 # 800、 # 9 0 0、 # 1 0 0 0、 # 1 1 0 0、 # 1 2 0 0のいずれか、 あるいはそれらを 適宜組み合わせて使用した。 なお、 加工粉体は循環 ·再利用するが、 使用してい る間に互いに衝突して破碎しあうので、 粒径が上記範囲を維持するように適宜分 球すると良い。 また、 基板の貫通孔部分の破碎粉等も混入するので、 必要に応じ、 これを除去する。 In the present embodiment, the particle size (#) of the processing powder is determined in consideration of the substrate material, the processing size (thickness, diameter) of the through hole, the desired processing speed, and the like. It is desirable to be within the range. In this embodiment, # 500, # 600, # 700, # 800, Any of # 900, # 10000, # 1100, # 1200, or a combination thereof was used as appropriate. Although the processed powder is circulated and reused, it collides with each other and shatters during use. Therefore, it is advisable to appropriately size the powder so that the particle size is maintained in the above range. In addition, crushed powder from the through-hole portion of the substrate is also mixed in. If necessary, this is removed.
従って、 本実施例において貫通孔形成に使用するサンドブラストマシンは、 循 環 '再利用機構と、 分球機構とを備えていることが望ましい。 加工粉体の循環 ' 再利用や分球が貫通孔加工と同時並行で自動的に運転されるように設定されてい るサンドプラストマシンを使用すると実用的である。  Therefore, it is desirable that the sandblasting machine used for forming the through-holes in the present embodiment has a circulation / reuse mechanism and a spheroid mechanism. It is practical to use a sandplast machine that is set up so that the recycle and spheroids are automatically operated in parallel with the processing of through holes.
なお、 フォトエッチングやレーザ加工で応力緩和層に孔を設けた場合、 絶縁基 板 1の表面に樹脂加工残さが残ることがあるが、 絶縁基板 1に行うサンドブラス ト加工の際に一緒に除去される。 通常レーザ加工により樹脂に孔を形成すると、 配線接続信頼性低下の原因となる樹脂の残留 （スミア） が形成され、 化学処理等 によるデスミァ処理を行う工程が必要となる。 本実施例の製造工程では、 レーザ 加工で形成した窪み部分に対してサンドプラストするため、 サンドブラストの段 階でスミアを除去することができ、 化学的なデスミァ処理を行う必要がない。 サンドプラストにより貫通孔 1 0 0を形成すると、 一方の開口端から他方の開 口端で、 貫通孔 1 0 0の径の大きさは異なるように形成されるが、 このようにテ ーパを有することにより、 スパッタゃ無電解めつき等の成膜方法により貫通孔 1 0 0の内面に給電膜が形成され易くなる。  When holes are formed in the stress relaxation layer by photoetching or laser processing, resin processing residue may remain on the surface of the insulating substrate 1, but the resin processing residue may be removed during the sandblasting performed on the insulating substrate 1. Is done. Normally, when holes are formed in a resin by laser processing, resin residues (smears) that cause a reduction in wiring connection reliability are formed, and a process of desmearing by chemical treatment or the like is required. In the manufacturing process of the present embodiment, since the dent portion formed by the laser processing is sandblasted, the smear can be removed at the sandblasting stage, and there is no need to perform a chemical desmear process. When the through hole 100 is formed by sand plast, the diameter of the through hole 100 is formed to be different from one opening end to the other opening end. With this, the power supply film is easily formed on the inner surface of the through hole 100 by a film forming method such as sputtering and electroless plating.
応力緩和層 5が形成されていない絶縁基板 1の面 （1次側） において、 貫通孔 1 0 0が形成される位置にあらかじめ鲖配線を形成しておくと、 サンドブラスト が絶縁基板 1を貫通した後に、 サンドブラストによって一次側の層間絶縁層 1 1 0 (薄膜配,锒層 2 ) が削られることを防止することができる。  If a wire is formed in advance on the surface (primary side) of the insulating substrate 1 where the stress relaxation layer 5 is not formed at the position where the through hole 100 is formed, the sandblast penetrates the insulating substrate 1 Later, it is possible to prevent the primary-side interlayer insulating layer 110 (thin film layer, second layer 2) from being cut by sandblasting.
貫通孔 1 0 0が形成された後、 エッチング等によりマスクを除去する。  After the through holes 100 are formed, the mask is removed by etching or the like.
続いて、 必要に応じて、 貫通孔 1 0 0を形成する過程で絶縁基板 1の貫通孔 1 0 0周辺に生じたマイクロクラックを除去する。  Subsequently, if necessary, microcracks generated around the through hole 100 of the insulating substrate 1 in the process of forming the through hole 100 are removed.
絶縁基板 1に生じるマイクロクラックは、 大きく分けるといわゆるメディアン クラックとラテラルクラックと呼ばれる 2種類に分類される。 メディアンクラッ クは貫通孔側壁面に対して深さ方向にのびているクラックであり、 一方、 ラテラ ルクラックは貫通孔側壁面に対して沿面方向にのびるものである。 The micro cracks generated in the insulating substrate 1 are roughly classified into two types, so-called median cracks and lateral cracks. Median crack Cracks are cracks extending in the depth direction with respect to the side wall surface of the through hole, while lateral cracks extend in the creepage direction with respect to the side wall surface of the through hole.
我々の実験によると、 ラテラルクラックの発生状況がサンドブラストによる貫 通孔加工の能率に影響を与えるものと推測され、 ラテラルクラックが発生しやす くなるような加工条件を選択することによりサンドプラストの加工能率が増大す る。 一方、 メディアンクラックは貫通孔壁面に対して深さ方向にのぴており、 我 々の実験によるとメディアンクラックが多くなるほど基板強度、 特に抗折強度が 低下しゃすレ、傾向があつた。  According to our experiments, it is assumed that the occurrence of lateral cracks will affect the efficiency of through-hole drilling by sandblasting. Efficiency increases. On the other hand, the median crack extends in the depth direction with respect to the wall surface of the through-hole. According to our experiments, the more the median crack, the lower the substrate strength, especially the bending strength.
従って、 本実施例では、 ラテラルクラックが発生しやすく、 メディアンクラッ クが発生しにくいようなサンドプラスト条件を選定することが肝要である。 我々 の実験によると、 ラテラルクラックとメディアンクラックの発生比率は、 ( 1 ) 加工粒体の硬度、 （2 ) 加工粒体の形状、 （3 ) 加工粒体の粒径、 （4 ) 加工粒 体が被加工物へ単位時間に衝突する回数、 （ 5 ) 加工粒体が被加工物に衝突する 角度、 （6 ) 加工粒体を搬送する気体の圧力、 等に依存していることがわかった。 従って、 単位時間の衝突回数や衝突角度、 搬送気体の圧力などを調整できるよう なノズルを有しているプラストマシンを使用すると良い。 適切なブラストマシン と加工条件を選ぶと加工能率と基板強度とを両立できる。  Therefore, in this embodiment, it is important to select sandplast conditions that cause lateral cracks and median cracks are less likely to occur. According to our experiments, the rate of occurrence of lateral cracks and median cracks is (1) hardness of processed grains, (2) shape of processed grains, (3) grain size of processed grains, (4) processed grains. It depends on the number of times the object collides with the workpiece in a unit time, (5) the angle at which the processed particles collide with the workpiece, and (6) the pressure of the gas transporting the processed particles. . Therefore, it is preferable to use a plast machine having a nozzle capable of adjusting the number of collisions per unit time, the collision angle, the pressure of the carrier gas, and the like. By selecting an appropriate blasting machine and processing conditions, both processing efficiency and substrate strength can be achieved.
しかしながら、 メディアンクラックが全く発生させないようにすることは実用 上困難であり、 仮にメディアンクラックを全く発生させなかつたとしても、 ラテ ラルクラックを起点に亀裂進展すると基板強度が低下して破損するおそれがある ため、 貫通孔形成後にはマイクロクラックを除去する工程を入れておくことが望 ましい。  However, it is practically difficult to prevent the generation of median cracks. Therefore, it is desirable to include a step of removing microcracks after the formation of the through-hole.
我々の実験によると貫通孔壁面の最表面を組成流動領域での機械加工や、 化学 的処理などで整面するなどの方法で貫通孔壁面の表面を除去してやれば、 マイク 口クラックが除去できる。 あるいは、 ガラス基板の場合には、 少なくとも貫通孔 周囲を軟化〜溶融温度まで加熱して自己融着させるなどの処理を施して、 マイク 口クラックを除去することもできる。 貫通孔周囲を加熱する方法として、 例えば、 レーザーァニールなどの方法が挙げられる。 あるいは、 ガラス基板全体を加熱し 口クラックを自己融着させた後にゆつく り冷却すると、 孔加工時にガラ ス基板内に蓄積されたひずみが開放されるので、 基板割れによる不良率を低下さ せることができる。 According to our experiments, if the outer surface of the through-hole wall is removed by machining the outermost surface of the through-hole wall in the composition flow region or by chemical treatment, the cracks in the microphone opening can be removed. Alternatively, in the case of a glass substrate, it is also possible to remove the microphone opening cracks by performing a process such as heating at least the periphery of the through-hole to the melting temperature and self-fusion. Examples of a method for heating the periphery of the through hole include a method such as laser annealing. Alternatively, if the entire glass substrate is heated and the mouth cracks are self-fused and then cooled slowly, Since the strain accumulated in the substrate is released, the failure rate due to substrate cracking can be reduced.
続いて、 図 1 6に示すように、 絶縁基板 1の 1次側と 2次側の配線層を電気的 に接続するため、 貫通孔 1 0 0の内壁面および多層配線基板の最表面に配線を形 成する。  Subsequently, as shown in FIG. 16, in order to electrically connect the wiring layers on the primary side and the secondary side of the insulating substrate 1, wiring is performed on the inner wall surface of the through hole 100 and the outermost surface of the multilayer wiring board. Is formed.
本実施例に好適な配線形成方法はいくつかあげられる。 以下には、 その代表例 を例示する。 第 1の方法では、 まず、 貫通孔 1 0 0の内壁に給電膜をスパッタゃ C VD、 蒸着などの方法により形成する。 給電膜としては、 例えばクロム Z銅の 多層膜が好ましいが、 チタン/銅の多層膜などめつき給電膜として公知慣用の膜 構成であればどれでも良い。 ここで、 クロムの機能は、 基板と銅との接着を確保 することであり、 その膜厚は、 7 5ナノメートル程度であり、 最大でも 0 . 5マ イク口メートル程度である。 一方、 給電膜の銅の膜厚は 0 . 5マイクロメートル 程度、 最大で 1マイクロメートルである。 給電膜の形成後、 絶縁基板 1の表面に めっきレジストを成膜し、 フォトリソグラフィ技術により、 配線の逆パターンと なるめっきマスクを形成した後、 電気めつきにより給電膜の上に配線を形成する。 レジスト除去、 めっき種膜除去を経て、 配線間に絶縁膜 （線間絶縁膜） を形成す る。 なお図 2は、 基板最表面における配線間絶縁膜 （線間絶縁膜） の形成前の状 態を示している。  There are several suitable wiring forming methods for this embodiment. The following is a typical example. In the first method, first, a power supply film is formed on the inner wall of the through hole 100 by a method such as sputtering CVD or vapor deposition. As the power supply film, for example, a multilayer film of chromium Z copper is preferable, but any known and commonly used film configuration as a plating power supply film such as a titanium / copper multilayer film may be used. Here, the function of chromium is to ensure adhesion between the substrate and copper, and its film thickness is about 75 nanometers, and at most about 0.5 micrometer. On the other hand, the thickness of the copper of the power supply film is about 0.5 μm, up to 1 μm. After forming the power supply film, a plating resist is formed on the surface of the insulating substrate 1, a plating mask that is a reverse pattern of the wiring is formed by photolithography technology, and then the wiring is formed on the power supply film by electroplating. . After removing the resist and removing the plating seed film, an insulating film (inter-line insulating film) is formed between the wirings. FIG. 2 shows the state before the formation of the inter-wiring insulating film (inter-wiring insulating film) on the outermost surface of the substrate.
第 2の方法は配線形成にサブトラクティブ法を用いる。 配線として、 クロム/ 銅などからなる多層膜をスパッタ成膜するところまでは第 1の方法と同じである 力 その後、 全面にめっきを施してから、 絶縁基板の表裏にエッチングレジスト を成膜、 フォトリソグラフィ技術によりエッチングマスクパターンを形成する。 エッチングによって配線を形成した後、 レジスト除去、 線間絶縁膜を形成する。 第 3の方法では、 貫通孔内部に導電性材料を充填する。 導電材料充填には、 例 えば、 ペースト印刷などが用いられる。 なお、 導電材料充填に先立って上記 2つ の方法と同様に貫通孔内壁にスパッタ成膜してもよい。 内壁表面にスパッタ膜を 形成すると、 （1 ) 内壁表面の平滑性向上による充填性の改善、 （2 ) 充填材と 絶縁基板との密着性向上、 などの効果がある。  The second method uses a subtractive method for forming wiring. The same method as in the first method up to the point where a multilayer film made of chromium / copper etc. is formed by sputtering as the wiring force.After that, plating is performed on the entire surface, and then etching resist is formed on the front and back of the insulating substrate. An etching mask pattern is formed by a lithography technique. After wiring is formed by etching, the resist is removed and an inter-line insulating film is formed. In the third method, the inside of the through hole is filled with a conductive material. For example, paste printing or the like is used for filling the conductive material. Prior to filling the conductive material, a sputter film may be formed on the inner wall of the through hole in the same manner as in the above two methods. Forming a sputtered film on the inner wall surface has the following effects: (1) improving the filling property by improving the smoothness of the inner wall surface; and (2) improving the adhesion between the filler and the insulating substrate.
その場合に成膜するスパッタ膜は、 第 1や第 2の方法と同様のク口ム /銅の多 層膜でもよいし、 単層膜でも構わない。 導電性材料としてはんだを使用する場合 には、 絶縁基板との密着性を確保するためのクロムやチタンなどの膜とはんだの 濡れ性を確保するための銅やニッケル、 金などの膜との積層膜であることが望ま しレ、。 貫通孔内部の導電材料充填のあとは、 セミアディティプ法かサブトラクテ イブ法によって基板表面に配線を形成する。 なお、 配線パターンによっては、 ぺ ースト印刷によつて貫通孔充填と配線パターン形成とを一括で達成できる場合も ある。 In this case, the sputter film to be formed should have a large amount of copper / copper as in the first and second methods. It may be a layer film or a single layer film. If solder is used as the conductive material, laminate a film of chromium or titanium to ensure adhesion to the insulating substrate and a film of copper, nickel, or gold to ensure solder wettability. Desirably, it is a membrane. After filling the conductive material inside the through-hole, wiring is formed on the substrate surface by the semi-additive method or the subtractive method. Note that, depending on the wiring pattern, filling of the through-holes and formation of the wiring pattern may be achieved in a batch by paste printing.
上記第 1力 ら第 3の方法を単独、 あるいは適宜組み合わせて使用することで、 基板の表裏を接続する貫通孔の導通配線と基板表面 （2次側） の配線とを形成す る。 基板表面の配線は、 必要な層数積層するが、 電気抵抗の観点から銅配線であ ることが望ましい。 また、 必要に応じて、 密着信頼性、 絶縁信頼性などの観点か ら、 銅の表面に異種金属を成膜することがある。  By using the first force to the third method individually or in an appropriate combination, a conductive wiring of a through hole connecting the front and back of the substrate and a wiring on the substrate surface (secondary side) are formed. The wiring on the substrate surface is laminated in a required number of layers, but is preferably copper wiring from the viewpoint of electric resistance. If necessary, a heterogeneous metal may be formed on the copper surface from the viewpoint of adhesion reliability, insulation reliability, and the like.
なお、 絶縁基板 1がガラス基板の場合、 ガラスは絶縁性を有する素材であるた め、 貫通孔内壁に直接接触するように配線等を形成しても問題はないが、 密着性 や絶縁信頼性、 耐マイグレーション性、 耐湿性などの観点から、 貫通孔内壁面の 表面を覆うように絶縁層を形成してもよい。 一方、 絶縁基板 1がシリコン基板の 場合には、 シリコンが導電性を有しているため、 配線基板 1の表裏を接続するた めの配線を形成するに先立って貫通孔内壁面表面を覆うように絶縁層を設ける必 要がある。  When the insulating substrate 1 is a glass substrate, since glass is a material having an insulating property, there is no problem if wiring or the like is formed so as to directly contact the inner wall of the through-hole. From the viewpoints of migration resistance, moisture resistance, and the like, an insulating layer may be formed so as to cover the surface of the inner wall surface of the through hole. On the other hand, when the insulating substrate 1 is a silicon substrate, since the silicon has conductivity, the inner wall surface of the through-hole should be covered before forming the wiring for connecting the front and back of the wiring substrate 1. It is necessary to provide an insulating layer on the surface.
以上の工程により、 貫通孔 1 0 0を有する多層配線基板 6を形成することがで きる。 このように多層配線基板を多面取りできる状態で出荷してもよいし、 さら に多層配線基板をダイシングして個別化して出荷してもよい。 多層配線基板をダ ィシングせずに出荷する場合は、 後の半導体チップ等を実装し、 マルチチップモ ジュールを形成した後にダイシングしてもよい。  Through the above steps, the multilayer wiring board 6 having the through holes 100 can be formed. As described above, the multilayer wiring board may be shipped in a state in which multiple boards can be obtained, or the multilayer wiring board may be diced and individually shipped. When the multilayer wiring board is shipped without dicing, dicing may be performed after mounting a semiconductor chip or the like to form a multi-chip module.
図 3に示すように、 はんだパンプ等の外部接続端子 3 0 0ゃ異方導電性シート (A C F ) を用いて、 多層配線基板 6に半導体装置 9およびコンデンサ等を実装 し、 半導体モジュールを形成する。 多層配線基板 6の 2次側には、 この半導体モ ジュール 1 0 0 0を実装基板 1 0に実装するため外部接続端子、 例えばはんだバ ( 2次接続用バンプ） を形成する。 例えば、 まず、 配線基板の 1次側に半導体装置 9の外部端子ピッチに応じては んだバンプ （1次側バンプ） を形成する。 バンプピッチは一般に約 5 0〜5 0 0 μ ιηの範囲になることが多い。 バンプサイズは前記バンプピッチに対して約 1 5 〜 8 0 %、 望ましくは、 約 3 0〜 6 5 %になるように調整する。 As shown in FIG. 3, a semiconductor module 9 is formed by mounting a semiconductor device 9 and a capacitor on a multilayer wiring board 6 using an external connection terminal 300 such as a solder pump or the like and an anisotropic conductive sheet (ACF). . On the secondary side of the multilayer wiring board 6, external connection terminals, for example, solder bars (bumps for secondary connection) are formed to mount the semiconductor module 100 on the mounting board 10. For example, first, solder bumps (primary-side bumps) are formed on the primary side of the wiring board in accordance with the external terminal pitch of the semiconductor device 9. The bump pitch is generally in the range of about 50 to 500 μιη. The bump size is adjusted to be about 15 to 80%, preferably about 30 to 65% with respect to the bump pitch.
続いて、 形成された 1次バンプを用いて、 多層配線基板 6に半導体装置 9を実 装する。 この 1次側バンプのピッチは約 5 0から 5 0 0 μ m程度である。 配線基 板 6と半導体装置 9とは線膨脹係数の差は小さいが、 必要に応じて、 配線基板 6 と半導体装置 9との間にアンダーフィル剤を充填したり、 半導体装置 9の上部に ポッティング材を塗布してもよい。 バンプサイズが 2 0 0マイクロメータ以下と いう微少なバンプになると、 バンプの体積が小さくなつたことにより機械的強度 が低下する場合があるが、 その場合にはアンダーフィル剤ゃポッティング材を単 独あるいは組み合わせて使用することによって信頼性低下などの問題は起こらな レ、。  Subsequently, the semiconductor device 9 is mounted on the multilayer wiring board 6 using the formed primary bumps. The pitch of the primary side bumps is about 50 to 500 μm. Although the difference in the coefficient of linear expansion between the wiring board 6 and the semiconductor device 9 is small, if necessary, an underfill agent is filled between the wiring substrate 6 and the semiconductor device 9 or potting is performed on the upper portion of the semiconductor device 9. A material may be applied. If the bump size is as small as 200 micrometers or less, the mechanical strength may decrease due to the reduction in the volume of the bump. In this case, the underfill agent and the potting material must be used alone. Or, if used in combination, problems such as reduced reliability will not occur.
そして、 半導体モジュールを実装基板 1 0に実装するためのバンプ 7 ( 2次側 バンプ） を形成する。  Then, bumps 7 (secondary side bumps) for mounting the semiconductor module on the mounting board 10 are formed.
これにより、 半導体装置 9 (半導体チップ） の配線と、 一次側バンプ 7が電気 的に接続され、 また多層配 基板 6によりファインピッチが実現される。  As a result, the wiring of the semiconductor device 9 (semiconductor chip) is electrically connected to the primary-side bump 7, and a fine pitch is realized by the multilayer wiring board 6.
なお、 上記では半導体モジュールを実装基板 1 0に実装するためのバンプ 7 ( 2次側バンプ） を一次側のバンプ形成後に形成している。'しかし、 必要に応じ て、 二次側バンプを形成後に、 一次側バンプを形成してもよい。 例えば、 半導体 装置 9と多層配線基板 6、 半導体モジュールと実装基板 1 0をともにはんだバン プで形成する場合、 はんだバンプ 7 (二次側バンプ） の融点が、 はんだバンプ 3 0 0 (—次側バンプ） の融点よりも低いときには、 1次側接続の後で 2次側接続 を行なう。 つまり、 はんだバンプ 3 0 0を形成し、 半導体チップ 9を実装した後 に、 はんだバンプ 7を形成して、 半導体モジュールを実装基板 1 0に実装するの がよい。  In the above description, the bump 7 (secondary bump) for mounting the semiconductor module on the mounting substrate 10 is formed after the formation of the primary bump. 'However, if necessary, the primary side bump may be formed after the secondary side bump is formed. For example, when the semiconductor device 9 and the multilayer wiring board 6 and the semiconductor module and the mounting board 10 are both formed by solder bumps, the melting point of the solder bump 7 (secondary side bump) becomes When the melting point is lower than the melting point of the bump, perform the secondary connection after the primary connection. That is, after forming the solder bumps 300 and mounting the semiconductor chip 9, it is preferable to form the solder bumps 7 and mount the semiconductor module on the mounting board 10.
また、 図 3では、 半導体装置 9は 2つ記載されているが、 半導体装置 9の数は 任意であり、 複数の半導体装置 9 (半導体チップ等） を多層配線基板 6に実装し、 いわゆるマルチチップモジュールを形成することもできることは言うまでもなレ、。 本実施例にかかる製造方法では、 サンドプラストにより貫通孔 1 0 0を開ける ため、 高コストな感光性ガラスを基板材料として用いる必要はなく、 低コストな ガラス基板、 シリコン基板を用いて配線基板おょぴ多層配線基板を製造すること ができる。 In FIG. 3, although two semiconductor devices 9 are shown, the number of the semiconductor devices 9 is arbitrary, and a plurality of semiconductor devices 9 (semiconductor chips and the like) are mounted on the multilayer wiring board 6 to form a so-called multi-chip It goes without saying that modules can be formed. In the manufacturing method according to the present embodiment, since the through-holes 100 are opened by the sandplast, it is not necessary to use a high-cost photosensitive glass as a substrate material. A multilayer wiring board can be manufactured.
また、 絶縁基板 1の二次側で、 サンドプラストにより形成される貫通孔 1 0 0 の位置に、 あらかじめ銅パッドを形成することにより、 絶縁基板 1にマイクロク ラックが発生しにくくすることができる。  In addition, by forming a copper pad in advance on the secondary side of the insulating substrate 1 at the position of the through hole 100 formed by sandplast, it is possible to reduce the occurrence of microcracks on the insulating substrate 1. .
また、 絶縁基板 1の一次側で、 サンドプラストにより形成される貫通孔 1 0 0 の位置に、 あらかじめ銅配線を形成することにより、 層間絶縁層 1 1 0が侵食さ れることを防止できる。  Further, by forming a copper wiring in advance on the primary side of the insulating substrate 1 at the position of the through hole 100 formed by sandplast, it is possible to prevent the interlayer insulating layer 110 from being eroded.
続いて、 多層配線基板 6の他の製造方法について説明する。 図 1 8は、 本実施 例にかかる製造方法をフローチャートで表したものである。 第一の実施例と主に 異なるところは、 絶縁基板 1に形成する貫通孔 1 0 0の工程の順番である。 まず、 第一の実施例と同様、 配線基板に用いられる絶縁基板 1として、 ガラス 基板またはシリコン基板を用意し、 必要に応じ、 表面や端面の整面処理や清浄化 処理、 表面絶縁化処理をおこなっておく。  Subsequently, another manufacturing method of the multilayer wiring board 6 will be described. FIG. 18 is a flowchart illustrating the manufacturing method according to the present embodiment. The main difference from the first embodiment is the order of the process of forming the through holes 100 in the insulating substrate 1. First, as in the first embodiment, a glass substrate or a silicon substrate is prepared as the insulating substrate 1 used for the wiring substrate, and if necessary, the surface and the end surface are subjected to surface conditioning treatment, cleaning treatment, and surface insulation treatment. I'll do it.
続いて、 図 1 9 aに示すように、 第一の実施例と同様にサンドブラストにより 絶縁基板 1にのみ貫通孔 1 0 0を形成する。 このサンドプラストにより、 絶縁基 板 1にはマイクロクラックが発生する。  Subsequently, as shown in FIG. 19a, through holes 100 are formed only in the insulating substrate 1 by sandblasting as in the first embodiment. Due to this sand blast, microcracks are generated on the insulating substrate 1.
続いて、 絶縁基板 1に発生したマイクロクラックを第一の実施例と同様の方法 で除去する。  Subsequently, microcracks generated on the insulating substrate 1 are removed by the same method as in the first embodiment.
続いて、 図 1 9 bに示すように、 絶縁基板 1の貫通孔 1 0 0および絶縁基板 1 の上に配,锒 1 2 0を形成する。 上記実施例 1と同様にセミアディティブ法やサブ 'トラクティブ法などを用いて配線形成できる。  Subsequently, as shown in FIG. 19b, a hole 120 is formed on the through-hole 100 of the insulating substrate 1 and the insulating substrate 1. Similar to the first embodiment, the wiring can be formed by using a semi-additive method or a subtractive method.
上記実施例 1と異なる点は、 貫通孔 1 0 0内面およぴ絶縁基板 1の表裏 （ 1次 面、 2次面） の 3面に給電膜を形成することである。 給電膜は基板の両面から同 時に成膜しても良いし、 1次面、 2次面と片側ずつ成膜しても良い。 3面に同時 形成するという観点からみると、 無電解めつき法が効率的である。 スパッタによ り給電膜を形成する場合は、 基板の表裏へ成膜、 特に 2次面への給電膜の成膜と 同時に貫通孔内壁への給電膜の形成が達成できる。 給電膜としては上記第 1の実 施例と同様、 例えば、 クロム膜 Z銅の多層膜などがあげられる。 給電膜形成後の 配線形成方法としては次の 2通りの方法がある。 The difference from the first embodiment is that a power supply film is formed on the inner surface of the through hole 100 and the three surfaces of the front and back surfaces (the primary surface and the secondary surface) of the insulating substrate 1. The power supply film may be formed from both sides of the substrate at the same time, or may be formed on the primary surface and the secondary surface one by one. From the viewpoint of simultaneous formation on three surfaces, the electroless plating method is more efficient. When the power supply film is formed by sputtering, the film is formed on the front and back of the substrate, especially when the power supply film is formed on the secondary surface. At the same time, the formation of the power supply film on the inner wall of the through hole can be achieved. Examples of the power supply film include a chromium film and a multilayer film of copper as in the first embodiment. There are the following two methods for forming wiring after forming the power supply film.
第 1の方法はセミアディティブプロセスである。 絶縁基板 1の表裏 （ 1次面お よび 2次面） にめつきレジストを成膜し、 フォトリソグラフィ技術により所望の めっき配線の反転パターンとなるレジストパターンを形成し、 しかる後にめっき によつて配線を形成する。 貫通孔上部のレジストを開口しておくことにより、 貫 通孔 1 0 0内壁と基板の表裏とを一括してめっきできる。 常法通りのパターン分 離工程で、 貫通孔内壁配線と基板表裏の配線とを一気にパターン分離できる。 配 線材料としては、 C u、 A l、 A g、 A u、 N i等があげられる。  The first is a semi-additive process. A resist is formed on the front and back surfaces (primary and secondary surfaces) of the insulating substrate 1, and a resist pattern that is the reverse pattern of the desired plating wiring is formed by photolithography technology, and then the wiring is formed by plating To form By opening the resist above the through-hole, the inner wall of the through-hole 100 and the front and back of the substrate can be collectively plated. In the pattern separation process as usual, the pattern can be separated at a stroke between the wiring on the inner wall of the through hole and the wiring on the front and back of the substrate. Examples of the wiring material include Cu, Al, Ag, Au, and Ni.
第 2の方法はサブトラクティブプロセスである。 常法通りのめっき処理により、 貫通孔 1 0 0内壁と基板の表裏とを一括してめっきできる。 このめつき膜の上に エッチングレジストを成膜し、 フォトリソグラフィ技術により所望の配；?泉の反転 パターンとなるレジストパターンを形成し、 しかる後にエッチングによって配線 を分離する。 配線材料は第 1の方法と同様、 C u、 A 1、 A g、 A u、 N i等で ある。  The second method is a subtractive process. By the usual plating treatment, the inner wall of the through-hole 100 and the front and back surfaces of the substrate can be collectively plated. An etching resist is formed on the plating film, and a resist pattern serving as a reverse pattern of a desired distribution is formed by a photolithography technique. Thereafter, the wiring is separated by etching. The wiring material is Cu, A1, Ag, Au, Ni, etc., as in the first method.
このように、 本実施例では貫通孔 1 0 0内壁と基板の表裏 （ 1次面おょぴ 2次 面） の配線形成を一括で処理できるため、 露光、 現像、 めっきの工数を大きく削 減できる。  As described above, in this embodiment, since the formation of the wiring on the inner wall of the through hole 100 and the front and back surfaces of the substrate (primary surface and secondary surface) can be collectively processed, the man-hours for exposure, development, and plating are greatly reduced. it can.
続いて、 図 1 9 cに示すように、 貫通孔 1 0 0に充填材を充填する。 充填材は 必ずしも導電性材料である必要はなく、 絶縁材料であっても良い。 ペースト印刷 などの簡便な充填方法で充填できるような充填性の高い材料であることが望まし レ、。 一度の印刷で貫通孔 1 0 0に充填できない場合は、 複数回印刷する必要があ る。  Subsequently, as shown in FIG. 19c, the through-hole 100 is filled with a filler. The filler need not necessarily be a conductive material, but may be an insulating material. It is desirable that the material has a high filling property that can be filled by a simple filling method such as paste printing. If it is not possible to fill the through hole 100 with one printing, it is necessary to print several times.
図 2 1は実際にペースト印刷を 5回行って貫通孔 1 0 0を充填したときに、 貫 通孔 1 0 0の中央に未充填の部分 （以下、 未充填ボイド 2 0 0という） が形成さ れた様子を示している。 このような未充填ボイド 2 0 0を内包するような絶縁基 板では、 製造プロセス中の温度変化、 例えば、 絶縁膜成膜工程や半田付け工程な どでの温度変化の度に、 ボイド内の空気の膨張収縮が起こるため貫通孔内壁の配 線の断線が起こりやすくなったり、 絶縁基板内部にひずみが集積して絶縁基板 1 の強度が低下する恐れがある。 また、 第 1回目の印刷工程で未充填ボイド 2 0 0 ができると、 2回目以降の印刷時に、 ペーストへの圧力の一部がボイドの圧縮と いう形で逃げてしまうので、 印刷圧が不足し、 その結果完全な充填できなくなる。 開口部の径が小さくなる絶縁基板 1の 1次側端面付近では圧損が大きいので、 印 刷圧が不足した場合には 1次側端面付近で未充填部分 2 0 1ができてしまうこと もある。 Figure 21 shows an unfilled part (hereinafter referred to as unfilled void 200) in the center of through-hole 100 when paste printing was performed 5 times to fill through-hole 100. This shows the appearance. In the case of such an insulating substrate that contains such unfilled voids 200, every time a temperature change occurs during the manufacturing process, for example, a temperature change in an insulating film forming step, a soldering step, or the like, the inside of the void is changed. Since the expansion and contraction of air occurs, The wire may be easily broken, or the strain may accumulate inside the insulating substrate, and the strength of the insulating substrate 1 may be reduced. In addition, if unfilled voids 200 are formed in the first printing process, a part of the pressure on the paste will escape in the form of void compression during the second and subsequent printing, resulting in insufficient printing pressure. As a result, complete filling is not possible. Since the pressure loss is large near the primary end face of the insulating substrate 1 where the diameter of the opening is small, if the printing pressure is insufficient, an unfilled portion 201 may be formed near the primary end face. .
さらに、 未充填ボイド 2 0 0を内包する貫通孔の上部には、 ポリイミドゃポリ ベンゾシク口ブテンなどの層間絶縁膜、 線間絶縁膜を精密に成膜することが困難 となる。 絶縁膜の硬化過程で加熱する際にボイドが膨張し、 その影響を受けて基 板表面に存在していて硬化途上にある絶縁層を変形させるためである。  Further, it becomes difficult to precisely form an interlayer insulating film such as polyimide / polybenzobutene or a line insulating film above the through hole including the unfilled void 200. This is because the void expands when heated in the process of curing the insulating film, and under the influence, the insulating layer present on the substrate surface and being cured is deformed.
絶縁基板 1の 1次側端面付近で発生する未充填部分 2 0 1の上には、 次の工程 で形成される層間絶縁層を平坦に形成することは困難である。 その解決策の一つ としては、 未充填ボイドを貫通孔内に形成しないことであり、 それには貫通孔裏 面から吸引しながらペース ト印刷することが有効である。 また揮発成分を含まな V、材料もしくは揮発成分の含有量が少ない絶縁性物質でペースト印刷したり、 あ るいは、 ペースト印刷後に基板全体を減圧してボイドを除去した後静水圧を作用 させるなどの処理が有効である。 例えば絶縁性物質として無溶剤ワニスが有効で ある。  On the unfilled portion 201 generated near the primary end face of the insulating substrate 1, it is difficult to form a flat interlayer insulating layer formed in the next step. One solution is to avoid the formation of unfilled voids in the through-holes. For this purpose, it is effective to perform paste printing while suctioning from the back of the through-holes. In addition, paste printing is performed using V that does not contain volatile components, insulating material that has a low content of materials or volatile components, or applying hydrostatic pressure after depressurizing the entire board after paste printing to remove voids, etc. Is effective. For example, a solventless varnish is effective as an insulating material.
他の解決策としては、 絶縁基板 1の上に配線を形成するに先だって、 導電性材 料等を 1次側端面付近で発生する未充填部分 2 0 1のくぼみに塗布することであ る。 このようにすれば、 未充填部分 2 0 1があったとしても、 絶縁基板 1上は平 坦になる。 導電性材料として銀ペーストなどを使用して、 これを未充填部分 2 0 1のくぼみに印刷すればよい。  Another solution is to apply a conductive material or the like to the hollow of the unfilled portion 201 generated near the primary end face before forming the wiring on the insulating substrate 1. By doing so, even if there is an unfilled portion 201, the surface on the insulating substrate 1 becomes flat. What is necessary is just to use silver paste etc. as a conductive material, and to print this in the hollow of the unfilled part 201.
続いて、 図 2 0 aに示すように、 貫通孔 1 0 0が充填された絶縁基板 1に、 配 線 1 2 0と層間絶縁層 1 1 0を有する薄膜配線層 2からなる多層配線層 3を形成 する。 配線形成工程そのものは、 前記第 1の実施例と本質的には同じである。 続いて、 図 2 O bに示すように、 必要に応じて、 応力緩和層 5を形成し、 さら に応力緩和層 5にフォトエッチングまたはレーザ加工等により孔 （ビアホール） を形成する。 応力緩和層 5形成工程そのものは、 前記第 1の実施例と本質的には 同じである。 Subsequently, as shown in FIG. 20a, a multilayer wiring layer 3 composed of a thin film wiring layer 2 having a wiring 120 and an interlayer insulating layer 110 is placed on an insulating substrate 1 filled with through holes 100. To form The wiring forming process itself is essentially the same as in the first embodiment. Subsequently, as shown in FIG. 2 Ob, a stress relaxation layer 5 is formed as necessary, and a hole (via hole) is formed in the stress relaxation layer 5 by photo-etching or laser processing. To form The process of forming the stress relaxation layer 5 is essentially the same as that of the first embodiment.
最後に、 図 2 0 cに示すように、 形成された多層配線層 3および応力緩和層 5 の孔およびその表面に配線を形成して、 多層配線基板 6を完成させる。  Finally, as shown in FIG. 20c, wiring is formed on the holes of the formed multilayer wiring layer 3 and the stress relaxation layer 5 and on the surface thereof to complete the multilayer wiring board 6.
多層配線基板 6完成後のバンプ形成からモジュール形成までの工程も前記第 1 の実施例と本質的に同様である。  The steps from the bump formation to the module formation after the completion of the multilayer wiring board 6 are essentially the same as those in the first embodiment.
本実施例によれば、 絶縁基板 1に絶縁性物質を充填するため、 貫通孔 1 0 0を 充填しない場合に比べ、 絶縁基板 1および多層配線基板 6の強度は大きくなる。 また、 貫通孔 1 0 0内壁と基板の表裏 （1次面おょぴ 2次面） の配線形成を一 括で処理できるため、 露光、 現像、 めっきの工程数を大きく削減できる。  According to the present embodiment, since the insulating substrate 1 is filled with the insulating substance, the strength of the insulating substrate 1 and the multilayer wiring board 6 is increased as compared with the case where the through holes 100 are not filled. In addition, since the wiring formation on the inner wall of the through hole 100 and the front and back surfaces of the substrate (the primary surface and the secondary surface) can be processed at one time, the number of steps of exposure, development, and plating can be greatly reduced.
続いて、 図 2 2およぴ図 2 3を用いて、 多層配線基板 6の他の製造方法につい て説明する。  Subsequently, another manufacturing method of the multilayer wiring board 6 will be described with reference to FIGS.
まず、 第 2の実施例と同様、 配線基板に用いられる絶縁基板 1として、 ガラス 基板またはシリコン基板を用意し、 必要に応じ、 表面や端面の整面処理や清浄ィ匕 処理、 表面絶縁化処理をおこなっておく。  First, similarly to the second embodiment, a glass substrate or a silicon substrate is prepared as the insulating substrate 1 used for the wiring substrate, and if necessary, the surface or the end surface is trimmed, the surface is cleaned, and the surface is insulated. I have done.
続いて、 図 2 2 aに示すように、 サンドブラストにより、 絶縁基板 1に貫通孔 1 0 0を形成する。 続いて、 絶縁基板 1に発生したマイクロクラックを除去する。 続いて、 図 2 2 bに示すように、 絶縁基板 1の貫通孔 1 0 0および絶縁基板 1 の上に配線を形成する。 上記実施例 1、 実施例 2と同様にセミアディティブ法や サブトラタティブ法などを用いて配線形成でき、 貫通孔 1 0 0内面おょぴ絶縁基 板 1の表裏 （1次面、 2次面） の 3面に給電膜を形成する点も実施例 2と同じで める。  Subsequently, as shown in FIG. 22A, through holes 100 are formed in the insulating substrate 1 by sandblasting. Subsequently, microcracks generated on the insulating substrate 1 are removed. Subsequently, as shown in FIG. 22B, wiring is formed on the through hole 100 of the insulating substrate 1 and the insulating substrate 1. Wiring can be formed using the semi-additive method, the subtractive method, or the like in the same manner as in the first and second embodiments. The front and back surfaces of the through hole 100 inner surface insulating substrate 1 (primary surface, secondary surface) The same as in Example 2 in that a power supply film is formed on the three surfaces.
実施例 2と本実施例との違いは、 絶縁基板 1の貫通孔 1 0 0への絶縁性物質充 填と絶縁基板 1上への層間絶縁層 1 1 0 (薄膜配線層 2 ) 形成の順番にある。 実 施例 2では基板表面配線形成の際には貫通孔 1 0 0の 1次側端は開口したままで あり、 その状態で貫通孔内部を充填していた。 一方、 本実施例では、 層間絶縁層 1 1 0 (薄膜配線層 2 ) の形成に先だって絶縁基板 1の 1次側の開孔端を配線に よって塞ぐ。 貫通孔の径が小さい場合にはめつき膜厚を厚くすれば、 貫通孔の狭 くなつている方の開孔端 （1次側開孔端） をめつき被膜で塞ぐことができる。 貫 通孔開孔端を塞いだ後、 多層配線層 3を形成する。 The difference between the second embodiment and this embodiment is that the order of filling the through hole 100 of the insulating substrate 1 with an insulating substance and forming the interlayer insulating layer 110 (thin film wiring layer 2) on the insulating substrate 1 is different. It is in. In Example 2, the primary side end of the through hole 100 was left open when the wiring on the substrate surface was formed, and the inside of the through hole was filled in that state. On the other hand, in the present embodiment, prior to forming the interlayer insulating layer 110 (thin film wiring layer 2), the opening end on the primary side of the insulating substrate 1 is closed by wiring. If the diameter of the through-hole is small, increasing the thickness of the plating allows the narrower end of the through-hole (primary opening) to be covered with the coating. Piercing After closing the through hole opening end, the multilayer wiring layer 3 is formed.
続いて、 図 2 2 cに示すように、 1次側開孔端が塞がれた貫通孔 1 0 0を充填 する。 実施例 1や実施例 2と同様、 絶縁性物質をペースト印刷することによる充 填でもよいし、 導電性材料の充填でも良レ、。  Subsequently, as shown in FIG. 22c, the through hole 100 whose primary side opening end is closed is filled. As in the case of the first and second embodiments, the filling may be performed by paste printing of an insulating substance, or the filling of a conductive material may be performed.
続いて、 図 2 3 aに示すように、 実施例 1や実施例 2と同様、 必要に応じて、 応力緩和層 5を形成し、 さらに応力,緩和層 5にフォトエッチングまたはレーザカロ ェ等により孔を形成する。  Subsequently, as shown in FIG. 23a, similarly to the first and second embodiments, a stress relaxation layer 5 is formed if necessary, and holes are formed in the stress and relaxation layer 5 by photoetching or laser calorie. To form
最後に、 図 2 3 b形成された多層配線層 3および応力緩和層 5の孔ぉよびその 表面に配線を形成して、 多層配線基板 6を完成させる。  Finally, wiring is formed on the holes and on the surfaces of the formed multilayer wiring layer 3 and stress relaxation layer 5 in FIG. 23B to complete the multilayer wiring board 6.
本実施例では、 絶縁基板 1上の二次側の配線により、 貫通孔 1 0 0の開口部を 塞ぐため、 多層配線層 3を形成した後に、 絶縁基板 1の貫通孔 1 0 0に絶縁性物 質を充填することができる。 この結果、 絶縁基板 1の 1次側端面付近で発生しゃ すい未充填部分 2 0 1の形成を効果的に抑制できる。 これにより、 次の工程で形 成される層間絶縁層の平坦性を確保でき、 高密度に配線を形成することがさらに 容易となる。  In this embodiment, since the wiring on the secondary side on the insulating substrate 1 closes the opening of the through hole 100, after forming the multi-layer wiring layer 3, the insulating hole 1 The substance can be filled. As a result, it is possible to effectively suppress the formation of the unfilled portion 201 near the primary end face of the insulating substrate 1. As a result, the flatness of the interlayer insulating layer formed in the next step can be ensured, and it becomes easier to form wiring with high density.
続いて、 配線基板および多層配線基板およびマルチチップモジュールの製造ェ 程のうち、 サンドプラストによって貫通孔を加工した絶縁基板上に配線をめつき 形成する工程について詳しく説明する。  Subsequently, in the manufacturing process of the wiring board, the multilayer wiring board, and the multi-chip module, a step of plating and forming the wiring on the insulating substrate in which the through hole is processed by the sand blast will be described in detail.
サンドブラストにより形成された微細な貫通孔の内壁面にスパッタゃ蒸着、 C V Dなどの方法で配線を形成すると、 貫通孔開孔端部付近あるいはその上部近傍 領域での配線断線や配線密着不良が発生しゃすレ、。 我々の研究によると、 サンド ブラストにより形成された微細な貫通孔を有する配線基板に接続信頼性が高い配 線を形成することが困難である理由が、 サンドブラストにより形成された貫通孔 の形状にその原因があることをつきとめた。 ここでは、 C u Z C rなどの給電膜 (めっき膜形成のための下地膜） をスパッタにより形成し、 その後めつきにより 銅 （C u ) 配線を形成する場合について説明する。  When wiring is formed on the inner wall of a fine through-hole formed by sand blasting by a method such as sputter deposition or CVD, wiring disconnection or poor wiring adhesion near the end of the through-hole opening or near the upper part of the hole occurs. Les ,. According to our research, it is difficult to form wiring with high connection reliability on a wiring board with fine through-holes formed by sand blast because of the shape of the through-holes formed by sand blast. Identified the cause. Here, a case will be described in which a power supply film (base film for forming a plating film) such as CuZCr is formed by sputtering, and then a copper (Cu) wiring is formed by plating.
図 6はサンドブラストを用いて基板に開孔した貫通孔の拡大写真を示している 力 図 2 4はその模式図を示す。 図 6および図 2 4より明らかなように、 絶縁基 板のサンドブラストで砂を吹き付ける側 （以下、 2次側） の裏側 （1次側） の開 孔先端部でくびれ形状になっていることがわかる。 すなわち、 2次側の開口径を d l、 1次側の開口径を d 3、 1次側の開口径の直前を d 2とすると、 d l >d 3 >d 2となっている。 図 6および図 24に示すように、 このくぴれ形状は加工 先端のわずか数マイクロメートル程度の大きさしかないが、 給電膜の膜厚が 1マ イクロメ一トル以下であることを考慮すると、 数マイクロメートルのくぴれ形状 は給電膜の形成に大きな影響を与える。 FIG. 6 shows an enlarged photograph of a through hole formed in a substrate by using sandblasting. FIG. 24 shows a schematic diagram of the force. As is evident from Figs. 6 and 24, the back side (primary side) of the side on which the sand is blown by the sandblasting of the insulating substrate (hereinafter, secondary side) is opened. It can be seen that the hole has a constricted shape at the tip. That is, assuming that the secondary side opening diameter is dl, the primary side opening diameter is d3, and immediately before the primary side opening diameter is d2, dl>d3> d2. As shown in Fig. 6 and Fig. 24, this constricted shape has a size of only a few micrometers at the processing tip, but considering that the thickness of the power supply film is less than 1 micrometer, The concave shape of several micrometers has a great effect on the formation of the feed film.
すなわち、 このようなくぴれ形状の最先端部は不連続形状となっているため、 貫通孔の内面にスパッタゃ C VD、 蒸着などの方法では給電膜の形成が不十分に なりやすい。 従って、 その箇所でめっきによる銅配線が形成されにくくなる。 特 に、 基板と配線との密着性を確保するためにスパッタにより成膜する C rや T i などは回り込みが起こりにくい傾向がある。 銅などの展性のある金属の場合には、 スパッタ成膜でも数マイクロメートル程度は回り込むが、 本来その下部に成膜さ れるべき C rなどの密着膜が精度良く成膜されていないために、 配線密着不良が 起こりやすくなっている。  In other words, since the leading edge of the irregular shape is discontinuous, the formation of the power supply film on the inner surface of the through-hole is likely to be insufficient by a method such as sputtering CVD or vapor deposition. Therefore, it becomes difficult to form a copper wiring by plating at that location. In particular, Cr, Ti, and the like, which are formed by sputtering in order to ensure the adhesion between the substrate and the wiring, tend to hardly wrap around. In the case of a malleable metal such as copper, even a sputtered film can go around a few micrometers, but the adhesion film such as Cr, which should be originally formed underneath, is not precisely formed. Insufficient wiring adhesion is likely to occur.
我々の実験によると、 貫通孔開孔端部付近あるいはその上部近傍領域での配線 断線や配線密着不良が発生し易いのは、 この配線密着不良に起因する現象である ことがわかった。  According to our experiments, it is the phenomenon caused by the poor wiring adhesion that is likely to cause the disconnection of the wiring or the poor wiring adhesion near the end of the through hole or near the upper part.
開孔先端部におけるくびれは、 貫通孔壁面に対して深さ方向に形成されている ことが示しているとおり、 サンドプラスト加工の際にできるメディアンクラック によるものである。  The constriction at the tip of the opening is due to a median crack formed during sand blasting, as indicated by the fact that it is formed in the depth direction with respect to the wall surface of the through hole.
本実施例では、 開孔先端部におけるくびれ形状を抑制するために、 いくつかの 方法を単独あるいは適宜組み合わせて使用する。  In the present embodiment, several methods are used alone or in an appropriate combination in order to suppress the constricted shape at the tip of the opening.
第一の方法として、 貫通孔を形成した後に、 くびれ形状が形成されている厚さ まで基板を研磨あるいは研削して、 くびれ形状を除去して平坦化する方法がある。 平坦化する方法としては、 化学的機械的研磨 （CMP ： Ch em i c a 1  As a first method, there is a method in which after forming a through-hole, the substrate is polished or ground to a thickness where the constricted shape is formed, and the constricted shape is removed to flatten the substrate. As a method of flattening, chemical mechanical polishing (CMP: Chemi c a 1
Me c h a n i c a l P o l i s h i n g) やラッピングなどが有効である。 くびれ形状が無くなった後に、 スパッタによりクロム膜を形成すれば、 一方向か らスパッタを行っても、 貫通孔の内面全体にクロム膜を形成することができ、 貫 通孔の内面全体に正確に銅めつきを行うことができる。 第二の方法として、 貫通孔が 1次側の付近まで形成されたときに、 (Mechanical Polishing) and wrapping are effective. If a chromium film is formed by sputtering after the constricted shape is eliminated, the chrome film can be formed on the entire inner surface of the through hole even if sputtering is performed from one direction, and the entire inner surface of the through hole can be accurately formed. Copper plating can be performed. As a second method, when the through hole is formed up to near the primary side,
ストの風圧を弱める、 もしくは粒子の径を小さくする方法がある。 このように、 風圧を弱める、 もしくは砂の粒径を微細にすることにより、 メディアンクラック 発生を抑制し、 従って、 くびれ形状が形成されないか、 あるいはくびれを小さく することができる。 There are methods to reduce the wind pressure of the strike or to reduce the particle diameter. As described above, by reducing the wind pressure or reducing the particle size of the sand, it is possible to suppress the occurrence of median cracks, so that no constricted shape is formed or the constriction can be reduced.
第三の方法として、 図 2 5に示すように、 基板の 1次側に他の部材をあてがう、 または 1次側の基板にフィルム等を貼り付け、 貫通孔が基板に達した後に、 その 部材またはフィルムを取り外す方法がある。 これにより、 貫通孔の 2次側表面近 傍での見かけの剛性が増大し、 従って、 メディアンクラックの発生が抑制される。 基板の 2次側にあてがうまたは貼付ける部材は、 絶縁基板 1と同等あるいはそれ 以上の曲げ弾性率を有する材料であることが望ましいが、 これに限定するわけで はない。 また、 1次側に隙間なく密着させることが望ましい。 例えば、 貫通孔形 成工程に先立って絶縁基板 1の 2次側の表面にスパッタなどを用いて補強膜を設 けても良い。 また、 あてがう部材は、 例えば基板の上に形成される配線であって あよい。  As a third method, as shown in Fig. 25, another member is applied to the primary side of the substrate, or a film or the like is attached to the primary side substrate, and after the through hole reaches the substrate, the member is used. Or there is a method of removing the film. As a result, the apparent rigidity near the secondary surface of the through hole is increased, and therefore, the occurrence of median cracks is suppressed. The member to be applied or adhered to the secondary side of the substrate is desirably a material having a bending elastic modulus equal to or higher than that of the insulating substrate 1, but is not limited thereto. It is also desirable that the primary side be in close contact with no gap. For example, prior to the through-hole forming step, a reinforcing film may be provided on the secondary surface of the insulating substrate 1 by using sputtering or the like. The member to be applied may be, for example, wiring formed on a substrate.
第四の方法として、 くびれ形状が生じた状態のままで、 基板の貫通孔にスパッ タを行う方法として、 基板の 1次側と 2次側の両面からスパッタを行う方法があ る。  As a fourth method, there is a method in which sputtering is performed on the through-holes of the substrate while the constricted shape remains, by sputtering from both the primary side and the secondary side of the substrate.
第五の方法としては、 図 2 6に示すように、 まず基板の 2次方向からクロムの スパッタを行い、 つぎに基板を裏返して 1次方向からクロムのスパッタを行い、 その状態でつぎに銅のスパッタを行い、 最後に基板をもう一度裏返して、 基板の 2次方向から銅のスパッタを行う方法がある。  As a fifth method, as shown in Fig. 26, first, chromium is sputtered from the secondary direction of the substrate, then the substrate is turned over, chromium is sputtered from the primary direction, and then copper is There is a method in which the substrate is turned over once again and copper is sputtered from the secondary direction of the substrate.
第四、 第五の方法では、 基板のくびれ形状を除去することなしに、 給電膜 ( C u /C r ) を均一に貫通孔の内部に形成することができる。  In the fourth and fifth methods, the power supply film (Cu / Cr) can be uniformly formed inside the through hole without removing the constricted shape of the substrate.
これらの方法を用いてめっき配線の形成を行えば、 サンドブラストにより形成 された貫通孔に信頼性の高い金属配線を形成することができる。  If a plating wiring is formed by using these methods, a highly reliable metal wiring can be formed in a through hole formed by sandblasting.
なお、 上記 5つの方法は、 サンドブラストによって形成された貫通孔にめっき 配線を行う場合に有効であり、 貫通孔が形成される基板はガラスまたはシリコン 基板に限定されるものではなく、 公知慣用の基板材料、 例えばセラミック基板等 に形成された貫通孔にめっき配線を行う場合にも有効である。 The above five methods are effective when plating wiring is applied to a through-hole formed by sandblasting. The substrate on which the through-hole is formed is not limited to a glass or silicon substrate. Material, for example ceramic substrate This is also effective when plating wiring is formed in the through hole formed in the substrate.
続いて、 上記実施例で説明した多層配線基板に形成される絶縁層 5 (応力緩和 層 5 ) の物性値等について詳しく説明する。  Subsequently, physical properties of the insulating layer 5 (stress relaxation layer 5) formed on the multilayer wiring board described in the above embodiment will be described in detail.
応力緩和層 5の膜厚は、 半導体モジュールのサイズ、 応力緩和層 5の弾性率、 絶縁基板 1の厚さや対角長さなどにも依存していて一概には断定できないが、 絶 縁基板 1の厚さを 0 . 3〜0 . 5 mmとし、 絶縁基板 1とその表面に形成される 応力緩和層 5とからなるバイメタルモデルで応力シミュレーシヨン実験を行なつ たところ、 許容できる応力緩和層 5の膜厚範囲は、 1 0乃至 5 0 0マイクロメ一 トルが望ましく、 更に好ましくは 3 0乃至 2 5 0マイクロメートルであることが わかった。 これは、 絶縁基板 1の厚みに対して約 1 / 1 0から 1 / 2程度の厚み に相当する。  The thickness of the stress relaxation layer 5 depends on the size of the semiconductor module, the elastic modulus of the stress relaxation layer 5, the thickness and the diagonal length of the insulating substrate 1, and cannot be unambiguously determined. When a stress simulation experiment was performed using a bimetal model composed of the insulating substrate 1 and the stress relaxation layer 5 formed on the surface thereof with a thickness of 0.3 to 0.5 mm, an acceptable stress relaxation layer 5 was obtained. It has been found that the film thickness range is preferably from 10 to 500 micrometers, more preferably from 30 to 250 micrometers. This corresponds to a thickness of about 1/10 to 1/2 of the thickness of the insulating substrate 1.
膜厚が 3 0マイクロメ一トルより小さくなると、 所望の応力緩和を得ることが できず、 また膜厚が 2 5 0マイクロメートルを越えて厚くなると応力緩和層 5自 身が持っている内部応力のために絶縁基板 1の反りが発生して基板が破損したり、 配線が断線するおそれがあるからである。  If the film thickness is less than 30 micrometers, the desired stress relaxation cannot be obtained, and if the film thickness exceeds 250 micrometers, the internal stress of the stress relaxation layer 5 itself is reduced. As a result, the insulating substrate 1 may be warped and the substrate may be damaged, or the wiring may be disconnected.
応力緩和層 5は、 絶縁基板 1より大幅に小さい弾性係数、 例えば室温において 0 . l G P aから l O G P aの弾性係数を有する樹脂材料により形成されている。 この範囲の弾性係数を有する応力緩和層 5であれば信頼性のある多層配線基板 6 を提供することができる。 すなわち、 0 . 1 G P aを下回る弾性係数の応力緩和 層 5の場合、 絶縁基板 1そのものの重量を支えることが困難になって半導体モジ ユール 1 0 0 0として使用する際に特性が安定しないという問題が生じやすい。 一方、 1 0 G P aを越える弾性係数の応力緩和層 5を使用すると、 応力緩和層 5 5自身が持っている内部応力のために絶縁基板 1の反りが発生し、 絶縁基板 1が 割れるおそれがある。  The stress relaxation layer 5 is formed of a resin material having an elastic coefficient significantly smaller than that of the insulating substrate 1, for example, from 0.1 GPa to 10 GPa at room temperature. If the stress relaxation layer 5 has an elastic coefficient in this range, a reliable multilayer wiring board 6 can be provided. That is, in the case of the stress relaxation layer 5 having an elastic coefficient of less than 0.1 GPa, it is difficult to support the weight of the insulating substrate 1 itself, and the characteristics are not stable when used as the semiconductor module 100. Problems are easy to occur. On the other hand, if the stress relaxation layer 5 having an elastic modulus exceeding 10 GPa is used, the insulation substrate 1 may be warped due to the internal stress of the stress relaxation layer 5 5 itself, and the insulation substrate 1 may be broken. is there.
ここで使用している応力緩和層 5の形成用の材料は、 ペースト状のポリイミド であるがこれに必ずしも限定されるわけではない。 前記ペースト状のポリイミド を使用する場合には、 印刷塗布された後に加熱することで硬化することが出来る。 また、 このペースト状のポリイミドは、 ポリイミドの前駆体と溶媒およびその中 に分散した多数のポリイミドの微小粒子からなっている。 微粒子としては、 具体 的には平均粒径 1乃至 2マイクロメ一トルであり、 最大粒径が約 1 0マイクロメ 一トルとなる粒度分布を有する微小粒子を使用した。 本実施例に用いられている ポリイミドの前駆体は、 硬化するとポリイミドの微小粒子と同一材料となるので、 ペースト状のポリイミドが硬ィヒした際には、 一種類の材料からなる均一な応力緩 和層 5が形成されることとなる。 本実施例では、 応力緩和層 5の形成材料として ポリイミドを用いたが、 本実施例ではポリイミド以外にアミドイミド樹脂、 エス テルイミド樹脂、 エーテルイミド樹脂、 シリコーン樹脂、 アクリル樹脂、 ポリエ ステル樹脂、 これらを変性した樹脂などを用いることも可能である。 ポリイミド 以外の樹脂を使用する場合には、 上記ポリイミド微小粒子表面に相溶性を付与す る処理を施すか、 あるいは、 上記ポリイミド微小粒子との親和性を向上するよう に樹脂組成に変成を施すことが望ましい。 The material for forming the stress relaxation layer 5 used here is a paste-like polyimide, but is not necessarily limited to this. When the paste-like polyimide is used, it can be cured by heating after printing and application. The paste-like polyimide is composed of a polyimide precursor, a solvent, and a large number of polyimide fine particles dispersed therein. As the fine particles, Specifically, fine particles having an average particle size of 1 to 2 micrometer and having a particle size distribution with a maximum particle size of about 10 micrometer were used. Since the polyimide precursor used in this example becomes the same material as the polyimide microparticles when cured, when the paste-like polyimide hardens, a uniform stress relaxation made of one type of material occurs. The sum layer 5 is formed. In this embodiment, polyimide was used as the material for forming the stress relaxation layer 5, but in this embodiment, in addition to polyimide, amide imide resin, ester imide resin, ether imide resin, silicone resin, acrylic resin, polyester resin, and these are modified. It is also possible to use a resin which has been used. When a resin other than polyimide is used, a treatment for imparting compatibility to the surface of the polyimide microparticles described above, or a modification of the resin composition so as to improve the affinity with the polyimide microparticles should be performed. Is desirable.
上記列挙した樹脂のうち、 イミド結合を有する樹脂、 例えばポリイミド、 アミ ドイミド、 エステルイミド、 エーテルイミド等では、 イミド結合による強固な骨 格のおかげで熱機械的特性、 例えば高温での強度などに優れ、 その結果として、 配線のためのめっき給電膜形成方法の撰択肢が広がる。 例えば、 スパッタなどの 高温処理を伴うめつき給電膜形成方法を選択できる。 シリコーン樹脂ゃァクリル 樹脂、 ポリエステル樹脂、 アミドイミド、 エステルイミ ド、 エーテルイミドなど イミド結合以外の結合で縮合した部分がある樹脂の場合、 熱機械特性は若干劣る ものの加工性や樹脂価格などの点で有利な場合がある。 例えば、 ポリエステルイ ミド樹脂では、 一般にポリイミドよりも硬化温度が低いため扱いやすい。  Among the resins listed above, resins having an imide bond, such as polyimide, amide imide, ester imide, and ether imide, have excellent thermomechanical properties, such as high-temperature strength, due to the strong skeleton of the imide bond. As a result, there are more options for forming a plating power supply film for wiring. For example, it is possible to select a plating power supply film forming method involving high-temperature processing such as sputtering. Silicone resin Polyacrylic resin, polyester resin, amide imide, ester imid, ether imide, etc.Resin with a portion condensed by a bond other than imide bond is slightly inferior in thermo-mechanical properties but advantageous in terms of processability and resin price There are cases. For example, polyesterimide resin is generally easier to handle because it has a lower curing temperature than polyimide.
応力緩和層 5形成用の材料は、 例えばエポキシ、 フエノール、 ポリイミド、 シ リコーン等の樹脂を単独あるいは 2種類以上配合し、 これに各種界面との接着性 を改善するための力ップリング剤や着色剤等を配合して用いることが可能である。 本実施例では、 これらの樹脂の中から価格、 熱機械特性などを総合的に勘案し てこれらの樹脂を適宜使い分ける。  The material for forming the stress relaxation layer 5 is, for example, a resin such as epoxy, phenol, polyimide, or silicone, alone or in combination of two or more resins. And the like can be blended and used. In the present embodiment, these resins are appropriately used in consideration of price, thermo-mechanical properties, and the like from among these resins.
ペースト状のポリイミド中にポリイミド微小粒子を分散させることで材料の粘 弾特性を調整することが可能となるため、 印刷性に優れたペーストを使用するこ とが出来る。 微小粒子の配合を調整することで、 ペーストのチキソトロピー特性 を制御することが可能となるため、 粘度の調整と組み合わせることで、 印刷特性 を改善することが出来る。 本願実施例で好適なペーストのチクソトロピー特性は、 回転粘度計を用いて測定した回転数 1 r p mでの粘度と回転数 1 0 r p mでの粘 度の比から求めた、 いわゆるチクソトロピーインデックスが 1 . 0から 1 0 . 0 の範囲にあることが望ましい。 なお、 チクソトロピーインデックスに温度依存性 が現れるペーストの場合、 チクソトロピーインデックスが 1 . 0から 1 0 . 0の 範囲になるような温度領域で印刷すると高成績が得られる。 By dispersing the polyimide fine particles in the paste-like polyimide, the viscoelastic properties of the material can be adjusted, so that a paste having excellent printability can be used. The thixotropic properties of the paste can be controlled by adjusting the composition of the fine particles. Can be improved. The thixotropy characteristic of the paste suitable in the examples of the present application is a so-called thixotropy index obtained from the ratio of the viscosity at a rotation speed of 1 rpm and the viscosity at a rotation speed of 10 rpm measured using a rotational viscometer. Is preferably in the range of 10.0 to 10.0. In the case of a paste in which the thixotropy index has a temperature dependency, high performance can be obtained by printing in a temperature region where the thixotropy index is in the range of 1.0 to 10.0.
必要となる応力緩和層 5の膜厚が 1回の印刷およぴ加熱硬化で形成されないと きには、 印刷及び材料の硬化を複数回繰り返すことで所定の膜厚を得ることがで きる。 例えば、 固形分濃度 3 0乃至 4 0 %のペーストを用いて厚さ 6 5マイクロ メートルのメタルマスクを使用した場合、 2回の印刷で硬化後の膜厚として約 5 0マイクロメートルを得ることが出来る。  When the required film thickness of the stress relaxation layer 5 is not formed by one printing and heat curing, a predetermined film thickness can be obtained by repeating printing and curing of the material a plurality of times. For example, if a metal mask with a thickness of 65 μm is used using a paste with a solid concentration of 30 to 40%, it is possible to obtain a film thickness of about 50 μm after curing by two printings. I can do it.
さらに、 応力緩和層 5用材料の硬化温度は 1 0 0 °Cから 2 5 0 °Cまでのものを 用いる事が望ましい。 硬化温度がこれより低い場合、 半導体モジュール製造のェ 程内での管理が難しく、 硬化温度がこれより高くなると硬化冷却時の熱収縮で絶 縁基板 1の応力が増大する懸念があるからである。  Further, it is desirable to use a material having a curing temperature of 100 ° C. to 250 ° C. for the material for the stress relaxation layer 5. If the curing temperature is lower than this, it is difficult to control within the semiconductor module manufacturing process, and if the curing temperature is higher than this, there is a concern that the stress of the isolated substrate 1 will increase due to heat shrinkage during curing and cooling. .
硬化後の応力緩和層 5はスパッタ、 めっき、 エッチングなどのさまざまな工程 にさらされることから、 耐熱性、 耐薬品性、 耐溶剤性などの特性も要求される。 具体的には、 耐熱性としてそのガラス転位温度 （T g ) が 1 5 0 °C超 4 0 0 °C以 下であることが望ましく、 より望ましくは T gが 1 8 0 °C以上、 最も好ましくは T gが 2 0 0 °C以上である。 図 2 7はガラス転移温度 (T g ) と線膨張係数の関 係を示す実験結果である。 これより、 ガラス転移温度 （T g ) が 2 0 0 °C以上で あれば、 クラックが発生していないことが分かる。 なお、 工程中での様々な温度 処理における変形量を抑える観点から、 T g以下の領域での線膨脹係数 （ 1 ) は小さいほど好ましい。 具体的には 3 p p m/°Cに近いほどよい。 一般に低弾性 材料は線膨脹係数が大きい場合が多いが、 本実施例で好適な応力緩和層 5材料の 線膨脹係数の範囲は 3 p p m/°C〜 3 0 0 p p mZ°Cの範囲であることが望まし い。 より好ましくは 3 p p mZ°C〜 2 0 0 p p mZ°Cの範囲であり、 最も望まし い線膨脹係数は 3 p p mZ°C〜 1 5 0 p p m/°Cの範囲である。 線膨脹係数が大 きい場合には、 前述した弾性係数が小さいことが望ましい。 より具体的には、 弾 性係数 （G P a ) と線膨脹係数 （p p m/°C) の積の値が特定の範囲にはいるよ うにすると良い。 この値の望ましい範囲は、 基板のサイズや厚み、 実装形態によ つて変動するが、 一般的には、 この値がおおむね、 5 0〜1 0 0 0の範囲に入つ ていることが望ましい。 Since the stress relaxation layer 5 after curing is exposed to various processes such as sputtering, plating, and etching, characteristics such as heat resistance, chemical resistance, and solvent resistance are also required. Specifically, the glass transition temperature (T g) of the heat resistance is preferably more than 150 ° C. and not more than 400 ° C. or less, more preferably T g is more than 180 ° C. Preferably, T g is 200 ° C. or higher. Figure 27 shows the experimental results showing the relationship between the glass transition temperature (T g) and the coefficient of linear expansion. From this, it can be seen that cracks did not occur when the glass transition temperature (T g) was 200 ° C. or higher. From the viewpoint of suppressing the amount of deformation in various temperature treatments in the process, the smaller the linear expansion coefficient (1) in the region of Tg or less, the better. Specifically, the closer to 3 ppm / ° C, the better. In general, low-elasticity materials often have a large linear expansion coefficient, but the preferred linear expansion coefficient of the stress relaxation layer 5 material in this embodiment is in the range of 3 ppm / ° C to 300 ppmZ ° C. It is desirable. More preferably, it is in the range of 3 ppmZ ° C to 200 ppmZ ° C, and the most desirable linear expansion coefficient is in the range of 3 ppmZ ° C to 150 ppm / ° C. When the coefficient of linear expansion is large, it is desirable that the above-mentioned elastic coefficient is small. More specifically, the bullet It is recommended that the value of the product of the coefficient of thermal expansion (GPa) and the coefficient of linear expansion (ppm / ° C) be within a specific range. The desirable range of this value varies depending on the size, thickness, and mounting form of the substrate, but generally, it is desirable that this value is generally in the range of 50 to 100,000.
一方、 熱分解温度 (T d ) は約 3 0 0 °C以上であることが望ましく、 さらに望 ましくは 3 5 0 °C以上であればよい。 T gや T dがこれらの値を下回っていると、 プロセス中での熱工程、 例えばスパッタゃスパッタエツチ工程で樹脂の変形、 変 質や分解が起こる危険性がある。 耐薬品性の観点から言うと、 3 0 %硫酸水溶液 や 1 0 %水酸化ナトリウム水溶液への 2 4時間以上の浸漬で変色、 変形などの樹 脂変質が起こらない事が望ましい。 耐溶剤性としては、 溶解度パラメーター （S P値） が 5〜3 0 ( c a l / c m 3 ) 1 Z 2となることが望ましい。 応力緩和層 5用がベースレジンに幾つかの成分を変成してなる材料である場合には、 その組 成の大部分が上記溶解度パラメータの範囲にはいっていることが望ましい。 より 具体的にいうと、 溶解度パラメータ （S P値） が 5未満あるいは 3 0超である成 分が 5 0重量％を越えて含有されていないことが望ましい。  On the other hand, the thermal decomposition temperature (T d) is desirably about 300 ° C. or higher, and more desirably, 350 ° C. or higher. If the Tg or Td is below these values, there is a risk that the resin will be deformed, deteriorated or decomposed during a thermal process in the process, for example, a sputter / sputter etch process. From the viewpoint of chemical resistance, it is desirable that resin aging such as discoloration and deformation does not occur when immersed in a 30% aqueous sulfuric acid solution or a 10% aqueous sodium hydroxide solution for 24 hours or more. As for the solvent resistance, the solubility parameter (SP value) is desirably 5 to 30 (cal / cm3) 1Z2. When the material for the stress relaxation layer 5 is a material obtained by modifying some components to the base resin, it is desirable that most of the composition fall within the range of the solubility parameter. More specifically, it is desirable that a component having a solubility parameter (SP value) of less than 5 or more than 30 does not exceed 50% by weight.
これらの耐薬品性ゃ耐溶剤性が不十分だと適用可能な製造プ口セスが限定され る場合があり、 製造原価低減の観点から好ましくないこともある。 現実的には、 これらの特性を満足する材料コストとプロセス自由度とを総合的に勘案した上で、 応力緩和層 5用の材料を決定すると良い。  If the chemical resistance and the solvent resistance are insufficient, applicable manufacturing processes may be limited, which may be undesirable from the viewpoint of reducing manufacturing costs. In reality, it is preferable to determine the material for the stress relaxation layer 5 after considering the material cost and the process flexibility satisfying these characteristics comprehensively.
上記実施例においては、 主にガラスおよぴシリコンからなる配線基板およびそ れを用いた多層配線基板、 さらにそれを用いたマルチチップモジュールについて 詳しく説明した。 本実施例では、 本発明に係る配線基板およぴ配線基板の製造方 法を変位センサ等、 加速度や角速度を検出して運動している物体の位置や姿勢の 制御を行う装置およびその製造方法に用いた場合について説明する。  In the above embodiment, the wiring board mainly made of glass and silicon, the multilayer wiring board using the same, and the multichip module using the same have been described in detail. In the present embodiment, a wiring board and a method of manufacturing the wiring board according to the present invention are controlled by using a displacement sensor or the like to control the position and orientation of a moving object by detecting acceleration or angular velocity and a method of manufacturing the same. The case where the method is used will be described.
図 3 0を用いて、 本実施例にかかるマイク口センサパッケージの製造方法を説 明する。 まず、 デバイスウェハ 4 0 0の表面をエッチングする （図 3 0 a ) 。 続 いて、 デバイスウェハ 4 0 0を保護する第一の基板、 たとえばガラス基板等にェ ツチングされたデバイスウェハ 4 0 0を接合する (図 3 O b ) 。 続いて、 デバイ スウェハ 4 0 0を再ぴエッチングして、 微細な振動素子等のデバイスを形成する (図 3 0 c ) 。 A method for manufacturing the microphone port sensor package according to the present embodiment will be described with reference to FIG. First, the surface of the device wafer 400 is etched (FIG. 30a). Subsequently, the device wafer 400, which has been etched onto a first substrate for protecting the device wafer 400, for example, a glass substrate, is joined (Ob in FIG. 3). Subsequently, the device wafer 400 is re-etched to form devices such as fine vibration elements. (Figure 30c).
続いて、 デバイスウェハ 4 0 0を支持するガラス基板等の第二の基板 4 2 0を エッチングして、 窪み部分を形成する （図 3 0 d ) 。 続いて、 振動素子等が形成 されているデバイスウェハと第二の基板 4 2 0を接合する （図 3 0 e ) 。  Subsequently, a second substrate 420 such as a glass substrate supporting the device wafer 400 is etched to form a concave portion (FIG. 30d). Subsequently, the device wafer on which the vibrating element and the like are formed and the second substrate 420 are joined (FIG. 30e).
続いて、 第一の基板 4 1 0とデバイスウェハ 4 1 0を電気的に接続するため、 サンドプラストにより第一の基板 4 1 0に貫通孔 4 3 0を形成する （図 3 0 f ) 。 なお、 第一の基板に貫通孔を形成するときに、 後の個別化工程でダイシングする 第一の基板の位置に窪み （穴） を形成していてもよい。  Subsequently, in order to electrically connect the first substrate 410 to the device wafer 410, a through-hole 430 is formed in the first substrate 410 by sand blast (FIG. 30f). When a through hole is formed in the first substrate, a depression (hole) may be formed at a position of the first substrate to be diced in a later individualization step.
続いて、 第一の基板 4 1 0とデバイスウェハ 4 0 0の電気的に接続するために、 第一の基板 4 1 0の表面おょぴ第一の基板 4 1 0の貫通孔 (コンタクトホール） 4 3 0の内側に、 図 3 0 gに示すような導体の金属を蒸着してパターニングして 配線を形成する。  Subsequently, in order to electrically connect the first substrate 410 and the device wafer 400, the surface of the first substrate 410 and the through holes (contact holes) of the first substrate 410 are formed. A conductor metal as shown in Fig. 30g is deposited and patterned inside the 400 to form wiring.
最後に、 第二のガラス基板 4 2 0の上に形成されているマイクロセンサ （マイ クロジャイロ） をダイシングして、 個別化する （図 3 O h ) 。 これにより、 マイ ク口センサのパッケージが完成する。  Finally, the microsensor (micro gyro) formed on the second glass substrate 420 is diced and individualized (Fig. 3 Oh). This completes the package for the microphone port sensor.
なお、 貫通孔内壁面の配線の形成をデバイスウェハに接合される前に行い、 配 線パタ一ンが形成されたパッケージ用基板をデバイスゥェハに接合してもよレ、。 この場合、 貫通孔内壁面の配線の形成には、 上記実施例で説明したように、 基板 両面からスパッタを行ってもよい。 また、 サンドブラス ト等により貫通孔を形成 する場合には、 上記説明したように貫通孔の開口端でくびれ部分が形成されるこ とがあるので、 貫通孔形成後にパッケージ用基板を研磨してもよレ、。  Note that the wiring on the inner wall surface of the through hole may be formed before bonding to the device wafer, and the package substrate on which the wiring pattern is formed may be bonded to the device wafer. In this case, the wiring on the inner wall surface of the through-hole may be formed by sputtering from both sides of the substrate as described in the above embodiment. Further, when the through-hole is formed by sandblasting or the like, a constricted portion may be formed at the opening end of the through-hole as described above. Therefore, the package substrate is polished after the through-hole is formed. Well ,.
また、 第一の基板 4 1 0とデバイスウェハ 4 0 0および第二の基板 4 2 0とデ パイスウェハ 4 3 0との間に、 第一及ぴ第二の基板とデバイスウェハの間に生じ る熱応力を緩和するための層を設けてもよい。  In addition, it occurs between the first substrate 410 and the device wafer 400 and between the second substrate 420 and the device wafer 430 and between the first and second substrates and the device wafer. A layer for reducing thermal stress may be provided.
本実施例では、 デバイスウェハの上下に位置する基板にガラスまたはシリコン 基板を用いるため、 狭ピッチな配線を形成することができる。 したがって、 マイ クロジャイロをより小型にすることができる。 また、 貫通孔をサンドブラストに より形成しているため、 貫通孔内の微小な凸凹により配線を形成する金属材料と パッケージ用基板との密着性が増し、 短絡等を防止することができる。 また、 本 実施例では、 貫通孔のくびれ部分が形成されない、 または形成されたくぴれ部分 を研磨して除去することにより、 配線の短絡等の防止ができる。 また、 第一及び 第二の基板とデバイスウェハの間に生じる熱応力を緩和するための層を形成する ことにより、 熱膨張係数の差によって熱応力が生じたとしても、 第一及び第二の 基板とデバイスウェハの間の振動素子が位置するキヤビティ内の真空状態を保つ ことができる。 In the present embodiment, since a glass or silicon substrate is used as the substrate located above and below the device wafer, it is possible to form wiring with a narrow pitch. Therefore, the micro gyro can be made smaller. In addition, since the through-hole is formed by sandblasting, the adhesion between the metal material forming the wiring and the package substrate is increased due to minute unevenness in the through-hole, and a short circuit or the like can be prevented. Also the book In the embodiment, short-circuiting of the wiring and the like can be prevented by removing the constricted portion of the through-hole which is not formed or the formed constricted portion by polishing. Also, by forming a layer for relaxing thermal stress generated between the first and second substrates and the device wafer, even if thermal stress is generated due to a difference in thermal expansion coefficient, the first and second It is possible to maintain a vacuum state in the cavity where the vibrating element is located between the substrate and the device wafer.
なお、 変位センサ、 慣性センサ、 特に加速度センサや回転角速度センサ （ジャ イロスコープ、 ョーレートセンサ） は、 自動車の車両安定制御システム、 ェアバ ックシステム、 ナピゲ一シヨンシステム、 カメラや小型ビデオ力メラの手ぶれ防 止などに必要なセンサとして用いられる。  In addition, displacement sensors and inertial sensors, especially acceleration sensors and rotational angular velocity sensors (gyroscopes, gyro sensors) are used in vehicle stability control systems, automotive systems, napige systems, camera shake prevention for cameras and small video cameras, etc. Used as a sensor required for
以上、 本発明に関し、 実施の形態に基づき具体的に説明したが、 本発明は前記 実施の形態に限定されるものではなく、 その趣旨を逸脱しなレ、範囲で種々変更可 能である。  As described above, the present invention has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various changes can be made without departing from the gist of the present invention.
産業上の利用可能性 Industrial applicability
本発明によれば、 信頼性が高く、 高密度配線可能な配線基板を製造することが できる。  According to the present invention, a wiring board having high reliability and capable of high-density wiring can be manufactured.

Claims

請求の範囲 The scope of the claims
1 . ガラス基板と、 該ガラス基板の上に形成された配線およぴ絶縁層を含む多 層配線層とを有する配線基板であって、 1. A wiring board having a glass substrate and a multilayer wiring layer including a wiring and an insulating layer formed on the glass substrate,
該ガラス基板は該ガラス基板の両面で電気的接続を取るための孔を有し、 該孔 はサンドプラストにより形成されたものである配線基板。  The wiring substrate, wherein the glass substrate has holes for making electrical connection on both sides of the glass substrate, and the holes are formed by sand blast.
2 . ガラス基板と、 該ガラス基板の上に形成された配線およぴ絶縁層を含む多 層配線層とを有する配線基板であつて、  2. A wiring board having a glass substrate and a multilayer wiring layer including wiring and an insulating layer formed on the glass substrate,
該ガラス基板は該ガラス基板の両面で電気的接続を取るための複数の孔を有し、 該孔は複数の開口を有するマスクを備えた該ガラス基板に粒子を吹き付け、 該ガ ラス基板の一部を破碎して形成したものである配線基板。  The glass substrate has a plurality of holes for electrical connection on both sides of the glass substrate, the holes spray particles onto the glass substrate provided with a mask having a plurality of openings, A wiring board formed by crushing a part.
3 . 請求項 1に記載の配線基板であって、 前記孔の内壁面には配線が形成され、 かつ該孔には絶縁性の材料が充填されている配線基板。  3. The wiring board according to claim 1, wherein a wiring is formed on an inner wall surface of the hole, and the hole is filled with an insulating material.
4 . 請求項 2に記載の配線基板であって、 前記孔の内壁面には配線が形成され、 かつ該孔には絶縁性の材料が充填されている配線基板。  4. The wiring board according to claim 2, wherein a wiring is formed on an inner wall surface of the hole, and the hole is filled with an insulating material.
5 . 請求項 1に記載の配線基板であって、 前記孔の内部には導電性の材料が充 填されている配線基板。  5. The wiring board according to claim 1, wherein the inside of the hole is filled with a conductive material.
6 . 請求項 2に記載の配線基板であって、 前記孔の内部には導電性の材料が充 填されている配線基板。  6. The wiring board according to claim 2, wherein the inside of the hole is filled with a conductive material.
7 . 請求項 1に記載の配線基板であって、 該配線基板は外部接続端子を有し、 かつ該外部接続端子は鉛フリ一である配線基板。  7. The wiring board according to claim 1, wherein the wiring board has external connection terminals, and the external connection terminals are lead-free.
8 . 請求項 2に記載の配線基板であって、 該配線基板は外部接続端子を有し、 かつ該外部接続端子は鉛フリ一である配線基板。  8. The wiring board according to claim 2, wherein the wiring board has external connection terminals, and the external connection terminals are lead-free.
9 . 貫通孔を備えた第一の基板と、  9. a first substrate having a through hole;
該第一の基板の一方の面に形成された第一の配線およぴ第一の絶縁層を有する 第一の配線層と、  A first wiring layer having a first wiring and a first insulating layer formed on one surface of the first substrate;
該第一の基板の他方の面に形成された第二の配線および第二の絶縁層を有する 第二の配線層とを有する配線基板であって、  A second wiring layer having a second wiring and a second insulating layer formed on the other surface of the first substrate, and a second wiring layer,
該第一の絶縁層と該第二の絶縁層の熱膨張係数が異なる配線基板。 A wiring board in which the first insulating layer and the second insulating layer have different thermal expansion coefficients.
1 0 . 請求項 9に記載の配線基板であつて、 10. The wiring board according to claim 9, wherein
前記第一の絶縁層の熱膨張係数は該配線基板に実装される半導体素子の熱膨張 係数に近く、  The coefficient of thermal expansion of the first insulating layer is close to the coefficient of thermal expansion of the semiconductor element mounted on the wiring board,
前記第二の絶縁層の熱膨張係数は該配線基板が実装される実装基板の熱膨張係 数に近い配線基板。  A wiring board wherein the thermal expansion coefficient of the second insulating layer is close to the thermal expansion coefficient of the mounting board on which the wiring board is mounted.
1 1 . 貫通孔を備え、 かつ熱膨張係数が約 3 p p m ^Cから約 5 p p m/°Cで ある第一の基板と、  1 1. a first substrate having a through-hole and having a coefficient of thermal expansion of about 3 ppm ^ C to about 5 ppm / ° C;
該孔の開口端の径が小さレ、方の該第一の基板の面に形成された第一の配線およ び第一の絶縁層を有する第一の配線層と、  A first wiring layer having a first wiring and a first insulating layer formed on the surface of the first substrate, the diameter of the opening end of the hole being smaller;
該孔の開口端の径が大きい方の該第一の基板の面に形成された第二の配線およ ぴ第二の絶縁層を有する第二の配線層と、  A second wiring layer having a second wiring and a second insulating layer formed on the surface of the first substrate having a larger diameter at the opening end of the hole;
該第二の配線層の表面であって、 かつ該第一の基板の反対側に形成された第三 の絶縁層を有する配線基板であって、  A wiring board having a third insulating layer formed on the surface of the second wiring layer and opposite to the first substrate,
該第三の絶縁層は該配線基板と該配線基板が実装される実装基板の間に生じる 熱応力を緩和する配線基板。  The wiring board, wherein the third insulating layer relieves thermal stress generated between the wiring board and a mounting board on which the wiring board is mounted.
1 2 . ガラス基板の上に導体層および絶縁層を有する配線層を多層に形成する 工程と、  12. forming a multilayer wiring layer having a conductor layer and an insulating layer on a glass substrate;
該ガラス基板の一方の面に形成された配線層に第一の孔を形成する工程と、 該第一の孔が形成された位置から該ガラス基板にサンドブラストを行って、 該 ガラス基板に第二の孔を形成する工程と、  Forming a first hole in a wiring layer formed on one surface of the glass substrate; and performing sand blasting on the glass substrate from a position where the first hole is formed. Forming a hole of
該第二の孔の内壁面および該配線層の最表面に配線を形成する工程を有する配 線基板の製造方法。  A method for manufacturing a wiring board, comprising a step of forming wiring on the inner wall surface of the second hole and the outermost surface of the wiring layer.
1 3 . 請求項 1 2に記載の配線基板の製造方法において、  13. The method of manufacturing a wiring board according to claim 12,
前記サンドプラストを前記ガラス基板の上に形成された配線パッドがある位置 に対して行うことを有する配線基板の製造方法。  A method of manufacturing a wiring substrate, comprising: performing the sand blasting on a position where a wiring pad formed on the glass substrate is present.
1 4 . 請求項 1 2に記載の配線基板の製造方法において、  14. The method of manufacturing a wiring board according to claim 12,
前記サンドブラストは、 該サンドプラストが開始される前記ガラス基板の面の 裏面に形成された前記導体層に向って行われることを有する配線基板の製造方法。  The method for manufacturing a wiring board, wherein the sandblasting is performed toward the conductor layer formed on the back surface of the surface of the glass substrate where the sandblasting is started.
1 5 . 請求項 1 2に記載の配線基板の製造方法において、 前記第二の孔を形成する方法と前記第一の孔を形成する方法は異なる配線基板 の製造方法。 15. The method of manufacturing a wiring board according to claim 12, A method of manufacturing a wiring board, wherein a method of forming the second hole and a method of forming the first hole are different.
1 6 . 請求項 1 2に記載の配線基板の製造方法において、  16. The method of manufacturing a wiring board according to claim 12,
前記絶縁層の少なくとも 1層はマスクを用いて印刷形成されたものである配線 基板の製造方法。  A method for manufacturing a wiring board, wherein at least one of the insulating layers is formed by printing using a mask.
1 7 . サンドブラストによりガラス基板に孔を形成する工程と、  17. A step of forming holes in the glass substrate by sandblasting;
該ガラス基板の少なくとも一方の面、 および該孔の内壁面に配線を形成するェ 程と、  Forming wiring on at least one surface of the glass substrate and the inner wall surface of the hole;
該ガラス基板およぴ該ガラス基板の上に形成された配線の上に、 絶縁層およぴ 導体層を含む多層配線層を形成する工程を有する配線基板の製造方法。  A method for manufacturing a wiring board, comprising: forming a multilayer wiring layer including an insulating layer and a conductor layer on the glass substrate and the wiring formed on the glass substrate.
1 8 . 請求項 1 7に記載の配線基板の製造方法において、  18. The method for manufacturing a wiring board according to claim 17,
前記孔を充填する工程を有する配線基板の製造方法。  A method for manufacturing a wiring board, comprising a step of filling the holes.
1 9 . 請求項 1 7に記載の配線基板の製造方法において、  19. The method of manufacturing a wiring board according to claim 17,
前記孔の内壁面に配線を形成する場合に、 該孔を形成した後、 前記ガラス基板 の他方の面を所望の厚さまで研磨し、 該孔の内壁面に配線を形成する配線基板の 製造方法。  When forming wiring on the inner wall surface of the hole, after forming the hole, the other surface of the glass substrate is polished to a desired thickness, and the wiring is formed on the inner wall surface of the hole. .
2 0 . 請求項 1 7に記載の配線基板の製造方法において、  20. The method of manufacturing a wiring board according to claim 17,
前記孔の内壁面に配線を形成する場合に、 前記ガラス基板の一方の側からスパ ッタを行レ、第一の導電性の膜を形成する工程と、  When forming wiring on the inner wall surface of the hole, performing a sputter from one side of the glass substrate to form a first conductive film;
該ガラス基板を裏返して、 スパッタを行い第二の導電性の膜を形成する工程と、 該第二の導電性の膜上に第三の導電性の膜を形成する工程と、  Turning over the glass substrate, forming a second conductive film by sputtering, and forming a third conductive film on the second conductive film;
該ガラス基板を裏返して第一の導電性の膜上に第四の導電性の膜を形成するェ 程を有する配線基板の製造方法。  A method of manufacturing a wiring board, comprising: turning over the glass substrate to form a fourth conductive film on the first conductive film.
2 1 . 請求項 1 2に記載の配線基板の製造方法において、  21. The method of manufacturing a wiring board according to claim 12,
前記ガラス基板に配線を形成した後に、 該ガラスを個別化する工程を有する配 線基板の製造方法。  A method for manufacturing a wiring substrate, comprising: after forming wiring on the glass substrate, individualizing the glass.
2 2 . 請求項 1 7に記載の配線基板の製造方法において、  22. The method of manufacturing a wiring board according to claim 17,
前記ガラス基板に配線を形成した後に、 該ガラスを個別化する工程を有するこ とを特徴とする配線基板の製造方法。  A method for manufacturing a wiring board, comprising a step of forming the wiring on the glass substrate and then individualizing the glass.
PCT/JP2002/005162 2001-05-31 2002-05-28 Wiring board and its production method WO2002100142A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001163641A JP4012375B2 (en) 2001-05-31 2001-05-31 Wiring board and manufacturing method thereof
JP2001-163641 2001-05-31

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