JP2015233084A - Chip module and information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip module and an information processing device that improve degradation in signal quality and power supply characteristics due to resonance that occurs in a glass interposer.SOLUTION: A chip module 100A has a glass interposer 5 between a semiconductor chip 1, 2 and a package substrate 3, and the glass interposer 5 has a through-via 7 with a larger electric resistance than approximately 1 Ω. When a voltage between an upper side and a lower side of a glass core 30 is high due to resonance noise, current will flow via the through-via 7 to convert electromagnetic energy to heat energy. Thus, the resonance noise will attenuate and degradation in signal quality and power supply capability can be avoided.

Description

The present invention relates to a chip module and information processing equipment.

  Patent Document 1 (U.S. Pat. No. 2013/0119555) states that “a small electronic package, wherein a plurality of through vias have a wall in a glass interposer having a top, and a stress relaxation barrier is formed on the top of the glass interposer. The plurality of metallization seed layers being at least part of the stress relaxation barrier, the conductor being at least part of the metallization seed layer and forming a plurality of metallized through package substrate vias; A through through vias, and at least some of the through vias are filled with the stress relaxation layer or metallization seed layer (A microelectronic package comprising: a plurality of through vias having walls in a glass interposer having a top portion; a stress relief barrier on at least a portion of the top p ortion of the glass interposer; a metallization seed layer on at least a portion of the stress relief layer; and a conductor on at least a portion of the metallization seed layer and through at least a portion of the plurality of the through vias forming a plural. of metalized through package vias, 10.at least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.).

US Patent 2013/0119555

  In the glass interposer, conductor layers are arranged on both surfaces of the glass core, and the upper and lower sides of the glass core are electrically connected by TGV (Trough Glass Via) penetrating the glass core. Because the loss of the glass core is small, the glass core part sandwiched between both sides works as a cavity resonator, and the electromagnetic field caused by the signal passing through the TGV and the current of the power supply / GND leaks into the core. Is excited, and there is a problem that signal quality and power supply characteristics deteriorate. The present invention has been made in view of such circumstances, and an object thereof is to provide a technique for improving signal quality deterioration and power supply characteristic deterioration due to resonance generated in a glass interposer.

  The present application includes a plurality of means for solving the above-described problems. For example, a chip module has a glass interposer between a semiconductor chip and a package substrate, and the glass interposer It has a through via having a resistance value greater than about 1Ω.

  According to the technology of the present invention, it is possible to improve signal quality deterioration and power supply characteristic deterioration due to resonance generated in a glass interposer. Problems, configurations, effects, and the like other than those described above will be clarified by the following description of embodiments.

1 is an example of a longitudinal sectional view of a chip module of Example 1. FIG. It is an example of the cross-sectional view of a chip module. The model for eigenmode analysis is shown. It is a comparison result of Q value in the model. The relationship between the electrical resistance value of TGV and the Q value of the primary mode is shown. The relationship between the electrical resistance value of TGV and the frequency of the primary mode is shown. It is a figure explaining an example of TGV formation. It is an example of the longitudinal cross-sectional view of the chip module of Example 2. It is an example of the cross-sectional view of a chip module. It is a figure explaining an example of TGV formation. It is an example of the longitudinal cross-sectional view of the chip module of Example 3. It is an example of the circuit diagram which shows a connection relationship. It is an example of the longitudinal cross-sectional view of the glass interposer of Example 4. It is an example of the longitudinal cross-sectional view of the chip module of Example 5. It is an example of the cross-sectional view of a chip module. It is the figure which looked at the board | substrate part of the information processing apparatus incorporating the chip module from the side surface.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Below, the same code | symbol is provided with respect to the same function and a structure, and description is abbreviate | omitted.
[Example 1]

  FIG. 1 is an example of a longitudinal sectional view of the chip module 100A of the first embodiment, and FIG. 2 is an example of a transverse sectional view of the chip module 100A. More specifically, FIG. 2 is an example of a cross-sectional view taken along line AA in FIG. 1, and FIG. 1 is an example of a cross-sectional view taken along line BB in FIG.

  The chip module here includes a package substrate and a glass interposer, and one or more semiconductor chips are mounted on the glass interposer. The semiconductor chip is, for example, an LSI (Large Scale Integration) or an IC (Integrated Circuit), but is not limited thereto. The package substrate is not particularly limited as long as it can be electrically connected to the glass interposer via the electrode portion. Here, the package substrate is made of ceramic, but is not limited to this, and any other material such as an organic resin may be adopted. The glass interposer includes a glass core formed of a glass-based material, has conductive planes on the upper and lower surfaces of the glass core, and includes at least one through via that connects the conductive planes. I just need it. Examples of the glass material include, but are not limited to, glass ceramics, borosilicate glass, quartz glass, and high silicate glass.

The chip module 100A is an example of a module in which an ASIC (Application Specific Integrated Circuit) and an optical IC are mounted on the same package substrate, but is not limited thereto. The chip module 100A may be mounted with any semiconductor chip such as an IC other than an ASIC or an optical IC, or an LSI. The ASIC may be, for example, an FPGA (Field-Programmable Gate Array), a CPU (Central Processing Unit), or a GPU (Graphics Processing Unit), and the optical IC may be, for example, a signal conditioner (electric signal relay LSI).
The chip module 100 </ b> A includes a glass interposer 5 and a package substrate 3. A glass interposer 5 is mounted on the upper surface of the package substrate 3.

  The package substrate 3 includes a via hole 9 and a conductor layer 10. BGA (Ball Grid Array) balls 8 are formed on the lower surface of the package substrate 3.

  Bumps 4-2 and 4-3 are formed on the upper surface of the glass interposer 5 (the surface that is not connected to the package substrate 3). The glass interposer 5 and the ASIC 1 and the optical IC 2 are electrically connected to each other by bumps 4-2 and 4-3. Bumps 4-1 are formed on the lower surface of glass interposer 5 (the surface connected to package substrate 3). The package substrate 3 and the glass interposer 5 are electrically connected by bumps 4-1.

  The glass interposer 5 includes at least a glass core 30 and a conductor layer 11. The conductor layer 11 is disposed on each of the upper surface and the upper surface of the glass core 30. Each of TGV6 and TGV7 is formed in the glass core 30.

  The TGV 6 is formed by applying copper plating to the inside of the through hole. Electrical connection between the upper and lower sides of the glass core 30 is established by the TGV 6. As a result, a high-density signal wiring between the ASIC 1 and the optical IC 2 is formed. The treatment applied to the inside of the TGV 6 is not limited to copper plating, and any material or technique can be used.

  The conductor layer 11 includes a wide plane to serve as a return plane for signal wiring. Therefore, the structure composed of the conductor layer 11 and the glass core 30 functions like a cavity resonator, and resonance noise is excited by a signal passing through the TGV 6 and a current change in the power supply / ground. A broken line 20 in FIG. 1 schematically shows the electric field strength of resonance noise. As shown in the figure, the place connected by TGV6 is a node of resonance voltage.

  The TGV 7 is formed by filling a through hole with a predetermined material. The planes of the upper and lower conductor layers 11 of the glass core 30 are electrically connected by the TGV 7. As shown in the drawing, both ends of the TGV 7 are effective when placed at positions where the electric field strength is large and the antinodes of the noise voltage are present, but the present invention is not limited to this.

  In addition, it can be predicted that the position of the antinode of resonance is an intermediate point between the nodes, and the end of the glass core 30 also becomes the antinode of resonance. Therefore, as shown in FIG. 2, it is effective that the position where the TGV 7 is disposed is at least one of the corners of the glass core 30, along the outer peripheral edge of the glass core 30, and between the TGVs 6. When TGV7 is arranged between TGV6, it is preferable that the intermediate point between TGV6 or near the intermediate point. If possible, it is preferable to perform an electromagnetic field analysis to obtain an accurate resonance voltage distribution and place the TGV 7 at the antinode position. Since TGV7 has a high resistance, the electric field distribution of resonance does not change due to the additional arrangement of TGV7. For this reason, it is possible to determine the position of the TGV 7 without repeatedly specifying the position of the antinode of resonance by electromagnetic field analysis or the like.

  When the voltage between the upper and lower sides of the glass core 30 increases due to resonance noise, current flows through the TGV 7 and electromagnetic energy is converted into thermal energy. As a result, resonance noise is attenuated, and signal quality deterioration and power supply capability deterioration can be avoided.

  It should be noted that the electric resistance value of TGV7 needs to be higher than about 1Ω in order to have a sufficient resonance damping effect. In this embodiment, an electric resistance value higher than about 1Ω is realized by a predetermined material filled in the through hole. The planes connected by the TGV 7 must have the same potential in terms of DC (Direct Current). The case of the same potential in terms of DC is, for example, the case where both are ground planes or both are power supply planes.

For example, the electrical resistance value of through vias such as TGV6 due to copper plating is almost much lower than about 1Ω. For example, when a TGV having a diameter of 20 μm and a copper plating thickness of 5 μm is formed on a glass core having a thickness of 100 μm, the electric resistance value is 10 mΩ or less. Therefore, TGV7 can be said to be a through via having a higher electrical resistance value than TGV6.
It should be noted that the numerical value such as “1Ω” here includes not only this number but also an error range caused by, for example, a model error or a measurement error.

In order to show the above effect, eigenmode analysis was performed on the resonance of the glass core by the three-dimensional finite element method. This analysis is performed on a simplified structure in order to directly evaluate the influence on resonance. FIG. 3 shows a model for eigenmode analysis. In the model 300, copper planes 50-1 and 50-2 are attached to the upper and lower surfaces of the glass core 30 having a thickness of about 30 mm and a thickness of about 100 μm. In the model 300, the position that becomes the antinode of resonance is, for example, the positions 51 of the four corners of the plane. In such a case, a Q value representing the stability of resonance was obtained under each of the following three conditions: Condition 1 to Condition 3. The lower the Q value, the faster the resonance attenuation.
Condition 1: Do not place anything at position 51 Condition 2: Place a TGV by copper plating at position 51 and electrically connect the upper and lower copper planes 50-1 and 50-2 Condition 3: From position 1 at about 1Ω The upper and lower copper planes 50-1 and 50-2 are electrically connected by arranging a TGV having a higher electrical resistance value. Each TGV has a diameter of about 20 μm and a TGV having an electrical resistance value higher than about 1Ω The actual electric resistance value was set to 5Ω per one.

  FIG. 4 shows a comparison result of the Q values in the model 300. The graph 400 shows the Q value for each resonance from the primary mode to the tertiary mode for each of the above conditions 1 to 3. For example, the bar 401 in the first mode indicates the Q value in the condition 1, the bar 402 indicates the Q value in the condition 2, and the bar 403 indicates the Q value in the condition 3. As shown in the figure, compared to condition 1 (bar 401), in condition 3 (bar 403), the Q value is 1/6 or less. Although the Q value reduction effect is recognized even under condition 2 (bar 402), it can be seen that the effect is small compared to condition 3 (bar 403).

  Next, in order to examine the influence of the electrical resistance value, the electrical resistance value of the TGV was changed for the model 300, and the transition of the Q value and frequency of the primary mode of resonance was analyzed. FIG. 5 shows the relationship between the electrical resistance value of TGV and the Q value of the primary mode. The horizontal axis of the graph 500 is the electrical resistance value of TGV, and the vertical axis is the Q value.

As shown in the figure, it can be seen that the Q value takes the lowest value in the vicinity of the electric resistance value of about 1Ω to about 10Ω. When the electrical resistance of the TGV is low, the resonance attenuation effect is small because the amount of resonance converted into thermal energy in the TGV is small. In addition, when the electrical resistance of the TGV is too high, no current flows through the TGV, so the attenuation effect is small. When the electrical resistance of TGV is extremely high (for example, about 1000Ω or more), the resonance damping effect cannot be obtained, and it is more desirable to set the electrical resistance to about 100Ω or less.
FIG. 6 shows the relationship between the electrical resistance value of TGV and the frequency of the primary mode. The horizontal axis of the graph 600 is the electrical resistance value of TGV, and the vertical axis is the frequency.

  As shown in the figure, the frequency is different between the low resistance side and the high resistance side, and transitions between about 1Ω and about 10Ω. The frequency value on the high resistance side matches the frequency when TGV is not inserted, and the frequency value on the low resistance side is equal to the frequency when normal TGV is inserted. This indicates that when a through via of about 1Ω or less is inserted, the position of the resonance antinode / node changes, whereas when a TGV greater than about 1Ω to about 10Ω is inserted, the antinode of resonance -This means that the position of the clause does not change.

From these results, it can be seen that by inserting a TGV having an electric resistance value greater than about 1Ω, the Q value can be effectively lowered without changing the resonance antinodes and nodes. In the case of the TGV structure in the model 300, a TGV having an electric resistance value of about 5Ω can be realized by using, for example, a silver paste having a volume resistivity of about 5 μΩm.
FIG. 7 is a diagram for explaining an example of TGV formation. In the figure, only the formation with respect to the glass core 30 will be described for simplification.

  TGV is formed by the steps in the order of FIGS. 7A to 7E. FIG. 7A shows only the glass core 30. FIG. 7B is an example in which a through hole 31-1 is provided in the glass core 30 with a laser or the like. Here, the through-hole 31-1 is provided only at the position where the TGV 7 is formed. FIG. 7C shows an example in which the through-hole 31-1 is filled with a predetermined material. In this way, the TGV 7 having an electrical resistance value greater than 1Ω is formed. FIG. 7D shows an example in which a through hole 31-2 is provided in the glass core 30 with a laser or the like. Here, the through hole 31-2 is provided at a position where the TGV 6 is formed. FIG. 7E is an example in which copper plating is applied to the glass core 30 in which the through hole 31-2 is formed. Thereby, TGV6 is formed. In the case of this step, the conductor layer 11 can be formed simultaneously with the formation of the TGV 6 by this copper plating.

Note that TGV formation is not limited to the above. For example, a through hole may be formed in a position where the TGV 6 or TGV 7 is provided in one process, and when filling the through hole, the through hole forming the TGV 6 may be masked.
[Example 2]

  FIG. 8 is an example of a longitudinal sectional view of the chip module 100B of the second embodiment, and FIG. 9 is an example of a transverse sectional view of the chip module 100B. More specifically, FIG. 9 is an example of a cross-sectional view taken along line CC in FIG. 8, and FIG. 8 is an example of a cross-sectional view taken along line DD in FIG.

  The difference between the first embodiment and the second embodiment is that a TGV composed of a conductive thin film and a resist is used in place of the TGV in which a through hole is filled with a predetermined material in order to realize a through via having an electric resistance larger than 1Ω. It is a point to use. Since the electric resistance value of the conductor thin film is high, the same resonance attenuation effect as that in the above embodiment can be obtained.

The electrical resistance value of TGV13 is preferably greater than about 1Ω as described above. Further, as described above, it is most effective to arrange the TGV 13 at the antinode of resonance as described above.
FIG. 10 is a diagram for explaining an example of TGV formation. In the figure, only the formation with respect to the glass core 30 will be described for simplification.

TGV is formed by the steps in the order of FIGS. FIG. 10A shows only the glass core 30. FIG. 10B is an example in which a through hole 31 is provided in the glass core 30 with a laser or the like. Here, the through hole 31 is provided at a position where the TGV 6 or TGV 13 is formed. FIG. 10C shows an example in which the conductive thin film 32 is formed inside the through hole 31 by, for example, electroless plating. The conductor thin film 32 is formed with a thickness of about 1 μm or less using a conductor having a high resistivity such as a P—Ni alloy. FIG. 10D shows an example in which a resist 33 is filled in the through hole 31 in which the conductive thin film 32 is formed at the position where the TGV 13 is formed. Thereby, TGV13 is formed. For example, photolithography (Photolithography) technology can be used for the resist 33 and its solidification, but the resist 33 is not limited thereto. FIG. 10E shows an example in which copper plating is applied to the glass core 30 on which the TGV 13 is formed. Thereby, copper plating is formed inside the through-hole 31 in which the conductive thin film 32 is formed but the resist 33 is not filled, and the TGV 6 and the conductor layer 11 are formed.
In this modification, the TGV drilling process can be performed once without including the steps such as the mask described above.

In this modification, the hollow portion of the TGV 13 is filled with a resist, but it may be left hollow. However, the strength of the glass core 30 increases when the hollow portion is filled with a resist or the like.
[Example 3]

  FIG. 11 is an example of a vertical cross-sectional view of the chip module 100C of the third embodiment. In this embodiment, it is possible to cope with the case where the planes of the upper and lower surfaces of the glass core 30 connected by the TGV 7 are not at the same potential. For this purpose, the chip module 100C is provided with a capacitor 14 in the vicinity of the TGV 7, and the upper and lower planes of the glass core 30 are electrically connected through both the capacitor 14 and the TGV 7. Although the upper and lower planes show an example of the conductor layer 11 in FIG. 11, the upper and lower planes are not limited to this.

  FIG. 12 is an example of a circuit diagram showing a connection relationship. The capacitor 14 is connected in series with the TGV 7 connected to the lower plane 43, and the tip is connected to the upper plane 42. That is, the two planes are electrically connected via the TGV 7 and the capacitor 14 connected in series.

  The capacitor 14 is preferably a small size because of the mounting space. An example of such a capacitor is a thin film capacitor, but is not limited thereto.

In this way, by connecting the two planes via the TGV 7 and the capacitor connected in series, it is possible to obtain a resonance damping effect even when these planes are not DC in the same potential. The case where the plane is not at the same potential in terms of DC is, for example, the case where one is a power supply and the other is a ground plane.
In addition, although the capacitor | condenser is arrange | positioned here at the upper part of the glass core 30, not only this but a capacitor | condenser may be arrange | positioned at the lower part of the glass core 30. FIG.

  Further, instead of TGV7, two planes may be connected in series via TGV13 and a capacitor. That is, it is only necessary that two planes can be connected in series via a TGV and a capacitor having an electrical resistance value greater than about 1Ω.

In addition, when the upper and lower planes of the glass core 30 have the same potential and the non-equal potential, a structure connected without a capacitor can be mixed as in the first and second embodiments. it can.
[Example 4]

  FIG. 13 is an example of a vertical cross-sectional view of the glass interposer of Example 4. The chip module 100D of the present embodiment is different from the second embodiment in the range in which the conductor thin film 34 is provided. In the chip module 100D, the conductor thin film 34 is formed not only on the inside of the through hole but also on each of the upper and lower surfaces (for example, the surface 1301 and the surface 1302) of the glass core 30, and the copper plating 35 is applied thereon. A conductor layer is formed. Except for this point, the structure of the chip module 100D is the same as that of the chip module 100B.

In the structure of the present embodiment, the resonance noise attenuation effect can be obtained by the TGV having an electric resistance larger than about 1Ω as in the above embodiment. Moreover, since the resonance noise current excited in the glass core is concentrated on the glass core 30 side of the upper and lower planes due to the skin effect, the conductive thin film 34 provided on the upper and lower surfaces of the glass core 30 also causes resonance noise. A damping effect is obtained.
[Example 5]

  FIG. 14 is an example of a vertical cross-sectional view of the chip module 100E of Example 5, and FIG. 15 is an example of a horizontal cross-sectional view of the chip module 100E. More specifically, FIG. 15 is an example of a cross-sectional view taken along line EE in FIG. 14, and FIG. 14 is an example of a cross-sectional view taken along line FF in FIG.

  The difference between this embodiment and the above embodiment is that a Si interposer 60 is further mounted on the package substrate 3 and the ASIC 1 is mounted across the Si interposer 60 and the glass interposer 5.

  14 and 15, four glass interposers 5-1 to 5-4 are mounted on one package substrate 3 in the chip module 100E. Each glass interposer 5 has one IC 2 mounted thereon, and one chip module 100E includes a total of four optical ICs 2-1 to 2-4.

  A Si interposer 60 is disposed at the center of the ceramic package substrate 3 or in the vicinity thereof, and the glass interposer 5 is disposed at least at a part of the periphery thereof. At least one ASIC 1 is disposed on the Si interposer 60. The ASIC 1 is arranged so as to straddle both the glass interposers 5-1 to 5-4 and the Si interposer 60. That is, the ASIC 1 is electrically connected to the package substrate 3 via each of the glass interposer 5 and the Si interposer 60.

  Accordingly, at least a part of the occupation range of the Si interposer 60 when the chip module 100E is viewed from above is included in the occupation range of the ASIC 1. Further, when the chip module 100E is viewed from above, the occupation range of the Si interposer 60 and the ASIC 1 is arranged so as to overlap a part of the occupation range of each of the four glass interposers 5-1 to 5-4. Further, when the chip module 100E is viewed from above, the occupation range of the Si interposer 60 and the ASIC 1 is arranged so as not to overlap with the occupation range of each IC 2 mounted on each of the glass interposers 5.

  The ASIC 1 is provided with an electrode portion for high-speed signals for connecting to the glass interposer 5. Although this electrode part is not limited, it is a pin, a bump, a lead, etc. (for example, bump 1401), for example, and is provided along the outer periphery of ASIC1 in this case. The high-speed signal wiring is connected to each of the optical ICs 2-1 to 2-4 via the respective signal wirings (not shown) of the glass interposers 5-1 to 5-4. As described above, the high-speed signal can be transmitted through the low-loss glass interposer to suppress the deterioration of the signal quality.

  The ASIC is provided with a low-speed signal for connecting to the Si interposer 60 and an electrode portion for power supply / ground of the core circuit. Although this electrode part is not limited, it is a pin, a bump, a lead, etc. (for example, bump 1402), for example, and is provided in the center vicinity of ASIC1 in this case. This wiring is connected to the package substrate 3 through the through via 61 of the Si interposer 60. As described above, since power is supplied to the power source / ground of the core circuit having a large current through the Si interposer having a large loss, the problem of resonance noise can be made difficult to occur.

  In addition, each of the glass interposers 5 includes any one of the configurations of the first to fourth embodiments described above. FIG. 14 shows an example including TGV7 as in the first embodiment, but TGV13 may be used. In any of TGV7 and TGV13, the arrangement position is the same as in the above embodiment. When a plurality of glass interposers 5 are mounted, each glass interposer 5 may include a configuration of a different example among the above-described first to fourth examples. Thereby, as described above, the resonance on the glass interposer side can be attenuated.

Note that the number of each of the Si interposer 60, the glass interposer 5, and the ASIC 1 mounted on one package substrate 3 may be one or more, and is not limited to that illustrated.
[Example 6]
FIG. 16 is a side view of the substrate portion of the information processing apparatus in which the chip module 100 is incorporated.
Note that the information processing equipment here refers to a device that includes an arithmetic device such as an IC or LSI and that can execute a desired arithmetic operation.

  The information processing device 200 includes a plurality of chip modules 100, a plurality of motherboards 71, a plurality of connectors 72, a backplane board 73, an optical fiber 74, and the like. These numbers may be singular or plural and are not limited to those shown. However, efficient information processing can be performed by performing processing simultaneously by the plurality of chip modules 100 and the motherboard 71.

  Any one or a plurality of chip modules 100-1 to 100-3 of the first to fifth embodiments are mounted on each of the motherboards 71-1 to 71-3. FIG. 16 shows an example in which the chip module 100E is mounted. Each of the mother boards 71-1 to 71-3 is electrically connected to the backplane board 73 by connectors 72-1 to 72-3. Optical fibers 74-1 and 74-2 are connected to the optical ICs mounted on each of the chip modules 100-1 to 100-3, and the chip modules 100-1 to 100-3 communicate with each other by optical signals. Is possible.

  Since the chip modules 100-1 to 100-3 are connected to the ASIC and the optical IC with high density and low noise, the chip modules 100-1 to 100-3 can have a broadband signal transmission capability by being mounted as described above. In addition, high-speed optical signal transmission can be performed between the chip modules 100-1 to 100-3. Thereby, the information processing capability can be improved.

  The invention made by the present inventor has been specifically described based on an example. In the field of information equipment such as servers, it is desired to improve the transmission throughput in the apparatus in order to improve the performance of the apparatus. For example, in inter-substrate transmission of about 60 cm connecting a processing node and a switch node, in order to maintain a transmission performance trend even in a loss increase accompanying an increase in speed, for example, a transmission distance such as a signal conditioner or an optical module is extended. For this purpose, a relay LSI is used. Also, in the field of information equipment, the required throughput between computing devices and memories (such as DRAM) has been improved year by year as the computing devices (such as CPUs) become multi-core. is necessary.

  In order to realize such technologies, it is necessary to improve the transmission throughput within the substrate. Conventionally, throughput has been improved by improving the transmission speed per wiring. However, at a transmission rate exceeding 25 Gbps, the technical difficulty due to loss increases. Thus, it is conceivable to increase the wiring density as another technique for improving the throughput. By increasing the wiring density, the overall throughput can be improved. In order to increase the wiring density, there is a technique using a Si substrate as a core material.

  In this case, using a Si substrate as a core material, fine wiring of the order of μm is formed on the plane, and the semiconductor chips are electrically connected with high density. The lower package (made of organic or ceramic) is electrically connected via TSV (Through Si Via). Such an implementation is called a 2.5-dimensional implementation.

  Another requirement is cost reduction. In order to reduce costs, there is a technique using glass as a core material. Since glass has a low loss, there is an advantage that the signal waveform is hardly deteriorated.

  However, when glass is used as the core material, since the signal waveform is less deteriorated, noise attenuation is also small. Therefore, the planes on both sides of the core material act like a cavity resonator and cause characteristic deterioration. As a result, the power supply and the ground impedance are degraded, and the characteristics of the signal wiring penetrating the core material are degraded.

  In the embodiment described above, a TGV having an electric resistance value greater than about 1Ω is provided in the glass core. The resonance noise voltage generated in the glass core causes a current to flow when applied to both ends of the TGV. Thereby, the electromagnetic energy of the resonance noise is converted into heat energy, and the resonance noise can be efficiently attenuated. Further, since the current flowing through the TGV is very small, the influence of the addition of the TGV on the position of the resonance antinode or node can be ignored. For this reason, unlike the case of adding a TGV that does not have an electrical resistance value greater than 1Ω, once the resonance noise distribution is calculated, the TGV may be placed at the antinode position of the resonance based on the distribution. This makes it easy to design with countermeasures against resonance noise.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above, and various modifications can be made without departing from the scope of the invention. Nor. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  100: chip module, 1: ASIC, 2: optical IC, 3: package substrate, 4: bump, 5: glass interposer, 6: TGV, 7: TGV, 8: bump, 9: through via, 10: conductor layer, 11 : Conductor layer, 13: TGV, 60: Si interposer, 200: Information processing equipment

Claims (8)

A glass interposer between the semiconductor chip and the package substrate;
The glass interposer has a through via having an electric resistance value larger than about 1Ω. The chip module according to claim 1,
The glass interposer includes a glass core,
A chip module characterized by realizing a through via having an electric resistance value larger than about 1Ω by filling a predetermined material into a through via provided in the glass core. The chip module according to claim 1,
The glass interposer includes a glass core,
A chip module characterized in that a through via having an electrical resistance value larger than about 1Ω is realized by a conductive thin film formed inside a through via provided in the glass core. The chip module according to claim 3,
A chip module, wherein a conductive thin film is further formed on the upper and lower surfaces of the glass core. The chip module according to claim 1,
The chip module, wherein the through via and the capacitor are connected in series. The chip module according to claim 1,
The chip module is characterized in that the through via is disposed at least one of a corner of the glass interposer, along an outer peripheral edge, and between through vias that are not through vias having an electric resistance value larger than about 1Ω. The chip module according to claim 1,
Further comprising a Si interposer between the semiconductor chip and the package substrate,
The chip module, wherein the semiconductor chip is electrically connected to the package substrate via each of the glass interposer and the Si interposer.   An information processing apparatus having one or a plurality of chip modules according to any one of claims 1 to 7.

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