JP5981265B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board for mounting a semiconductor element.

  Conventionally, a wiring board having a multilayer structure formed by a build-up method is used as a wiring board for mounting a semiconductor element. A conventional example of such a wiring board is shown in FIG. As shown in FIG. 7, the conventional wiring substrate 200 is formed by laminating buildup portions 32 on the upper and lower surfaces of the core substrate 31. The wiring board 200 is a rectangular flat plate having a length of about several tens of mm on one side and a thickness of about 250 to 1500 μm.

  The core substrate 31 includes a core insulating plate 34 having a plurality of through holes 33, and core wiring conductors 35 deposited in the through holes 33 and on the upper and lower surfaces of the core insulating plate 34. The core insulating plate 34 is formed of a fiber reinforced resin plate in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin. The thickness of the core insulating plate 34 is about 200 to 800 μm. The diameter of the through hole 33 is about 100 to 200 μm. The core wiring conductor 35 is made of copper foil or copper plating. The thickness of the core wiring conductor 35 is about 10 to 30 μm.

  The build-up unit 32 alternately includes build-up insulating layers 37 having a plurality of via holes 36 and build-up wiring conductors 38 deposited in the via holes 36 and on the surface of the build-up insulating layer 37 on the upper and lower surfaces of the core substrate 31. It is formed by laminating a plurality of layers. The buildup insulating layer 37 is formed of a filler-containing resin layer in which an inorganic insulating filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. The thickness of the buildup insulating layer 37 is about 25 to 50 μm. The diameter of the via hole 36 is about 50 to 100 μm. The build-up wiring conductor 38 is made of copper plating. The build-up wiring conductor 38 has a thickness of about 10 to 30 μm.

  A solder resist layer 39 for protecting the outermost buildup wiring conductor 38 is deposited on the surface of the upper and lower buildup portions 32. The solder resist layer 39 is made of a thermosetting resin such as an acrylic-modified epoxy resin. The thickness of the solder resist layer 39 is about 20 to 50 μm.

  A mounting portion 32A on which the semiconductor element S is mounted is formed at the center of the upper surface of the buildup portion 32 on the upper surface side. The mounting portion 32A is a rectangular region having a size corresponding to the semiconductor element S. In general, each side of the mounting portion 32 </ b> A is parallel to the outer periphery of the wiring board 200. The mounting portion 32A is formed with a plurality of semiconductor element connection pads 40 made up of build-up wiring conductors 38 deposited on the uppermost build-up insulating layer 37 on the upper surface side. The diameter of the semiconductor element connection pad 40 is about 50 to 150 μm. Several hundred to several thousand semiconductor element connection pads 40 are arranged in a lattice pattern. The array of the semiconductor element connection pads 40 has lattice points parallel to each side of the square forming the mounting portion 32A at a pitch of about 100 to 300 μm.

  A plurality of external connection pads 41 made of buildup wiring conductors 38 are formed on the lower surface of the buildup portion 32 on the lower surface side and are attached to the lower surface of the uppermost buildup insulating layer 37 on the lower layer side. The diameter of the external connection pad 41 is about 250 to 1000 μm. Several hundred to several thousand external connection pads 41 are arranged in a lattice pattern. The array of the external connection pads 41 has lattice points parallel to the outer periphery of the wiring board 200 at a pitch of about 500 to 2000 μm. Each semiconductor element connection pad 40 and the external connection pad 41 are electrically connected to each other via the build-up wiring conductor 38 and the core wiring conductor 35.

  By the way, in general, the current semiconductor elements have been noticeably increased in speed and capacity. Accordingly, a wiring board on which a semiconductor element is mounted is required to have a form with less electrical loss in high frequency transmission. For this reason, in particular, in a wiring board having a transmission path for transmitting a high-frequency signal, an increase in the number of transmission lines using a differential line as a transmission path for the high-frequency signal. In the differential line, two transmission lines are arranged adjacent to each other with a predetermined interval therebetween, and a transmission loss in high-frequency transmission is reduced by transmitting signals having opposite phases to the transmission lines. .

  Such a differential line will be described with reference to FIGS. 8, 9, and 10. FIG. FIG. 8 is a top view of the wiring board 200 shown in FIG. 7 and mainly shows a set of differential lines. In FIG. 8, the outline of the wiring board 200 and the semiconductor element connection pads 40 are indicated by solid lines, and the wiring conductor 38 and the core wiring conductor 35 constituting the differential line are indicated by broken lines inside and under the wiring board 200. Yes. Further, the semiconductor element mounting portion 32A is indicated by a two-dot chain line. 9 is a perspective view showing only the signal lines of the differential line shown in FIG.

  As shown in FIGS. 8 and 9, the semiconductor element connection pad 40 has a pair 40P for differential lines. The semiconductor element connection pad pairs 40P are arranged adjacent to each other. The external connection pad 41 has a pair 41P corresponding to the semiconductor element connection pad pair 40P. The pair 40P of semiconductor element connection pads and the pair 41P of external connection pads are electrically connected to each other via a pair of strip-shaped wiring conductors 42P provided on the buildup wiring conductor 38 on the upper surface side. It is connected.

  Each pair of strip-shaped wiring conductors 42P extends from below the corresponding pair 40P of semiconductor element connection pads to above the pair 41P of external connection pads. The pair of semiconductor element connection pads 40P and the pair of strip-like wiring conductors 42P are connected via the via holes 36 immediately below the pair of semiconductor element connection pads 40P. The external connection pad pair 41P and the strip-like wiring conductor pair 42P are connected via the through hole 33 and the via hole 36 above the external connection pad pair 41P. The pair of strip-shaped wiring conductors 42P are parallel and extend in parallel with each other at a predetermined width and adjacent interval except for the vicinity of the connection end with the semiconductor element connection pad pair 40P and the vicinity of the connection end with the external connection pad pair 41P. It has an extending part 42A.

  Here, FIG. 10 is a perspective view showing a state of the ground or power supply conductor layer disposed around the pair of strip-shaped wiring conductors 42P. FIG. 10 is a partially transparent perspective view showing only a part of the core wiring conductor 35 and the buildup wiring conductor 38 on the upper surface side. The uppermost buildup wiring conductor 38 located on the upper surface side of the pair of strip-shaped wiring conductors 42 is opposed to the region excluding the connection end of the strip-shaped wiring conductor pair 42P with the semiconductor element connection pad pair 40P and its vicinity. Thus, the ground or power supply conductor layer G1 is arranged. In addition, a ground or power supply conductor layer G2 is disposed on the build-up wiring conductor 38 in the same layer as the pair of strip-shaped wiring conductors 42 so as to surround the strip-shaped wiring conductor pair 42P at a predetermined interval. Further, the build-up wiring conductor 38 and the core wiring conductor 35 below the strip-shaped wiring conductor pair 42P are opposed to the region excluding the connection end of the strip-shaped wiring conductor pair 42P with the external connection pad pair 41P and the vicinity thereof. Thus, the ground or power supply conductor layers G3 to G5 are arranged. In the ground or power supply conductor layers G3 to G5, an oval opening is formed so as to surround the via hole 36 and the through hole 33 that connect the pair 42P of the strip-like wiring conductor and the pair 41P of the external connection pads at a predetermined interval. A is formed. In this differential line, the line width and adjacent interval of the pair of strip-shaped wiring conductors 42P and the ground or power supply conductor layers G1 to G5 are set so that the characteristic impedance of the pair of strip-shaped wiring conductors 42P is approximately 100Ω, for example. The interval has been adjusted.

  According to this wiring board 200, the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 40 via solder to mount the semiconductor element S, and the external connection pad 41 is wired to the external electric circuit board. By connecting to the conductor via solder, the semiconductor element S to be mounted is electrically connected to an external electric circuit board.

  However, although this conventional wiring substrate 200 is designed so that the characteristic impedance in the path from the pair 40P of semiconductor element connection pads to the pair 41P of external connection pads is a value approximating to 100Ω, for example, When a capacitive component is added to the electrode T of the semiconductor element S connected to the connection pad pair 40P, the high-frequency signal reflection loss between the electrode T of the semiconductor element S and the pair of semiconductor element connection pads 40P. In addition, there is a problem that transmission loss increases.

JP 2010-258390 A

  An object of the present invention is to provide a wiring board capable of transmitting a high-frequency signal with low loss when a capacitance component is added to an electrode of a semiconductor element to be mounted.

The wiring board of the present invention includes a plurality of pairs of an insulating substrate formed by laminating an inner insulating layer under a surface insulating layer and a signal semiconductor element connection pad formed on the surface insulating layer. The semiconductor element connection pad is formed on the inner insulating layer, and has a connection end connected to the pad via a via hole immediately below the pair of signal semiconductor element connection pads. A pair of strip-shaped wiring conductors having parallel extending portions extending parallel to each other on the inner insulating layer from the vicinity, and the pair of strip-shaped wiring conductors on the surface insulating layer and below the inner insulating layer A grounding or power supply conductor layer disposed so as to be sandwiched from above and below, wherein the grounding or power supply conductor layer extends in parallel from the connection end of the pair of strip-shaped wiring conductors. Over some parts Of the wavelength of the signal propagating through the pair of the ground or power supply conductor layers and the strip line conductor pairs and said strip line conductors so that the opening of the non-opposing partially protruding along the parallel extending portion It is characterized by being formed with a length of 1/16 or less.

According to the wiring board of the present invention, the ground or power supply conductor layer is grounded or connected to a part of the parallel extending portion from the connection portion of the pair of strip-like wiring conductors connected to the signal semiconductor element connection pads through the via holes. Less than 1/16 of the wavelength of the signal propagating through the pair of band-shaped wiring conductors so that the opening that makes the power supply conductor layer and the pair of band-shaped wiring conductors non-oppose partially extends along the parallel extending portion Since the length is formed, the capacitance component in the portion where the opening is formed becomes small. As a result, when the capacitance component added to the electrode of the semiconductor element is offset by the decrease in the capacitance component of this portion and the capacitance component added to the electrode of the semiconductor element, the high-frequency signal is reduced with low loss. It becomes possible to transmit.

FIG. 1 is a schematic sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a perspective top view of an essential part showing an example of an embodiment of the wiring board of the present invention. FIG. 3 is a perspective view of a main part showing an example of an embodiment of the wiring board of the present invention. FIG. 4 is a perspective view of a main part showing an example of an embodiment of the wiring board of the present invention. FIG. 5 is a perspective view of a principal part showing another example of the embodiment of the wiring board of the present invention. FIG. 6 is a graph showing a simulation result for verifying the effect of the present invention. FIG. 7 is a schematic sectional view showing a conventional wiring board. FIG. 8 is a perspective top view of a main part showing a conventional wiring board. FIG. 9 is a perspective view showing a main part of a conventional wiring board. FIG. 10 is a perspective view showing a main part of a conventional wiring board.

  Next, an example of an embodiment of the wiring board of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing a wiring board 100 of the present invention. As shown in FIG. 1, a wiring board 100 of the present invention is formed by laminating buildup portions 2 on the upper and lower surfaces of a core substrate 1. The wiring board 100 is a rectangular flat plate having a length of about several tens of mm on one side and a thickness of about 250 to 1500 μm.

  The core substrate 1 includes a core insulating plate 4 having a plurality of through holes 3, and core wiring conductors 5 attached to the through holes 3 and the upper and lower surfaces of the core insulating plate 4. The core insulating plate 4 is formed of a fiber reinforced resin plate in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin. The thickness of the core insulating plate 4 is about 200 to 800 μm. The diameter of the through hole 3 is about 100 to 200 μm. The core wiring conductor 5 is made of copper foil or copper plating. The thickness of the core wiring conductor 5 is about 10 to 30 μm. In the following description, the through-hole 3 means one including the core wiring conductor 5 deposited inside.

  The build-up unit 2 has a build-up insulating layer 7 having a plurality of via holes 6 and build-up wiring conductors 8 deposited in the via holes 6 and on the surface of the build-up insulating layer 7 alternately on the upper and lower surfaces of the core substrate 1. It is formed by laminating a plurality of layers. The build-up insulating layer 7 is formed of a filler-containing resin layer in which an inorganic insulating filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. The build-up insulating layer 7 has a thickness of about 25 to 50 μm. The diameter of the via hole 6 is about 50 to 100 μm. The build-up wiring conductor 8 is made of copper plating. The thickness of the buildup wiring conductor 8 is about 10 to 30 μm. In the following description, the via hole 6 means that including the build-up wiring conductor 8 deposited inside.

  A solder resist layer 9 for protecting the outermost buildup wiring conductor 8 is deposited on the surface of the upper and lower buildup portions 2. The solder resist layer 9 is made of a thermosetting resin such as an acrylic-modified epoxy resin. The thickness of the solder resist layer 9 is about 20 to 50 μm.

  A mounting portion 2A on which the semiconductor element S is mounted is formed at the center of the upper surface of the buildup portion 2 on the upper surface side. The mounting portion 2A is a square region having a size corresponding to the semiconductor element S. In general, each side of the mounting portion 2 </ b> A is parallel to the outer periphery of the wiring board 100. In the mounting portion 2A, a plurality of semiconductor element connection pads 10 composed of the uppermost layer buildup wiring conductor 8 on the upper surface side are formed. The diameter of the semiconductor element connection pad 10 is about 50 to 150 μm. The arrangement pitch of the semiconductor element connection pads 10 is about 100 to 300 μm. Although only a small number of semiconductor element connection pads 10 are shown for the convenience of drawing, hundreds to thousands of semiconductor element connection pads 10 are actually arranged in a lattice pattern.

  A plurality of external connection pads 11 made of the outermost layer buildup wiring conductor 8 on the lower layer side are formed on the lower surface of the buildup portion 2 on the lower surface side. The diameter of the external connection pad 11 is about 250 to 1000 μm. The arrangement pitch of the external connection pads 11 is about 500 to 2000 μm. The external connection pads 11 are shown in a small number for the convenience of drawing, but actually hundreds to thousands are arranged in a lattice pattern. Corresponding semiconductor element connection pads 10 and external connection pads 11 are electrically connected to each other via the build-up wiring conductor 8 and the core wiring conductor 5.

  Then, the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 10 via a solder bump, and the external connection pad 11 is connected to a wiring conductor of the external electric circuit board via a solder ball, whereby the mounting portion 2A is connected. The semiconductor element S to be mounted and the external electric circuit board are electrically connected.

  By the way, the wiring board 100 includes a differential line as a transmission path for high-frequency signals. In the differential line, two transmission lines are arranged adjacent to each other with a predetermined interval therebetween, and a transmission loss in high-frequency transmission is reduced by transmitting signals having opposite phases to the transmission lines. .

  Here, an example of the differential line in the wiring board 100 of the present invention will be described with reference to FIGS. FIG. 2 is a top view of the wiring board 100 shown in FIG. 1 and mainly shows a set of differential lines. In FIG. 2, the outline of the wiring board 100 and the semiconductor element connection pads 10 are indicated by solid lines, and the build-up wiring conductor 8 and the through hole 3 constituting the differential line are indicated by broken lines inside and under the wiring board 100. ing. The semiconductor element mounting portion 2A is indicated by a two-dot chain line. FIG. 3 is a perspective view showing only the differential line shown in FIG. In FIGS. 2 and 3, a set of differential lines is shown as a representative, but actually, a larger number of sets of differential lines are arranged.

  As shown in FIGS. 2 and 3, the semiconductor element connection pad 10 has a pair 10P for differential lines. The semiconductor element connection pad pairs 10P are arranged adjacent to each other. The external connection pad 11 has a pair 11P of external connection pads corresponding to the pair 10P of semiconductor element connection pads. These external connection pad pairs 11 </ b> P are arranged adjacent to each other on the outer periphery of the lower surface of the wiring substrate 100. The semiconductor element connection pad pair 10P and the external connection pad pair 11P are electrically connected to each other via the strip-like wiring conductor pair 12P provided on the buildup wiring conductor 8 on the upper surface side. Connected.

  The strip-shaped wiring conductor pair 12P extends from the lower side of the semiconductor element connection pad pair 10P to the upper side of the external connection pad pair 11P in the mounting portion 2A. The pair 10P of semiconductor element connection pads and the pair 12P of strip-like wiring conductors are connected via the via holes 6 immediately below the pair 10P of semiconductor element connection pads. The external connection pad pair 11P and the strip-like wiring conductor pair 12P are connected to each other via the through hole 3 and the via hole 6 above the external connection pad pair 11P. The strip-shaped wiring conductor pair 12P is parallel to each other with a predetermined width and adjacent interval except for the vicinity of the connection end with the semiconductor element connection pad pair 10P and the connection end with the external connection pad pair 11P. It has an extending portion 12A.

  Here, the state of the ground or power supply conductor layer disposed around the pair of strip-like wiring conductors 12P is shown in a perspective view in FIG. FIG. 4 is a partially transparent perspective view showing only a part of the core wiring conductor 5 and the buildup wiring conductor 8 on the upper surface side. The uppermost buildup wiring conductor 8 located on the upper surface side of the pair of strip-shaped wiring conductors 12 is opposed to the region excluding the connection end of the strip-shaped wiring conductor pair 12P with the semiconductor element connection pad pair 10P and the vicinity thereof. Thus, the ground or power supply conductor layer G1 is arranged. The build-up wiring conductor 8 in the same layer as the strip-shaped wiring conductor pair 12P is provided with a ground or power supply conductor layer G2 so as to surround the belt-shaped wiring conductor pair 12P at a predetermined interval. Further, the build-up wiring conductor 8 and the core wiring conductor 5 below the strip-like wiring conductor pair 12P include a region excluding the connection end of the strip-like wiring conductor pair 12P with the semiconductor element connection pad pair 10P and the vicinity thereof, and Grounding or power supply conductor layers G3 to G5 are arranged so as to face the region excluding the connection end with the external connection pad pair 11P and the vicinity thereof. The ground or power supply conductor layers G3 to G5 have an oval opening so as to surround the via hole 6 and the through hole 3 that connect the strip-like wiring conductor pair 12P and the external connection pad pair 11P at a predetermined interval. A is formed.

  Furthermore, in the present invention, the ground or power supply conductor layers G1 to G5 are connected to the ground or power supply conductor layer G1 from the connection end of the strip-like wiring conductor pair 12P with the semiconductor element connection pad pair 10P to a part of the parallel extending portion 12A. Opening B is provided so that G5 and the strip-shaped wiring conductor pair 12P do not face each other. In the parallel extending portion 12A, the characteristic impedance is approximately 100Ω, for example, except for the portion that is not opposed to the ground or the power supply conductor layers G1 to G5. On the contrary, the characteristic impedance is larger than 100Ω in the portion not facing the ground or the power supply conductor layers G1 to G5. Thus, the ground or power supply conductor layers G1 to G5 are connected to the semiconductor element connection pad pair 10P via the via hole 6 from the connection end to a part of the parallel extending portion 12A, or the ground or power supply conductor layer G1. Since the opening B that makes G5 and the strip-shaped wiring conductor pair 12P non-opposing is formed, the capacitance component in the portion where the opening B is formed is reduced. As a result, when the capacitance component added to the electrode T of the semiconductor element S is offset by the decrease in the capacitance component of this portion and the capacitance component added to the electrode T of the semiconductor element S, the high-frequency signal is added. Can be transmitted with low loss. In addition, when the non-opposing portion between the ground or power supply conductor layers G1 to G5 and the strip-like wiring conductor pair 12A does not include a part of the parallel extending portion 12A in the opening B, it does not face the strip-like wiring conductor pair 12A. The capacity component of the portion cannot be made sufficiently small. In addition, when the length of the non-opposing portion between the ground or power supply conductor layers G1 to G5 and the strip-shaped wiring conductor pair 12A exceeds 1/16 of the wavelength of the signal propagating through the strip-shaped wiring conductor pair 12A in the opening B. The impedance mismatching region in the strip-shaped wiring conductor pair 12A becomes too long with respect to the wavelength of the signal, and the reflection of the signal increases. Therefore, in the opening B, the non-opposing portion of the ground or power supply conductor layers G1 to G5 and the strip-shaped wiring conductor pair 12A includes the parallel extending portion 12A and the length of the signal propagates through the strip-shaped wiring conductor pair 12A. It is necessary to be 1/16 or less of the wavelength.

  The present invention is not limited to an example of the above-described embodiment, and various modifications are possible as long as they do not depart from the gist of the present invention. Although the line width of the conductor pair 12P is constant, as shown in FIG. 5, the line width of the region corresponding to the opening B in the pair of strip-like wiring conductors 12P is made smaller than the line width of the remaining region. In this case, the inductance component of the strip-shaped wiring conductor pair 12P increases in the region corresponding to the opening B, and the increase in the inductance component in this portion and the capacitance component added to the electrode T of the semiconductor element S are further increased. When the capacitance component is added to the electrode T of the semiconductor element S to be offset, the high frequency signal can be transmitted with lower loss. When the narrow portion of the strip-shaped wiring conductor pair 12A does not include a part of the parallel extending portion 12A, the inductance of the narrow portion cannot be sufficiently increased. If the length of the narrow portion of the strip-shaped wiring conductor pair 12A exceeds 1/16 of the wavelength of the signal propagating through the strip-shaped wiring conductor pair 12A, the impedance mismatching region in the strip-shaped wiring conductor pair 12A The reflection of the signal increases because it becomes too long with respect to the wavelength of the signal. Accordingly, the narrow portion of the strip-shaped wiring conductor pair 12A includes the parallel extending portion 12A, and the length thereof needs to be 1/16 or less of the wavelength of the signal propagating through the strip-shaped wiring conductor pair 12A. .

  In order to confirm the effect of the present invention, the present inventor created an analysis model according to the present invention and an analysis model for comparison, and analyzed them using an electromagnetic field simulator.

  In the first analytical model according to the present invention, a build-up insulating layer having a thickness of 13 μm and a build-up insulating layer having a thickness of 33 μm was stacked on each of the upper and lower surfaces of the core insulating plate having a thickness of 400 μm. A pair of semiconductor element connection pads for differential lines is provided at the center of the upper surface of the uppermost build-up insulating layer on the upper surface side, and an external for differential lines is provided on the outer periphery of the lower surface of the uppermost build-up insulating layer on the lower surface side. A pair of connection pads was provided. The pair of semiconductor element connection pads had a diameter of 120 μm and a pitch of 220 μm. The pair of external connection pads had a diameter of 600 μm and a pitch of 1000 μm.

  A via hole was provided immediately below the pair of semiconductor element connection pads in the uppermost buildup insulating layer on the upper surface side, and a circular first land connected to the via hole was provided on the upper surface of the underlying buildup insulating layer. Further, a circular second land is provided above the pair of external connection pads on the upper surface of the buildup insulating layer. The diameter of the via hole was 50 μm, and the diameters of the first and second lands were 100 μm. The pitch of the first land was the same as the pitch of the pair of semiconductor element connection pads, and the pitch of the second land was the same as the pitch of the pair of external connection pads.

  Furthermore, a pair of strip-shaped wiring conductors having one end connected to the first land and the other end connected to the second land are provided on the upper surface of the buildup insulating layer. The pair of strip-shaped wiring conductors have parallel extending portions extending in parallel with each other except for both end portions thereof, and are parallel to each other. The pitch of the parallel extending portions in the pair of strip-shaped wiring conductors is 109 μm. The distance between the ends of the pair of strip-shaped wiring conductors increases from the position 100 μm away from the first land toward the center of the first land. Further, the other end portion of the pair of strip-shaped wiring conductors is configured such that the interval is widened from a position 900 μm away from the second land toward the center of the second land.

  On the other hand, through holes were provided above the pair of external connection pads on the core insulating plate, and through hole lands were provided above and below the through holes. The diameter of the through hole was 150 μm, and the diameter of the through hole land was 250 μm. The pitch of the through holes was the same as the pitch of the pair of external connection pads. The inside of the through hole was filled with a hole filling resin.

  Furthermore, via holes stacked in the vertical direction were provided between the through-hole lands and the second lands in the build-up insulating layer on the upper surface side below the outermost layer to connect the second lands and the through-hole lands. A via land was provided on each via hole stacked vertically. In addition, via holes stacked in the vertical direction were provided between the pair of external connection pads and the through-hole lands in the build-up insulating layer on the lower surface side to connect the pair of external connection pads and the corresponding through-holes. A circular via land was provided between the via holes stacked one above the other. The diameter of the via holes stacked above and below was 50 μm, and the diameter of the via land was 100 μm. The pitch of these via holes and via lands was the same as the pitch of the external connection pad pairs.

  The length of the pair of strip-shaped wiring conductors from the first land to the second land was 11 mm. Further, the line width of each pair of strip-shaped wiring conductors was set to 29 μm. The interval between the pair of strip-like wiring conductors in the parallel extending portion was 80 μm.

  Further, a ground solid layer surrounding the pair of strip-shaped wiring conductors and the first and second lands connected thereto with a spacing of about 80 to 90 μm in the horizontal direction was disposed. Also, a solid ground layer facing the pair of strip-shaped wiring conductors was disposed on the surface of each build-up insulating layer and the surface of the core insulating plate above and below the pair of strip-shaped wiring conductors. The solid ground layer on the upper surface side of the core insulating plate has a width so that the solid ground layer and the pair of strip-shaped wiring conductors are not opposed to each other along the pair of strip-shaped wiring conductors from the first land. A first opening having a length of 298 μm and a length of 1 mm was provided. Further, in the solid ground layer except for the uppermost layer, an oval second opening was formed so as to surround a pair of via land, through-hole land, and external connection pad connected to the second land. These second openings were formed by connecting two concentric circles with via lands, through-hole lands, and external connection pads. The diameter of the circle forming these second openings was 550 μm at the second opening on the upper surface side from the core insulating plate and 800 μm at the second opening on the lower surface side from the core insulating plate. The semiconductor element connection pads, external connection pads, strip-shaped wiring conductors, lands, and other conductors had the same physical properties as copper and had a thickness of 15 μm. And the electrode of the semiconductor element was connected to the pair of semiconductor element connection pads. It was assumed that a capacitance component of 200 fF was added to the electrode of the semiconductor element.

  In the second analysis model according to the present invention, the line width from the connection end with the first land to a part of the parallel extending portion in the pair of strip-shaped wiring conductors is 12 μm over a length of 1 mm, and the remaining width is 29 μm. And the interval between the pair of strip-like wiring conductors in the parallel extending portion is the same as that of the first analysis model according to the present invention described above except that the width is 97 μm at the 12 μm portion and 80 μm at the 29 μm width portion. .

  In the analysis model for comparison, in the solid ground layer on the upper surface side than the core insulating plate, the solid ground layer and the strip wiring conductor pair are not opposed to each other along the pair of strip wiring conductors from the first land. The first analysis model according to the present invention is the same as that described above except that the first opening is not provided.

  About these analysis models, the simulation result which performed the electromagnetic field analysis using HFSS by ANSYS is shown in FIG. As shown in FIG. 6, it can be seen that the first analysis model and the second analysis model according to the present invention have less loss in both reflection characteristics and transmission characteristics than the analysis model for comparison. It can be seen that the second analysis model according to the present invention has less loss in both reflection characteristics and transmission characteristics than the first analysis model.

6... Via hole 7... Insulating layer 10... Semiconductor element connection pad 10 P... Signal signal semiconductor element connection pad pair 12 A. ... Pairs of strip-shaped wiring conductors B ... Openings

Claims (2)

An insulating substrate formed by laminating an inner insulating layer under a surface insulating layer; a plurality of semiconductor element connection pads including a pair of signal semiconductor element connection pads formed on the surface insulating layer; and An inner insulating layer formed on an inner insulating layer, having a connection end connected to the pad via a via hole immediately below the pair of signal semiconductor element connection pads and from the vicinity of the connection end A pair of strip-shaped wiring conductors having parallel extending portions that extend in parallel with each other, and the pair of strip-shaped wiring conductors are arranged on the surface insulating layer and below the inner insulating layer so as to sandwich the pair of strip-shaped wiring conductors from above and below. A grounding or power supply conductor layer, wherein the grounding or power supply conductor layer extends from the connection end of the pair of strip-like wiring conductors to a part of the parallel extending portion. Or power 1 opening 16 of the wavelength of signals propagating pairs of said strip conductor so as to project partially along the parallel extending portions that the the body layer and the pair of the band conductor and the non-facing A wiring board having the following length: The band-shaped wiring conductor pair has a width from the connecting end to a part of the parallel extending portion that is not more than 1/16 of the wavelength of a signal propagating through the band-shaped wiring conductor pair. The wiring board according to claim 1, wherein the wiring board is also narrow.

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