JP2012033529A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which has a small reflection loss and an insertion loss of a signal thereby transmitting the signal correctly.SOLUTION: The wiring board comprises: an insulating substrate 10 constituted by a laminate of a plurality of insulation layers 11 to 17; a pair of external connection pads 41 and 42 for a pair transmission channel formed on an undersurface of the insulating substrate 10; a plurality of conductor layers 22 to 27 provided between the insulation layers 11 to 17 in which openings 91a to 96a are formed at positions corresponding to the pair of external connection pad 41 and 42; penetration conductors 52 to 57 which are electrically connected to the pair of external connection pads 41 and 42 at corresponding positions in the openings 91a to 96a and penetrate the plurality of insulating layers 11 to 17. The conductor layers 22 to 27 have power supply patterns surrounding the openings 91a to 96a independently from its surrounding power supply layers 73 to 78, and upper and lower power supply patterns 91 to 96 are connected each other to the same power supply potential by the penetration conductor 52 to 57.

Description

  The present invention relates to a wiring board for mounting a semiconductor element such as a semiconductor integrated circuit element.

  A small-sized wiring board for mounting a semiconductor element has a plurality of conductor layers for wiring conductors disposed inside and on the surface of an insulating substrate formed by laminating a plurality of insulating layers, and a through conductor that penetrates the insulating layer Thus, a multilayer wiring structure in which the upper and lower wiring conductors are connected to each other is formed. A plurality of semiconductor element connection pads are formed in the central portion of the upper surface of the insulating substrate, to which the electrodes of the semiconductor element are electrically connected via solder bumps, etc. The wiring conductor of the external electric circuit substrate is formed on the lower surface of the insulating substrate. External connection pads are formed which are electrically connected to each other via solder balls or the like. These semiconductor element connection pads and external connection pads are electrically connected to each other by wiring conductors and through conductors disposed on the surface and inside of the insulating substrate.

  Recently, a wiring board for mounting a semiconductor element is required to have a form with less electrical loss in high-frequency transmission. Therefore, a wiring board having a pair transmission line that functions as a differential line is used as a transmission line for signals. The pair transmission line is provided with two strip-shaped wiring conductors extending in parallel with each other at a predetermined interval on the surface or inside of the insulating substrate as a pair, and for grounding or power supply above, below, left and right of the two strip-shaped wiring conductors forming the pair The conductors are formed by providing impedance matching at predetermined intervals. Further, the through conductors used for connecting the paired strip-shaped wiring conductors and the upper and lower conductor layers are also provided so as to be adjacent to each other in pairs at a predetermined interval.

  FIG. 4 shows a conventional example of a wiring board having a pair transmission line as described above. As shown in FIG. 4, the conventional wiring board 200 has build-up insulating layers 113, 112, and 111 stacked on the upper surface of the core insulating layer 114 and a build-up insulating layer on the lower surface of the insulating layer 114. Conductor layers 121, 122, 123, 124 for wiring conductors between the upper and lower surfaces of the insulating substrate 110 formed by laminating 115, 116 and 117 and between the insulating layers 111, 112, 113, 114, 115, 116, 117, 125, 126, 127, 128 are arranged.

  A semiconductor element connection pad 130 that is electrically connected to an electrode terminal of the semiconductor element S via a solder bump B1 is formed at the center of the upper surface of the insulating substrate 110. An external electric circuit board is formed on the lower surface of the insulating substrate 110. External connection pads 140 that are electrically connected to the wiring conductors via solder balls (not shown) are formed. The semiconductor element connection pads 130 and the external connection pads 140 are wiring conductors formed in the conductor layers 121 to 128 and through conductors 151 penetrating the insulating layers 111, 112, 113, 114, 115, 116, 117, respectively. , 152, 153, 154, 155, 156 and 157 are electrically connected to each other. Furthermore, a solder resist layer 161 having an opening exposing the central portion of the semiconductor element connection pad 130 is deposited on the surfaces of the uppermost insulating layer 111 and the conductor layer 121, and the lowermost insulating layer 117 and the conductor are exposed. A solder resist layer 162 having an opening exposing the central portion of the external connection pad 140 is deposited on the surface of the layer 128.

  Here, an example of a pair transmission path in a conventional wiring board will be described. FIGS. 5A to 5D and FIGS. 6E to H are parts of the conductor layers 121, 122, 123, 124, 125, 126, 127, and 128 and the through conductors in the wiring board 200 described above. 5 is a top view showing only a part of 151, 152, 153, 154, 155, 156, and 157. FIG.

  FIG. 5A shows the conductor layer 121. The conductor layer 121 includes a pair 131 and 132 of semiconductor element connection pads 130 connected to the pair transmission line, and a power supply layer 171 connected to the first power supply potential. The semiconductor element connection pads 131 and 132 are circular having a diameter of about 100 to 200 μm, and are adjacent to each other at a pitch of about 110 to 250 μm. The power supply layer 171 extends in a solid shape from the vicinity of the central portion of the insulating substrate 110 to the vicinity of the outer peripheral edge.

  FIG. 5B shows the conductor layer 122 and the through conductor 151 connected thereon. The conductor layer 122 includes a pair of strip-like wiring conductors 181 and 182 extending from below the semiconductor element connection pads 131 and 132 to above the pair 141 and 142 of the external connection pad 140 described later, and the power supply layer 171 described above. Similarly, the power supply layer 172 connected to the first power supply potential is included. The pair of strip-like wiring conductors 181 and 182 extend in parallel at a predetermined interval except for the ends thereof, and one end thereof is connected to the semiconductor element connection pads 131 and 132 by the through conductor 151 and the other end. The portion extends to a position corresponding to the central portion of the external connection pads 141 and 142. The power supply layer 172 is arranged in a solid shape so as to surround the strip-like wiring conductor pairs 181 and 182 at a predetermined interval, and is formed in an oval shape at a position corresponding to the external connection pad pairs 141 and 142 described later. Having an opening 172a. The power supply layer 172 is connected to the upper power supply layer 171 by the through conductor 151 in the vicinity of the strip-shaped wiring conductors 181 and 182 and the opening 172a.

  FIG. 5C shows the conductor layer 123 and the through conductor 152 connected thereon. The conductor layer 123 has a power supply layer 173 connected to a second power supply potential different from the first power supply potential. The power supply layer 173 has an oval opening 173 a at a position corresponding to the pair of external connection pads 141 and 142. And in the opening part 173a, the penetration conductor 152 is connected to the other end of the strip | belt-shaped wiring conductors 181 and 182 mentioned above.

  FIG. 5D shows the conductor layer 124 and the through conductor 153 connected thereto. The conductor layer 124 has a power supply layer 174 connected to the same second power supply potential as the power supply layer 173 described above. The power supply layer 174 has an oval opening 174 a at a position corresponding to the pair of external connection pads 141 and 142. In the vicinity of the opening 174a, the through conductor 153 is connected to the upper power supply layer 173. Further, the through conductor 153 is connected to the upper through conductor 152 in the opening 174a.

  FIG. 6E shows the conductor layer 125 and the through conductor 154 connected thereon. The conductor layer 125 has a power supply layer 175 connected to a third power supply potential different from the first and second power supply potentials. The power supply layer 175 has an oval opening 175 a at a position corresponding to the pair of external connection pads 141 and 142. Further, the through conductor 154 is connected to the upper through conductor 153 in the opening 175a.

  FIG. 6F shows the conductor layer 126 and the through conductor 155 connected thereon. The conductor layer 126 has a power supply layer 176 connected to the same third power supply potential as the power supply layer 175 described above. The power supply layer 176 has an oval opening 176 a at a position corresponding to the pair of external connection pads 141 and 142. In the vicinity of the opening 176a, the through conductor 155 is connected to the upper power supply layer 175. A through conductor 155 connected to the upper land 175b is disposed in the opening 176a.

  FIG. 6G shows the conductor layer 127 and the through conductor 156 connected thereon. The conductor layer 127 has a power supply layer 177 connected to the same third power supply potential as the power supply layers 175 and 176 described above. The power supply layer 177 has an oval opening 177 a at a position corresponding to the pair of external connection pads 141 and 142. In the vicinity of the opening 177a, the through conductor 156 is connected to the upper power supply layer 176. A through conductor 156 connected to the upper through conductor 155 is disposed in the opening 177a.

  FIG. 6 (h) shows the conductor layer 128 and the through conductor 157 connected thereon. The conductor layer 128 includes the external connection pad 140 pair 141 and 142 connected to the above-described strip-like wiring conductor pair 181 and 182, and the above-described power supply layer 178 connected to the second power supply potential. Have. The external connection pads 141 and 142 are circular with a diameter of about 300 to 500 μm, and are adjacent to each other with a pitch of about 500 to 1000 μm. The through conductor 157 is connected to the upper through conductor 156. The power supply layer 178 has an oval opening 178 a at a position corresponding to the pair of external connection pads 141 and 142.

  With the configuration as described above, there is a pair transmission path in which the pair of semiconductor element connection pads 131 and 132 and the pair of external connection pads 141 and 142 are connected via the pair of strip-like wiring conductors 181 and 182 and the through conductors 151 to 157. Is formed.

  However, according to this conventional pair transmission line, the power supply layers 172 to 177 in which the through conductors 152 to 157 connecting the pair of strip-like wiring conductors 181 and 182 and the pair of external connection pads 141 and 142 are connected to different power supply potentials. Since the connection is made through the through conductors 152 to 157 passing through the openings 172a to 177a, the characteristic impedances of the through conductors 152 to 157 passing through the openings 172a to 177a are difficult to match. As a result, when the signal propagating through the pair transmission line becomes a high frequency exceeding, for example, 10 GHz, the reflection loss and insertion loss of the signal become large, and it becomes difficult to propagate the signal normally.

JP 2004-289094 A

  An object of the present invention is to provide a wiring board capable of normally transmitting a signal with a small signal reflection loss and insertion loss even if the signal propagating through the pair transmission line is a high frequency exceeding 10 GHz, for example. It is to provide.

  The wiring board of the present invention is arranged between the insulating layer, an insulating board formed by laminating a plurality of insulating layers, a pair of external connection pads for a pair transmission path formed on the lower surface of the insulating board, and the insulating layer. A plurality of conductor layers having openings formed at positions corresponding to the pairs of external connection pads; and the plurality of insulating layers electrically connected to the pairs of external connection pads at positions corresponding to the openings. A wiring board comprising a through conductor penetrating through the conductor layer, wherein the conductor layer has a power source pattern surrounding the opening independently of the surrounding conductor layer, and the upper and lower power source patterns are the same power source by the through conductor. It is characterized by being connected to a potential.

  According to the wiring board of the present invention, the plurality of power supply layers in which the openings are formed at positions corresponding to the pairs of the external connection pads for the pair transmission lines have the first power supply pattern surrounding the openings as the surrounding power supply. Since the upper and lower first power supply patterns are independent from each other and are connected by a through conductor, the through conductor connected to the pair of external connection pads is surrounded by the first power supply pattern having the same potential. Therefore, the characteristic impedance is easily matched. Accordingly, it is possible to provide a wiring board capable of normally transmitting a signal with a small signal reflection loss and insertion loss even if a signal propagating through a pair transmission line has a high frequency exceeding, for example, 10 GHz. it can.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a plan view showing only a part of the conductor layer and part of the through conductor of the wiring board shown in FIG. FIG. 3 is a plan view showing only a part of the conductor layer and a part of the through conductor of the wiring board shown in FIG. FIG. 4 is a schematic cross-sectional view showing a conventional wiring board. FIG. 5 is a plan view showing only a part of the conductor layer and part of the through conductor of the wiring board shown in FIG. FIG. 6 is a plan view showing only a part of the conductor layer and part of the through conductor of the wiring board shown in FIG.

  Next, an example of an embodiment of the wiring board of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing a wiring board 100 of this example. In the figure, reference numeral 10 denotes an insulating substrate formed by laminating insulating layers 11, 12, 13, 14, 15, 16, and 17, 21, 22. 23, 24, 25, 26, 27 and 28 are conductor layers, 30 is a semiconductor element connection pad, 40 is an external connection pad, 51, 52, 53, 54, 55, 56 and 57 are through conductors, and 61 and 62 are solders. It is a resist layer. In the wiring substrate 100 of this example, build-up insulating layers 13, 12 and 11 are laminated on the upper surface of the core insulating layer 14, and build-up insulating layers 15, 16 and 17 are formed on the lower surface of the insulating layer 14. Conductive layers 21, 22, 23, 24, 25, 26, 27, 28 for wiring conductors between the upper and lower surfaces of the insulating substrate 10 and the insulating layers 11, 12, 13, 14, 15, 16, 17. Is arranged. A semiconductor element connection pad 30 that is electrically connected to the electrode terminal of the semiconductor element S via the solder bump B1 is formed at the center of the upper surface of the insulating substrate 10, and an external electric circuit board is formed on the lower surface of the insulating substrate 10. External connection pads 40 that are electrically connected to the wiring conductors via solder balls (not shown) are formed. The semiconductor element connection pads 30 and the external connection pads 40 are formed of wiring conductors formed on the conductor layers 21, 22, 23, 24, 25, 26, 27, and 28 and the insulating layers 11, 12, 13, 14, 15 , 16 and 17 are electrically connected to each other through through conductors 51, 52, 53, 54, 55, 56 and 57, respectively. Further, a solder resist layer 61 having an opening exposing the central portion of the semiconductor element connection pad 30 is deposited on the surfaces of the uppermost insulating layer 11 and the conductor layer 21, and the lowermost insulating layer 17 and the conductor are exposed. A solder resist layer 62 having an opening exposing the central portion of the external connection pad 40 is deposited on the surface of the layer 28.

  The insulating layer 14 is a member that becomes a core substrate of the wiring substrate 100, and is formed by impregnating a glass fabric in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as epoxy resin or bismaleimide triazine resin. It has a plurality of through holes 14a having a diameter of about 0.1 to 0.3 mm from the upper surface to the lower surface. The conductor layers 24 and 25 are attached to the upper and lower surfaces, and the through conductor 54 is attached to the inner surface of the through hole 14a. The through hole 14a to which the through conductor 54 is attached is filled with resin.

  Such an insulating layer 14 is manufactured by thermally curing an insulating sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling through holes 14a from the upper surface to the lower surface. The conductor layers 24 and 25 on the upper and lower surfaces of the insulating layer 14 have a copper foil having a thickness of about 3 to 50 μm adhered to the entire upper and lower surfaces of the insulating sheet for the insulating layer 14, and the copper foil is cured on the sheet. A predetermined pattern is formed by etching later. The through conductor 54 on the inner surface of the through hole 14a is formed by depositing a copper plating film having a thickness of about 3 to 50 μm on the inner surface of the through hole 14a by an electroless plating method and an electrolytic plating method. In order to fill the inside of the through hole 14a with a resin, an uncured pasty thermosetting resin is filled into the through hole 14a in which the through conductors 54 are formed by a screen printing method, and then the filled resin is filled. A method of thermally curing is adopted.

  Each of the insulating layers 11, 12, 13, 15, 16, and 17 laminated on the upper and lower surfaces of the insulating layer 14 is a build-up insulating layer, and an inorganic insulator such as a silicon oxide powder on a thermosetting resin such as an epoxy resin. It consists of an insulating material in which about 30 to 70% by mass of filler is dispersed. The insulating layers 11, 12, 13, 15, 16, and 17 each have a thickness of about 20 to 60 μm, and a plurality of via holes 11 a, 12 a, 13 a, 15 a, and a diameter of about 30 to 100 μm from the upper surface to the lower surface of each layer. 16a, 17a. The via holes 11a, 12a, 13a, 15a, 16a, and 17a are filled with through conductors 51, 52, 53, 55, 56, and 57, respectively, and these through conductors 51, 52, 53, 55, 56, and By electrically connecting predetermined wiring patterns of the conductor layers 21, 22, 23, 24, 25, 26, 27, 28 through 57, high-density wiring can be formed three-dimensionally. Each of such insulating layers 11, 12, 13, 15, 16, and 17 is formed by attaching an insulating film made of an uncured thermosetting resin having a thickness of about 20 to 60 μm to the upper and lower surfaces of the insulating layer 14. And the via holes 13a and 15a are drilled by laser processing, and the next insulating layers 12, 11 and 16, 17 are sequentially stacked thereon in the same manner. In addition, in the conductor layers 21, 22, 23, 26, 27, 28 and the via holes 11a, 12a, 13a, 15a, 16a, 17a deposited on the surfaces of the insulating layers 11, 12, 13, 15, 16, 17 The through conductors 51, 52, 53, 55, 56, and 57 filled in each of the insulating layers 11, 12, 13, 15, 16, and 17 are formed each time the insulating layers 11, 12, 13, 15, 16, and 17 are formed. , 17 and a copper plating film having a thickness of about 5 to 50 μm on the surface of via holes 11a, 12a, 13a, 15a, 16a, and 17a by applying a predetermined pattern by a pattern forming method such as a known semi-additive method. It is formed.

  In addition, the solder resist layers 61 and 62 are formed by adding a filler such as silica or talc to a thermosetting resin such as an acrylic-modified epoxy resin. If the solder resist layer 61 is on the upper surface side, the semiconductor element connection pad 30 is used. In addition, the solder resist layer 62 on the lower surface side has an opening for exposing the central portion of the external connection pad 40. The solder resist layers 61 and 62 have a thickness of about 10 to 50 μm, and the uncured resin paste for the solder resist layers 61 and 62 having photosensitivity is insulated by adopting a roll coater method or a screen printing method. After coating on the layers 11 and 17 and drying them, exposure and development processes are performed to form openings that expose the central portions of the semiconductor element connection pads 30 and the external connection pads 40, and then this is heated. It is formed by curing.

  Here, an example of a pair transmission line in the wiring board of the present invention will be described. 2 (a) to 2 (d) and FIGS. 3 (e) to 3 (h) show parts of the conductor layers 21, 22, 23, 24, 25, 26, 27, and 28 and the through conductors in the wiring board 100 described above. It is the top view which extracted and showed only a part of 51,52,53,54,55,56,57.

  FIG. 2A shows the conductor layer 21. The conductor layer 21 includes a pair 31 and 32 of semiconductor element connection pads 30 connected to the pair transmission path, and a power supply layer 71 connected to the first power supply potential. The semiconductor element connection pads 31 and 32 are circular with a diameter of about 100 to 200 μm, and are adjacent to each other with a pitch of about 110 to 250 μm. The first power supply layer 71 extends in a solid shape from the vicinity of the central portion of the insulating substrate 10 to the vicinity of the outer peripheral edge.

  FIG. 2B shows the conductor layer 22 and the through conductor 51 connected thereon. The conductor layer 22 includes strip-shaped wiring conductor pairs 81 and 82 extending from below the semiconductor element connection pads 31 and 32 to above the pairs 41 and 42 of external connection pads 40 described later, and the power supply layer 71 and Similarly, a power supply layer 72 connected to the first power supply potential is included. A pair of strip-like wiring conductors 81 and 82 extend in parallel at a predetermined interval except for their end portions, one end of which is connected to the semiconductor element connection pads 31 and 32 by a through conductor 51 and the other end. The portion extends to a position corresponding to the central portion of the external connection pads 41 and 42. Further, the power supply layer 72 is arranged in a solid shape so as to surround these strip-like wiring conductor pairs 81 and 82 at a predetermined interval, and has an oval shape at a position corresponding to the external connection pad pairs 41 and 42 described later. The opening 72a is provided. The power supply layer 72 is connected to the upper power supply layer 71 by the through conductor 51 in the vicinity of the strip-shaped wiring conductors 81 and 82 and the opening 72a.

  FIG. 2C shows the conductor layer 23 and the through conductor 52 connected thereon. The conductor layer 23 has a power supply layer 73 connected to a second power supply potential different from the first power supply potential and a power supply pattern 91 connected to the first power supply potential. The power supply layer 73 extends from the center of the insulating substrate 10 in a solid shape. The power supply pattern 91 is disposed on the outer peripheral portion of the insulating substrate 10 independently from the power supply layer 73, and has an oval opening 91 a at a position corresponding to the pair of external connection pads 41 and 42. The power supply pattern 91 is connected to the upper power supply layer 72 by the through conductor 52 in the vicinity of the opening 91a. Further, in the opening 91a, the through conductor 52 is connected to the other ends of the above-described strip-like wiring conductors 81 and 82.

  FIG. 2D shows the conductor layer 24 and the through conductor 53 connected thereon. The conductor layer 24 has a power supply layer 74 connected to the same second power supply potential as the power supply layer 73 described above and a power supply pattern 92 connected to the first power supply potential. The power supply layer 74 extends from the center of the insulating substrate 10 in a solid shape. The power supply pattern 92 is disposed on the outer peripheral portion of the insulating substrate 10 independently from the power supply layer 74, and has an oval opening 92 a at a position corresponding to the pair of external connection pads 41 and 42. The power supply pattern 92 is connected to the upper power supply pattern 91 by the through conductor 53 in the vicinity of the opening 92a. Further, the through conductor 53 is connected to the upper through conductor 52 in the opening 92a.

  FIG. 3E shows the conductor layer 25 and the through conductor 54 connected thereon. The conductor layer 25 has a power supply layer 75 connected to a third power supply potential different from the first and second power supply potentials, and a power supply pattern 93 connected to the first power supply potential. The power supply layer 75 extends in a solid shape from the central portion of the insulating substrate 10. The power supply pattern 93 is disposed on the outer peripheral portion of the insulating substrate 10 independently from the power supply layer 75, and has an oval opening 93 a at a position corresponding to the pair of external connection pads 41 and 42. The power supply pattern 93 is connected to the upper power supply pattern 92 by the through conductor 54 in the vicinity of the opening 93a. Further, the through conductor 54 is connected to the upper through conductor 53 in the opening 93a.

  FIG. 3F shows the conductor layer 26 and the through conductor 55 connected thereon. The conductor layer 26 has a power supply layer 76 connected to the same third power supply potential as the power supply layer 75 described above and a power supply pattern 94 connected to the first power supply potential. The power supply layer 76 extends from the central portion of the insulating substrate 10 in a solid shape. The power supply pattern 94 is arranged on the outer peripheral portion of the insulating substrate 10 independently from the power supply layer 76, and has an oval opening 94 a at a position corresponding to the pair of external connection pads 41 and 42. The power supply pattern 94 is connected to the upper power supply pattern 93 by a through conductor 55 in the vicinity of the opening 94a. Further, the through conductor 55 is connected to the upper through conductor 54 in the opening 94a.

  FIG. 3G shows the conductor layer 27 and the through conductor 56 connected thereon. The conductor layer 27 has a power supply layer 77 connected to the same third power supply potential as the power supply layers 75 and 76 described above, and a power supply pattern 95 connected to the first power supply potential. The power supply layer 77 extends from the central portion of the insulating substrate 10 in a solid shape. The power supply pattern 95 is disposed on the outer peripheral portion of the insulating substrate 10 independently from the power supply layer 77, and has an oval opening 95 a at a position corresponding to the pair of external connection pads 41 and 42. The power supply pattern 95 is connected to the upper power supply pattern 94 by the through conductor 56 in the vicinity of the opening 95a. Further, the through conductor 56 is connected to the upper through conductor 55 in the opening 95a.

  FIG. 3 (h) shows the conductor layer 28 and the through conductor 57 connected thereon. The conductor layer 28 has the pair 41, 42 of the external connection pads 40 connected to the pair of strip-like wiring conductors 81, 82 described above, and the power supply layer 78 connected to the second power supply potential described above. A power supply pattern 96 connected to the first power supply potential. The external connection pads 41 and 42 are circular with a diameter of about 300 to 500 μm, and are adjacent to each other with a pitch of about 500 to 1000 μm. The power supply layer 78 extends from the center of the insulating substrate 10 in a solid shape. The power supply pattern 96 is disposed on the outer peripheral portion of the insulating substrate 10 independently from the power supply layer 78, and has an oval opening 96 a at a position corresponding to the pair of external connection pads 41 and 42. The semiconductor element connection pads 41 and 42 are connected to the upper through-conductor 56 by the through-conductor 57 in the opening 96a. The power supply pattern 96 is connected to the upper power supply pattern 95 by a through conductor 57 in the vicinity of the opening 96a.

  With the configuration described above, a pair transmission path in which the pair 31 and 32 of semiconductor element connection pads and the pair 41 and 42 of external connection pads are connected via the pair of strip-like wiring conductors 81 and 82 and the through conductors 51 to 57 is provided. Is formed. In the present invention, as described above, for example, in the conductor layers 23 to 28, the power supply patterns 91 to 96 surrounding the openings 91a to 96a are provided independently from the surrounding power supply layers 73 to 78, and The power supply patterns 91 to 96 are connected to the same first power supply potential by through conductors 52 to 57 in the vicinity of the openings 91a to 96a. Then, through conductors 52 to 57 connecting the strip-like wiring conductor pairs 81 and 82 and the external connection pad pairs 41 and 42 are connected to the power supply patterns 91 to 96 connected to the first power supply potential and these. Since it is surrounded by the through conductors 52 to 57, matching of the characteristic impedance of the pair transmission line is facilitated. As a result, even if the signal propagating through the pair transmission line has a high frequency exceeding 10 GHz, for example, the signal reflection loss In addition, it is possible to provide a wiring board that has a small insertion loss and can propagate signals normally.

DESCRIPTION OF SYMBOLS 10 ... Insulating substrate 11, 12, 13, 14, 15, 16, 17 ... Insulating layer 41, 42 ... Pair of external connection pads 51, 52, 53, 54, 55, 56, 57 Penetration conductor 71,72,73,74,75,76,77,78 ... power supply layer 91, 92, 93, 94, 95, 96 ... power supply pattern 91a, 92a, 93a, 94a, 95a, 96a ... Opening part 100 ... Wiring board

Claims (1)

  An insulating substrate formed by laminating a plurality of insulating layers, a pair of external connection pads for a pair transmission path formed on the lower surface of the insulating substrate, and the pair of external connection pads disposed between the insulating layers. A plurality of conductor layers having openings formed at positions corresponding to the through holes, and through-conductors that are electrically connected to the pair of external connection pads at positions corresponding to the openings and pass through the plurality of insulating layers. The conductor layer has a power pattern surrounding the opening independently of the surrounding conductor layer, and the upper and lower power patterns are connected to the same power supply potential by through conductors. A wiring board characterized by.

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