WO2015190236A1 - Chip module and information processing device - Google Patents

Chip module and information processing device Download PDF

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Publication number
WO2015190236A1
WO2015190236A1 PCT/JP2015/064270 JP2015064270W WO2015190236A1 WO 2015190236 A1 WO2015190236 A1 WO 2015190236A1 JP 2015064270 W JP2015064270 W JP 2015064270W WO 2015190236 A1 WO2015190236 A1 WO 2015190236A1
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WO
WIPO (PCT)
Prior art keywords
interposer
chip module
tgv
glass
resonance
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PCT/JP2015/064270
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French (fr)
Japanese (ja)
Inventor
仁博 遠山
植松　裕
智子 依田
大坂　英樹
敬 飯田
Original Assignee
株式会社日立製作所
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Publication of WO2015190236A1 publication Critical patent/WO2015190236A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to a chip module and information processing equipment.
  • the present invention claims the priority of Japanese Patent Application No. 2014-119565 filed on June 10, 2014, and for the designated countries where weaving by reference is allowed, the contents described in the application are as follows: Is incorporated into this application by reference.
  • Patent Document 1 (U.S. Pat. No. 2013/0119555) states that “a small electronic package, wherein a plurality of through vias have a wall in a glass interposer having a top, and a stress relaxation barrier is formed on the top of the glass interposer.
  • the plurality of metallization seed layers being at least part of the stress relaxation barrier, the conductor being at least part of the metallization seed layer and forming a plurality of metallized through package substrate vias; Through vias, and at least some of the through vias are filled with the stress relaxation layer or metallization seed layer (A microelectronic package comprising: a plurality of through vias having walls in a glass interposer having a top portion; a stress relief barrier on at least a portion of the top portion of the glass interposer; a metallization seed layer on at least a portion of the stress relief layer; and a conductor on at least a port of the portionofa the through vias forming a plurality of metalized through package vias, wherein at least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.
  • a glass interposer In a glass interposer, conductor layers are arranged on both sides of a glass core, and the upper and lower sides of the glass core are electrically connected by TGV (Trough Glass Via) penetrating the glass core. Because the loss of the glass core is small, the glass core part sandwiched between both sides works as a cavity resonator, and the electromagnetic field caused by the signal passing through the TGV and the current of the power supply / GND leaks into the core. Is excited, and there is a problem that signal quality and power supply characteristics deteriorate.
  • the present invention has been made in view of such circumstances, and an object thereof is to provide a technique for improving signal quality deterioration and power supply characteristic deterioration due to resonance generated in a glass interposer.
  • the present application includes a plurality of means for solving the above-described problems.
  • the chip module includes a semiconductor chip and an interposer, and the interposer has an electrical resistance value greater than about 1 ⁇ . Has through vias.
  • FIG. 1 is an example of a longitudinal sectional view of a chip module of Example 1.
  • FIG. It is an example of the cross-sectional view of a chip module.
  • the model for eigenmode analysis is shown. It is a comparison result of Q value in the model.
  • the relationship between the electrical resistance value of TGV and the Q value of the primary mode is shown.
  • the relationship between the electrical resistance value of TGV and the frequency of the primary mode is shown. It is a figure explaining an example of TGV formation.
  • FIG. 10 is an example of a vertical cross-sectional view of a chip module of Example 7. The relationship between the via resistance value of the ceramic interposer and the Q value of the primary mode is shown. The relationship between the via resistance value of a ceramic interposer and the frequency of a primary mode is shown.
  • FIG. 10 is an example of a longitudinal sectional view of a chip module according to an eighth embodiment. It is an example of the longitudinal cross-sectional view of the chip module of Example 9.
  • FIG. 1 is an example of a longitudinal sectional view of the chip module 100A of the first embodiment
  • FIG. 2 is an example of a transverse sectional view of the chip module 100A. More specifically, FIG. 2 is an example of a cross-sectional view taken along line AA in FIG. 1, and FIG. 1 is an example of a cross-sectional view taken along line BB in FIG.
  • the chip module includes a package substrate and a glass interposer, and one or more semiconductor chips are mounted on the glass interposer.
  • the semiconductor chip is, for example, LSI (Large Scale Integration) or IC (Integrated Circuit), but is not limited thereto.
  • the package substrate is not particularly limited as long as it can be electrically connected to the glass interposer via the electrode portion.
  • the package substrate is made of ceramic, but is not limited to this, and any other material such as an organic resin may be adopted.
  • the glass interposer includes a glass core formed of a glass-based material, has conductive planes on the upper and lower surfaces of the glass core, and includes at least one through via that connects the conductive planes. I just need it. Examples of the glass material include, but are not limited to, glass ceramics, borosilicate glass, quartz glass, and high silicate glass.
  • the chip module 100A is an example of a module in which an ASIC (Application Specific Integrated Circuit) and an optical IC are mounted on the same package substrate, but is not limited thereto.
  • the chip module 100A may be mounted with any semiconductor chip such as an IC other than an ASIC or an optical IC, or an LSI.
  • the ASIC may be, for example, an FPGA (Field-Programmable Gate Array), a CPU (Central Processing Unit), or a GPU (Graphics Processing Unit), and the optical IC may be, for example, a signal conditioner (electric signal relay LSI).
  • the chip module 100 ⁇ / b> A includes a glass interposer 5 and a package substrate 3. A glass interposer 5 is mounted on the upper surface of the package substrate 3.
  • Package board 3 includes via hole 9, conductor layer 10, and the like.
  • BGA All Grid Array
  • balls 8 are formed on the lower surface of the package substrate 3.
  • Each of the bumps 4-2 and 4-3 is formed on the upper surface of the glass interposer 5 (the surface not connected to the package substrate 3).
  • the glass interposer 5 and the ASIC 1 and the optical IC 2 are electrically connected by the bumps 4-2 and 4-3, respectively.
  • Bumps 4-1 are formed on the lower surface of glass interposer 5 (the surface connected to package substrate 3).
  • the package substrate 3 and the glass interposer 5 are electrically connected by bumps 4-1.
  • the glass interposer 5 includes at least a glass core 30 and a conductor layer 11.
  • the conductor layer 11 is disposed on each of the upper surface and the upper surface of the glass core 30.
  • Each of TGV6 and TGV7 is formed in the glass core 30.
  • TGV6 is formed by copper plating inside the through hole. Electrical connection between the upper and lower sides of the glass core 30 is established by the TGV 6. As a result, a high-density signal wiring between the ASIC 1 and the optical IC 2 is formed.
  • the treatment applied to the inside of the TGV 6 is not limited to copper plating, and any material or technique can be used.
  • the conductor layer 11 includes a wide plane to serve as a return plane for signal wiring. Therefore, the structure composed of the conductor layer 11 and the glass core 30 functions like a cavity resonator, and resonance noise is excited by a signal passing through the TGV 6 and a current change in the power supply / ground.
  • a broken line 20 in FIG. 1 schematically shows the electric field strength of resonance noise. As shown in the figure, the place connected by TGV6 is a node of resonance voltage.
  • TGV7 is formed by filling a through hole with a predetermined material.
  • the planes of the upper and lower conductor layers 11 of the glass core 30 are electrically connected by the TGV 7.
  • both ends of the TGV 7 are effective when placed at positions where the electric field strength is large and the antinodes of the noise voltage are present, but the present invention is not limited to this.
  • the position where the antinode of resonance is an intermediate point between the nodes, and the end of the glass core 30 also becomes the antinode of resonance. Therefore, as shown in FIG. 2, it is effective that the position where the TGV 7 is disposed is at least one of the corners of the glass core 30, along the outer peripheral edge of the glass core 30, and between the TGVs 6.
  • TGV7 is arranged between TGV6, it is preferable that the intermediate point between TGV6 or near the intermediate point.
  • the electrical resistance value of TGV7 needs to be higher than about 1 ⁇ in order to give a sufficient resonance damping effect.
  • an electric resistance value higher than about 1 ⁇ is realized by a predetermined material filled in the through hole.
  • the planes connected by the TGV 7 must have the same potential in terms of DC (Direct Current).
  • DC Direct Current
  • the case of the same potential in terms of DC is, for example, the case where both are ground planes or both are power supply planes.
  • the electrical resistance value of through vias such as TGV6 due to copper plating is almost much lower than about 1 ⁇ .
  • the electric resistance value is 10 m ⁇ or less. Therefore, TGV7 can be said to be a through via having a higher electrical resistance value than TGV6.
  • the numerical value such as “1 ⁇ ” here includes not only this number but also an error range caused by, for example, a model error or a measurement error.
  • FIG. 3 shows a model for eigenmode analysis.
  • the model 300 is obtained by bonding copper planes 50-1 and 50-2 on the upper and lower surfaces of the glass core 30 having a thickness of about 30 mm square and a thickness of about 100 ⁇ m.
  • the position that becomes the antinode of resonance is, for example, the positions 51 of the four corners of the plane.
  • the Q value representing the stability of resonance was obtained under each of the following three conditions 1 to 3. The lower the Q value, the faster the resonance attenuation.
  • Condition 1 Nothing is placed at position 51
  • Condition 2 TGV by copper plating is placed at position 51 and upper and lower copper planes 50-1 and 50-2 are electrically connected
  • Condition 3 From position 1 at about 1 ⁇ The upper and lower copper planes 50-1 and 50-2 are electrically connected by arranging a TGV having a higher electrical resistance value. Each TGV has a diameter of about 20 ⁇ m and a TGV having an electrical resistance value higher than about 1 ⁇ . The actual electric resistance value was set to 5 ⁇ per one.
  • FIG. 4 shows a comparison result of Q values in the model 300.
  • the graph 400 shows the Q value for each resonance from the primary mode to the tertiary mode for each of the above conditions 1 to 3.
  • the bar 401 in the first mode indicates the Q value in the condition 1
  • the bar 402 indicates the Q value in the condition 2
  • the bar 403 indicates the Q value in the condition 3.
  • the Q value is 1/6 or less.
  • the Q value reduction effect is recognized even under condition 2 (bar 402), it can be seen that the effect is small compared to condition 3 (bar 403).
  • FIG. 5 shows the relationship between the electrical resistance value of TGV and the Q value of the primary mode.
  • the horizontal axis of the graph 500 is the electrical resistance value of TGV, and the vertical axis is the Q value.
  • the Q value takes the lowest value in the vicinity of the electric resistance value of about 1 ⁇ to about 10 ⁇ .
  • the electrical resistance of the TGV is low, the resonance attenuation effect is small because the amount of resonance converted into thermal energy in the TGV is small.
  • the electrical resistance of the TGV is too high, no current flows through the TGV, so the attenuation effect is small.
  • the electrical resistance of TGV is extremely high (for example, about 1000 ⁇ or more), the resonance damping effect cannot be obtained, and it is more desirable to set the electrical resistance to about 100 ⁇ or less.
  • FIG. 6 shows the relationship between the electrical resistance value of TGV and the frequency of the primary mode.
  • the horizontal axis of the graph 600 is the electrical resistance value of TGV, and the vertical axis is the frequency.
  • the frequency is different between the low resistance side and the high resistance side, and transitions between about 1 ⁇ and about 10 ⁇ .
  • the frequency value on the high resistance side matches the frequency when TGV is not inserted, and the frequency value on the low resistance side is equal to the frequency when normal TGV is inserted. This indicates that if a through via of about 1 ⁇ or less is inserted, the position of the resonance antinode / node changes, while if a TGV greater than about 1 ⁇ to about 10 ⁇ is inserted, the resonance antinode -This means that the position of the clause does not change.
  • FIG. 7 is a diagram for explaining an example of TGV formation. In the figure, only the formation with respect to the glass core 30 will be described for simplification.
  • FIG. 7A shows only the glass core 30.
  • FIG. 7B shows an example in which a through hole 31-1 is provided in the glass core 30 with a laser or the like. Here, the through hole 31-1 is provided only at a position where the TGV 7 is formed.
  • FIG. 7C shows an example in which the through hole 31-1 is filled with a predetermined material. In this way, the TGV 7 having an electrical resistance value greater than 1 ⁇ is formed.
  • FIG. 7D shows an example in which a through hole 31-2 is provided in the glass core 30 with a laser or the like. Here, a through hole 31-2 is provided at a position where the TGV 6 is formed.
  • FIG. 7A shows only the glass core 30.
  • FIG. 7B shows an example in which a through hole 31-1 is provided in the glass core 30 with a laser or the like. Here, the through hole 31-1 is provided only at a position where the TGV 7 is formed.
  • FIG. 7C shows an example in which the through hole 31-1 is filled with a predetermined
  • FIG 7E shows an example in which copper plating is applied to the glass core 30 in which the through hole 31-2 is formed. Thereby, TGV6 is formed.
  • the conductor layer 11 can be formed simultaneously with the formation of the TGV 6 by this copper plating.
  • TGV formation is not limited to the above.
  • a through hole may be formed in a position where the TGV 6 or TGV 7 is provided in one process, and when filling the through hole, the through hole forming the TGV 6 may be masked.
  • FIG. 8 is an example of a longitudinal sectional view of the chip module 100B of the second embodiment
  • FIG. 9 is an example of a transverse sectional view of the chip module 100B. More specifically, FIG. 9 is an example of a cross-sectional view taken along line CC in FIG. 8, and FIG. 8 is an example of a cross-sectional view taken along line DD in FIG.
  • the difference between the first embodiment and the second embodiment is that a TGV composed of a conductive thin film and a resist is used in place of the TGV in which a through hole is filled with a predetermined material in order to realize a through via having an electric resistance larger than 1 ⁇ . It is a point to use. Since the electric resistance value of the conductor thin film is high, the same resonance attenuation effect as that in the above embodiment can be obtained.
  • the electrical resistance value of TGV13 is preferably greater than about 1 ⁇ as described above. Further, as described above, it is most effective to arrange the TGV 13 at the antinode of resonance as described above.
  • FIG. 10 is a diagram for explaining an example of TGV formation. In the figure, only the formation with respect to the glass core 30 will be described for simplification.
  • FIG. 10A shows only the glass core 30.
  • FIG. 10B is an example in which a through hole 31 is provided in the glass core 30 with a laser or the like. Here, the through hole 31 is provided at a position where the TGV 6 or TGV 13 is formed.
  • FIG. 10C shows an example in which the conductive thin film 32 is formed inside the through hole 31 by, for example, electroless plating. The conductor thin film 32 is formed with a thickness of about 1 ⁇ m or less using a conductor having a high resistivity such as a P—Ni alloy.
  • FIG. 10D shows an example in which a resist 33 is filled in the through hole 31 in which the conductive thin film 32 is formed at the position where the TGV 13 is formed.
  • TGV13 is formed.
  • photolithography Photolithography
  • FIG. 10E shows an example in which copper plating is applied to the glass core 30 on which the TGV 13 is formed.
  • copper plating is formed inside the through-hole 31 in which the conductive thin film 32 is formed but the resist 33 is not filled, and the TGV 6 and the conductor layer 11 are formed.
  • the TGV drilling process can be performed once without including the steps such as the mask described above.
  • the hollow portion of the TGV 13 is filled with a resist, but it may be left hollow.
  • the strength of the glass core 30 increases when the hollow portion is filled with a resist or the like.
  • FIG. 11 is an example of a longitudinal sectional view of the chip module 100C of the third embodiment.
  • the chip module 100C is provided with a capacitor 14 in the vicinity of the TGV 7, and the upper and lower planes of the glass core 30 are electrically connected through both the capacitor 14 and the TGV 7.
  • the upper and lower planes show an example of the conductor layer 11 in FIG. 11, the upper and lower planes are not limited to this.
  • FIG. 12 is an example of a circuit diagram showing a connection relationship.
  • the capacitor 14 is connected in series with the TGV 7 connected to the lower plane 43, and the tip is connected to the upper plane 42. That is, the two planes are electrically connected via the TGV 7 and the capacitor 14 connected in series.
  • the capacitor 14 is preferably a small size because of the mounting space.
  • An example of such a capacitor is a thin film capacitor, but is not limited thereto.
  • two planes may be connected in series via TGV13 and a capacitor. That is, it is only necessary that two planes can be connected in series via a TGV and a capacitor having an electrical resistance value greater than about 1 ⁇ .
  • FIG. 13 is an example of a longitudinal sectional view of the glass interposer of Example 4.
  • the chip module 100D of the present embodiment is different from the second embodiment in the range in which the conductor thin film 34 is provided.
  • the conductor thin film 34 is formed not only on the inside of the through hole but also on each of the upper and lower surfaces (for example, the surface 1301 and the surface 1302) of the glass core 30, and the copper plating 35 is applied thereon. A conductor layer is formed. Except for this point, the structure of the chip module 100D is the same as that of the chip module 100B.
  • the resonance noise attenuation effect can be obtained by the TGV having an electric resistance larger than about 1 ⁇ as in the above embodiment. Moreover, since the resonance noise current excited in the glass core is concentrated on the glass core 30 side of the upper and lower planes due to the skin effect, the conductive thin film 34 provided on the upper and lower surfaces of the glass core 30 also causes resonance noise. A damping effect is obtained. [Example 5]
  • FIG. 14 is an example of a longitudinal sectional view of the chip module 100E of Example 5, and FIG. 15 is an example of a transverse sectional view of the chip module 100E. More specifically, FIG. 15 is an example of a cross-sectional view taken along line EE in FIG. 14, and FIG. 14 is an example of a cross-sectional view taken along line FF in FIG.
  • a Si interposer 60 is further mounted on the package substrate 3 and the ASIC 1 is mounted across the Si interposer 60 and the glass interposer 5.
  • each glass interposer 5 has one IC 2 mounted thereon, and one chip module 100E includes a total of four optical ICs 2-1 to 2-4.
  • the Si interposer 60 is disposed at the center of the ceramic package substrate 3 or in the vicinity thereof, and the glass interposer 5 is disposed at least partially around the periphery. At least one ASIC 1 is disposed on the Si interposer 60. The ASIC 1 is disposed so as to straddle both the glass interposers 5-1 to 5-4 and the Si interposer 60. That is, the ASIC 1 is electrically connected to the package substrate 3 via each of the glass interposer 5 and the Si interposer 60.
  • the occupation range of the Si interposer 60 when the chip module 100E is viewed from above is included in the occupation range of the ASIC 1. Further, when the chip module 100E is viewed from above, the occupation range of the Si interposer 60 and the ASIC 1 is arranged so as to overlap a part of the occupation range of each of the four glass interposers 5-1 to 5-4. Further, when the chip module 100E is viewed from above, the occupation range of the Si interposer 60 and the ASIC 1 is arranged so as not to overlap with the occupation range of each IC 2 mounted on each of the glass interposers 5.
  • the ASIC 1 is provided with an electrode portion for high-speed signals for connecting to the glass interposer 5.
  • this electrode part is not limited, it is a pin, a bump, a lead, etc. (for example, bump 1401), for example, and is provided along the outer periphery of ASIC1 in this case.
  • the high-speed signal wiring is connected to each of the optical ICs 2-1 to 2-4 via each signal wiring (not shown) of the glass interposers 5-1 to 5-4. As described above, the high-speed signal can be transmitted through the low-loss glass interposer to suppress the deterioration of the signal quality.
  • the ASIC is provided with electrodes for low-speed signals and power supply / ground of the core circuit for connection with the Si interposer 60.
  • this electrode part is not limited, it is a pin, a bump, a lead, etc. (for example, bump 1402), for example, and is provided in the center vicinity of ASIC1 in this case.
  • This wiring is connected to the package substrate 3 through the through via 61 of the Si interposer 60. As described above, since power is supplied to the power source / ground of the core circuit having a large current through the Si interposer having a large loss, the problem of resonance noise can be made difficult to occur.
  • each of the glass interposers 5 includes any one of the configurations of the first to fourth embodiments described above.
  • FIG. 14 shows an example including TGV7 as in the first embodiment, but TGV13 may be used. In any of TGV7 and TGV13, the arrangement position is the same as in the above embodiment.
  • each glass interposer 5 may include a configuration of a different example among the above-described first to fourth examples. Thereby, as described above, the resonance on the glass interposer side can be attenuated.
  • FIG. 16 is a side view of the substrate portion of the information processing apparatus in which the chip module 100 is incorporated.
  • the information processing equipment here refers to a device that includes an arithmetic device such as an IC or LSI and that can execute a desired arithmetic operation.
  • the information processing apparatus 200 includes a plurality of chip modules 100, a plurality of motherboards 71, a plurality of connectors 72, a backplane board 73, an optical fiber 74, and the like. These numbers may be singular or plural and are not limited to those shown. However, efficient information processing can be performed by performing processing simultaneously by the plurality of chip modules 100 and the motherboard 71.
  • any one or a plurality of chip modules 100-1 to 100-3 of the first to fifth embodiments are mounted on each of the mother boards 71-1 to 71-3.
  • FIG. 16 shows an example in which the chip module 100E is mounted.
  • Each of the mother boards 71-1 to 71-3 is electrically connected to the backplane board 73 by connectors 72-1 to 72-3.
  • Optical fibers 74-1 and 74-2 are connected to the optical ICs mounted on each of the chip modules 100-1 to 100-3, and the chip modules 100-1 to 100-3 communicate with each other by optical signals. Is possible.
  • the chip modules 100-1 to 100-3 can have a broadband signal transmission capability by being mounted as described above.
  • high-speed optical signal transmission can be performed between the chip modules 100-1 to 100-3. Thereby, the information processing capability can be improved.
  • FIG. 17 is an example of a vertical cross-sectional view of the chip module 100F of the seventh embodiment.
  • the glass interposer is used as an object.
  • a resonance problem may also occur in a module using a substrate such as a low-loss ceramic.
  • via holes having high resistance are arranged in the ceramic interposer to suppress resonance between planes and avoid characteristic deterioration.
  • the ASIC 1 and the optical IC 2 are arranged on the upper surface of the ceramic interposer 300.
  • the ASIC 1 and the optical IC 2 are connected to the surface conductor layer 302 of the ceramic interposer 300 by bumps 4-2 and 4-3, respectively.
  • the ceramic interposer 300 is electrically connected to a printed circuit board or the like by BGA balls 8 arranged on the lower surface.
  • the ceramic interposer 300 has a structure in which ceramic substrates 305-1 to 305-5 and a conductor layer 302 are laminated. A wiring pattern and a power / GND plane are formed on the conductor layer 302. In order to electrically connect the upper and lower conductor layers 302 of the ceramic substrate 305, a via hole 303 having a low electrical resistance is disposed so as to penetrate the ceramic substrate 305.
  • a high-resistance via hole 304 is disposed at the antinode of the resonance voltage.
  • the via holes 304 are effective if they are arranged at the corners of the ceramic substrates 305-1 to 305-5 or along the outer periphery of the ceramic substrate.
  • the high-resistance via hole 304 needs to be 1 ⁇ or more as in the case of the glass interposer.
  • a model was prepared in which a GND plane was formed of silver on the upper and lower sides of a ceramic substrate having a size of 30 mm square and a thickness of 80 ⁇ m. And about the structure at the time of arrange
  • FIG. 18 shows the relationship between the via resistance value of the ceramic interposer and the Q value of the primary mode.
  • the horizontal axis of the graph 501 is the electrical resistance value of the via hole 304, and the vertical axis is the Q value of the primary mode.
  • the Q value takes the lowest value in the vicinity of 1 ⁇ to 10 ⁇ as in the case of the glass interposer.
  • FIG. 19 shows the relationship between the via resistance value of the ceramic interposer and the frequency of the primary mode.
  • the horizontal axis of the graph 601 is the electrical resistance value of the via hole 304, and the vertical axis is the frequency of the primary mode.
  • the resonance frequency changes between about 1 ⁇ and 10 ⁇ as in the case of the glass interposer. This indicates that when a via hole of 1 ⁇ or less is inserted, the position of the resonance antinode / node changes, whereas when a via hole larger than about 1 ⁇ to about 10 ⁇ is inserted, the resonance antinode -This means that the position of the clause does not change.
  • Example 7 an example in which ceramic is used as the substrate material is shown, but a low-loss resin base material or the like may be used.
  • FIG. 20 is an example of a longitudinal sectional view of the chip module 100G of the eighth embodiment.
  • the capacitor 306 is disposed on the upper surface of the ceramic interposer 300 with respect to the chip module 100F of the seventh embodiment.
  • a high resistance via hole 304 and a capacitor 306 are connected in series, and the upper and lower planes are connected via the capacitor 306. Connect.
  • the connection is made through the low resistance via hole 303.
  • the capacitor 306 is disposed on the upper surface of the ceramic interposer 300, but may be disposed on the lower surface. Further, a capacitor formed in the ceramic interposer 300 may be used as the capacitor.
  • FIG. 21 is an example of a vertical cross-sectional view of the chip module 100H of the ninth embodiment.
  • the chip module 100H according to the ninth embodiment has a buildup layer 307 capable of forming a narrow pitch wiring on the upper surface of the ceramic interposer 300 as compared with the chip modules 100F and 100G according to the seventh and eighth embodiments.
  • the build-up layer 307 normally uses a thin film such as polyimide as a dielectric material, but the material is not limited to this.
  • the build-up layer 307 connects the ASIC 1 and the optical IC 2 with a large number of wires by using finer wires than those in the ceramic interposer 300.
  • a capacitor 306 for assisting power supply is disposed as necessary.
  • the capacitor 306 is connected in series with the high resistance via hole 304 for suppressing the resonance of the ceramic substrates 305-1 to 305-5 in the same manner as in the eighth embodiment, and can suppress the resonance between the planes having different potentials.
  • the invention made by the present inventor has been specifically described based on an example.
  • the transmission throughput in the apparatus in order to improve the performance of the apparatus.
  • a transmission distance such as a signal conditioner or an optical module is extended.
  • a relay LSI is used.
  • the required throughput between computing devices and memories is increasing year by year as the computing devices (such as CPUs) become multi-core, and there is a technology for connecting them at high density. is necessary.
  • Another requirement is cost reduction.
  • the core material when glass is used as the core material, there is little deterioration of the signal waveform, so there is little attenuation of noise. Therefore, the planes on both sides of the core material act like a cavity resonator and cause characteristic deterioration. As a result, the power supply and the ground impedance are degraded, and the characteristics of the signal wiring penetrating the core material are degraded.
  • a TGV having an electric resistance value greater than about 1 ⁇ is provided on the glass core.
  • the resonance noise voltage generated in the glass core causes a current to flow when applied to both ends of the TGV.
  • the electromagnetic energy of the resonance noise is converted into heat energy, and the resonance noise can be efficiently attenuated.
  • the current flowing through the TGV is very small, the influence of the addition of the TGV on the position of the resonance antinode or node can be ignored. For this reason, unlike the case of adding a TGV that does not have an electrical resistance value greater than 1 ⁇ , once the resonance noise distribution is calculated, the TGV may be placed at the antinode position of the resonance based on the distribution. This makes it easy to design with countermeasures against resonance noise.

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Abstract

　Provided is a technique for ameliorating degradation of signal quality and degradation of power supply characteristics due to resonance occurring in an interposer. A chip module has a semiconductor chip and an interposer, and the interposer has a through-via having an electrical resistance value in excess of approximately 1Ω.

Description

チップモジュールおよび情報処理機器Chip module and information processing equipment
本発明は、チップモジュールおよび情報処理機器に関する。本発明は２０１４年６月１０日に出願された日本国特許の出願番号２０１４－１１９５６５の優先権を主張し、文献の参照による織り込みが認められる指定国については、その出願に記載された内容は参照により本出願に織り込まれる。 The present invention relates to a chip module and information processing equipment. The present invention claims the priority of Japanese Patent Application No. 2014-119565 filed on June 10, 2014, and for the designated countries where weaving by reference is allowed, the contents described in the application are as follows: Is incorporated into this application by reference.
　特許文献１（米国特許2013/0119555号公報）には、「小型電子パッケージであって、複数のスルービアは、頂部を有するガラスインターポーザに壁を有し、応力緩和バリアは前記ガラスインターポーザの前記頂部の少なくとも一部にあり、メタライゼーションシードレイヤは前記応力緩和バリアの少なくとも一部にあり、導体は前記メタライゼーションシードレイヤの少なくとも一部にあり且つ複数のメタライズされたスルーパッケージ基板ビアを形成する前記複数のスルービアの一部を貫通しており、前記スルービアの少なくとも一部は前記応力緩和層又はメタライゼーションシードレイヤで充填されている（A microelectronic package comprising: a plurality of through vias having walls in a glass interposer having a top portion; a stress relief barrier on at least a portion of the top portion of the glass interposer; a metallization seed layer on at least a portion of the stress relief layer; and a conductor on at least a portion of the metallization seed layer and through at least a portion of the plurality of the through vias forming a plurality of metalized through package vias, wherein at least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.）」と記載されている。 Patent Document 1 (U.S. Pat. No. 2013/0119555) states that “a small electronic package, wherein a plurality of through vias have a wall in a glass interposer having a top, and a stress relaxation barrier is formed on the top of the glass interposer. The plurality of metallization seed layers being at least part of the stress relaxation barrier, the conductor being at least part of the metallization seed layer and forming a plurality of metallized through package substrate vias; Through vias, and at least some of the through vias are filled with the stress relaxation layer or metallization seed layer (A microelectronic package comprising: a plurality of through vias having walls in a glass interposer having a top portion; a stress relief barrier on at least a portion of the top portion of the glass interposer; a metallization seed layer on at least a portion of the stress relief layer; and a conductor on at least a port of the portionofa the through vias forming a plurality of metalized through package vias, wherein at least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.) ".
米国特許2013/0119555号公報US Patent 2013/0119555
　ガラスインターポーザでは、ガラスコアの両面に導体層が配置され、ガラスコアを貫通するTGV（Trough Glass Via）によって、ガラスコアの上下間が電気的に接続される。ガラスコアの損失が小さいため、両面を導体で挟まれたガラスコア部分が空洞共振器として働き、TGVを通過する信号や電源・GNDの電流に起因する電磁界がコア内に漏れだすことで共振が励起され、信号品質の劣化や給電特性が劣化するという課題がある。本発明はこのような事情に鑑みてなされたもので、ガラスインターポーザで発生する共振による信号品質の劣化や給電特性の劣化を改善する技術の提供を目的とする In a glass interposer, conductor layers are arranged on both sides of a glass core, and the upper and lower sides of the glass core are electrically connected by TGV (Trough Glass Via) penetrating the glass core. Because the loss of the glass core is small, the glass core part sandwiched between both sides works as a cavity resonator, and the electromagnetic field caused by the signal passing through the TGV and the current of the power supply / GND leaks into the core. Is excited, and there is a problem that signal quality and power supply characteristics deteriorate. The present invention has been made in view of such circumstances, and an object thereof is to provide a technique for improving signal quality deterioration and power supply characteristic deterioration due to resonance generated in a glass interposer.
　本願は、上記課題を解決するための手段を複数含んでいるが、その一例を挙げるならば、チップモジュールは、半導体チップとインターポーザを有し、前記インターポーザは、電気抵抗値が約１Ωよりも大きいスルービアを有する。 The present application includes a plurality of means for solving the above-described problems. To give an example, the chip module includes a semiconductor chip and an interposer, and the interposer has an electrical resistance value greater than about 1Ω. Has through vias.
　本発明の技術によれば、インターポーザで発生する共振による信号品質の劣化や給電特性の劣化を改善することができる。上記以外の課題、構成および効果等は、以下の実施形態の説明により明らかにされる。 According to the technique of the present invention, it is possible to improve signal quality deterioration and power supply characteristic deterioration due to resonance generated in the interposer. Problems, configurations, effects, and the like other than those described above will be clarified by the following description of embodiments.
実施例１のチップモジュールの縦断面図の例である。1 is an example of a longitudinal sectional view of a chip module of Example 1. FIG. チップモジュールの横断面図の例である。It is an example of the cross-sectional view of a chip module. 固有モード解析対象のモデルを示す。The model for eigenmode analysis is shown. モデルにおけるQ値の比較結果である。It is a comparison result of Q value in the model. TGVの電気抵抗値と１次モードのQ値との関係を示す。The relationship between the electrical resistance value of TGV and the Q value of the primary mode is shown. TGVの電気抵抗値と１次モードの周波数との関係を示す。The relationship between the electrical resistance value of TGV and the frequency of the primary mode is shown. TGV形成の一例を説明する図である。It is a figure explaining an example of TGV formation. 実施例２のチップモジュールの縦断面図の例である。It is an example of the longitudinal cross-sectional view of the chip module of Example 2. チップモジュールの横断面図の例である。It is an example of the cross-sectional view of a chip module. TGV形成の一例を説明する図である。It is a figure explaining an example of TGV formation. 実施例３のチップモジュールの縦断面図の例である。It is an example of the longitudinal cross-sectional view of the chip module of Example 3. 接続関係を示す回路図の例である。It is an example of the circuit diagram which shows a connection relationship. 実施例４のガラスインターポーザの縦断面図の例である。It is an example of the longitudinal cross-sectional view of the glass interposer of Example 4. 実施例５のチップモジュールの縦断面図の例である。It is an example of the longitudinal cross-sectional view of the chip module of Example 5. チップモジュールの横断面図の例である。It is an example of the cross-sectional view of a chip module. チップモジュールを組み込んだ情報処理機器の基板部分を側面から見た図である。It is the figure which looked at the board | substrate part of the information processing apparatus incorporating the chip module from the side surface. 実施例７のチップモジュールの縦断面図の例である。FIG. 10 is an example of a vertical cross-sectional view of a chip module of Example 7. セラミックスインターポーザのビア抵抗値と１次モードのQ値との関係を示す。The relationship between the via resistance value of the ceramic interposer and the Q value of the primary mode is shown. セラミックスインターポーザのビア抵抗値と１次モードの周波数との関係を示す。The relationship between the via resistance value of a ceramic interposer and the frequency of a primary mode is shown. 実施例８のチップモジュールの縦断面図の例である。FIG. 10 is an example of a longitudinal sectional view of a chip module according to an eighth embodiment. 実施例９のチップモジュールの縦断面図の例である。It is an example of the longitudinal cross-sectional view of the chip module of Example 9.
　以下、本発明の一実施形態を、図面を参照して詳細に説明する。以下では、同じ機能、構成のものに対しては同じ符号を付与し説明を省略する。
[実施例１] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Below, the same code | symbol is provided with respect to the same function and a structure, and description is abbreviate | omitted.
[Example 1]
　図１は、実施例１のチップモジュール１００Ａの縦断面図の例であり、図２はチップモジュール１００Ａの横断面図の例である。より詳細には、図１の線Ａ－Ａにおける断面図の例が図２であり、図２の線Ｂ－Ｂにおける断面図の例が図１である。 FIG. 1 is an example of a longitudinal sectional view of the chip module 100A of the first embodiment, and FIG. 2 is an example of a transverse sectional view of the chip module 100A. More specifically, FIG. 2 is an example of a cross-sectional view taken along line AA in FIG. 1, and FIG. 1 is an example of a cross-sectional view taken along line BB in FIG.
　ここでいうチップモジュールとは、パッケージ基板と、ガラスインターポーザとを含み、ガラスインターポーザには１つ以上の半導体チップが搭載されているものをいう。半導体チップは、例えばLSI(Large Scale Integration)やIC（Integrated Circuit）であるが、これに限定しない。パッケージ基板は、電極部を介してガラスインターポーザと電気的に接続可能であればよく、特に限定しない。パッケージ基板は、ここではセラミック製であるものとするが、これに限定せず、例えば有機樹脂製など、他の任意の素材を採用しえる。また、ガラスインターポーザは、ガラス系材料で形成されたガラスコアを含み、ガラスコアの上面及び下面に導電性のプレーンを有し、この導電性のプレーン間を接続する少なくとも１つのスルービアを含むものであればよい。ガラス系材料としては、例えばガラスセラミックス、ホウケイ酸ガラス、石英ガラス、高ケイ酸ガラス等があるが、これに限定しない。 Here, the chip module includes a package substrate and a glass interposer, and one or more semiconductor chips are mounted on the glass interposer. The semiconductor chip is, for example, LSI (Large Scale Integration) or IC (Integrated Circuit), but is not limited thereto. The package substrate is not particularly limited as long as it can be electrically connected to the glass interposer via the electrode portion. Here, the package substrate is made of ceramic, but is not limited to this, and any other material such as an organic resin may be adopted. The glass interposer includes a glass core formed of a glass-based material, has conductive planes on the upper and lower surfaces of the glass core, and includes at least one through via that connects the conductive planes. I just need it. Examples of the glass material include, but are not limited to, glass ceramics, borosilicate glass, quartz glass, and high silicate glass.
　チップモジュール１００Ａは、ASIC（Application Specific Integrated Circuit）と光ICとを同一パッケージ基板に搭載したモジュールの例であるが、これに限らない。チップモジュール１００Ａには、ASICや光IC以外のICや、LSIなど、任意の半導体チップを搭載しても良い。また、ASICは、例えばFPGA（Field-Programmable Gate Array）やCPU（Central Processing Unit）、GPU(Graphics Processing Unit)でも良いし、光ICは、例えばシグナルコンディショナ(電気信号用中継LSI)でも良い。
　チップモジュール１００Ａは、ガラスインターポーザ５及びパッケージ基板３を含む。パッケージ基板３の上面にガラスインターポーザ５が搭載されている。 The chip module 100A is an example of a module in which an ASIC (Application Specific Integrated Circuit) and an optical IC are mounted on the same package substrate, but is not limited thereto. The chip module 100A may be mounted with any semiconductor chip such as an IC other than an ASIC or an optical IC, or an LSI. The ASIC may be, for example, an FPGA (Field-Programmable Gate Array), a CPU (Central Processing Unit), or a GPU (Graphics Processing Unit), and the optical IC may be, for example, a signal conditioner (electric signal relay LSI).
The chip module 100 </ b> A includes a glass interposer 5 and a package substrate 3. A glass interposer 5 is mounted on the upper surface of the package substrate 3.
　パッケージ基板３は、ビアホール９、導体層１０等を含む。パッケージ基板３の下面にはBGA（Ball Grid Array）ボール８が形成されている。 Package board 3 includes via hole 9, conductor layer 10, and the like. BGA (Ball Grid Array) balls 8 are formed on the lower surface of the package substrate 3.
　ガラスインターポーザ５の上面（パッケージ基板３と接続している面ではない面）には、バンプ４－２、４－３の各々が形成されている。ガラスインターポーザ５とASIC１および光IC２とは、バンプ４－２、４－３の各々により電気的に接続されている。ガラスインターポーザ５の下面（パッケージ基板３と接続している面）にはバンプ４－１が形成されている。パッケージ基板３とガラスインターポーザ５とは、バンプ４－１により電気的に接続している。 Each of the bumps 4-2 and 4-3 is formed on the upper surface of the glass interposer 5 (the surface not connected to the package substrate 3). The glass interposer 5 and the ASIC 1 and the optical IC 2 are electrically connected by the bumps 4-2 and 4-3, respectively. Bumps 4-1 are formed on the lower surface of glass interposer 5 (the surface connected to package substrate 3). The package substrate 3 and the glass interposer 5 are electrically connected by bumps 4-1.
　ガラスインターポーザ５は、少なくともガラスコア３０と、導体層１１とを含む。導体層１１は、ガラスコア３０の上面及び上面の各々に配置される。ガラスコア３０にはTGV６、TGV７の各々が形成されている。 The glass interposer 5 includes at least a glass core 30 and a conductor layer 11. The conductor layer 11 is disposed on each of the upper surface and the upper surface of the glass core 30. Each of TGV6 and TGV7 is formed in the glass core 30.
　TGV６は、貫通孔の内側に銅めっきが施されて形成される。TGV６によって、ガラスコア３０上下の電気的な接続がとられる。これらによってASIC１と光IC２の間の高密度な信号配線が形成される。なお、TGV６の内側に施される処理は、銅めっきに限るわけではなく、任意の素材や技術を用いることができる。 TGV6 is formed by copper plating inside the through hole. Electrical connection between the upper and lower sides of the glass core 30 is established by the TGV 6. As a result, a high-density signal wiring between the ASIC 1 and the optical IC 2 is formed. The treatment applied to the inside of the TGV 6 is not limited to copper plating, and any material or technique can be used.
　導体層１１は、信号配線のリターンプレーンとするために幅広なプレーンを含む。そのため、導体層１１及びガラスコア３０からなる構造は、空洞共振器のように機能し、TGV６を通過する信号や電源・グラウンドの電流変化によって共振ノイズが励起される。図１の破線２０は、共振ノイズの電界強度を模式的に示している。図示するように、TGV６で接続している場所は共振電圧の節になる。 The conductor layer 11 includes a wide plane to serve as a return plane for signal wiring. Therefore, the structure composed of the conductor layer 11 and the glass core 30 functions like a cavity resonator, and resonance noise is excited by a signal passing through the TGV 6 and a current change in the power supply / ground. A broken line 20 in FIG. 1 schematically shows the electric field strength of resonance noise. As shown in the figure, the place connected by TGV6 is a node of resonance voltage.
　TGV７は、貫通孔に所定材料が充填されて形成される。TGV７によって、ガラスコア３０の上下の導体層１１のプレーンが電気的に接続される。図示するように、TGV７の両端は、電界強度が大きく、ノイズ電圧の腹となる位置に配置されると効果的であるが、これに限定しない。 TGV7 is formed by filling a through hole with a predetermined material. The planes of the upper and lower conductor layers 11 of the glass core 30 are electrically connected by the TGV 7. As shown in the drawing, both ends of the TGV 7 are effective when placed at positions where the electric field strength is large and the antinodes of the noise voltage are present, but the present invention is not limited to this.
　なお、共振の腹となる位置は、節と節との間の中間地点であることが予測可能であり、また、ガラスコア３０の端部も共振の腹となる。従って、図２に一例を示すように、TGV７が配される位置は、ガラスコア３０の隅、ガラスコア３０の外周縁沿い、TGV６間のうち少なくとも１つであると効果的である。TGV７をTGV６間に配置する場合は、TGV６間の中間点又は中間点近傍であるほうが好ましい。可能であれば、電磁界解析を行って正確な共振電圧分布を求め、腹の位置にTGV７を配置することが好ましい。なお、TGV７は高抵抗であることから、TGV7の追加配置によって共振の電界分布が変化しない。このため、電磁界解析などによる共振の腹の位置の特定を繰り返すこと無く、TGV７の位置を定めることが可能となる。 In addition, it can be predicted that the position where the antinode of resonance is an intermediate point between the nodes, and the end of the glass core 30 also becomes the antinode of resonance. Therefore, as shown in FIG. 2, it is effective that the position where the TGV 7 is disposed is at least one of the corners of the glass core 30, along the outer peripheral edge of the glass core 30, and between the TGVs 6. When TGV7 is arranged between TGV6, it is preferable that the intermediate point between TGV6 or near the intermediate point. If possible, it is preferable to perform an electromagnetic field analysis to obtain an accurate resonance voltage distribution and place the TGV 7 at the antinode position. Since TGV7 has a high resistance, the electric field distribution of resonance does not change due to the additional arrangement of TGV7. For this reason, it is possible to determine the position of the TGV 7 without repeatedly specifying the position of the antinode of resonance by electromagnetic field analysis or the like.
　共振ノイズによってガラスコア３０の上下間の電圧が高くなると、TGV７を介して電流が流れ、電磁的なエネルギーが熱エネルギーに変換される。これにより、共振ノイズが減衰し、信号品質劣化や給電能力の劣化を避けることができる。 When the voltage between the upper and lower sides of the glass core 30 increases due to the resonance noise, a current flows through the TGV 7 and electromagnetic energy is converted into heat energy. As a result, resonance noise is attenuated, and signal quality deterioration and power supply capability deterioration can be avoided.
　なお、十分な共振減衰効果を持たせるため、TGV7の電気抵抗値は約１Ωよりも高い必要がある。本実施例では、貫通孔に充填させた所定材料により、約１Ωよりも高い電気抵抗値を実現する。また、TGV７によって接続されるプレーンはDC（Direct Current）的に同電位である必要がある。DC的に同電位である場合とは、例えば、両方がグラウンドプレーンであるか、両方が電源供給プレーンである場合である。 It should be noted that the electrical resistance value of TGV7 needs to be higher than about 1Ω in order to give a sufficient resonance damping effect. In this embodiment, an electric resistance value higher than about 1Ω is realized by a predetermined material filled in the through hole. The planes connected by the TGV 7 must have the same potential in terms of DC (Direct Current). The case of the same potential in terms of DC is, for example, the case where both are ground planes or both are power supply planes.
　例えばTGV６のような、銅めっきなどによるスルービアの電気抵抗値は約１Ωより大幅に低い場合がほとんどである。例えば、１００μm厚のガラスコアに直径２０μmで銅メッキ厚が５μmのTGVを作成した場合、電気抵抗値は１０mΩ以下となる。従って、TGV7は、TGV６よりも電気抵抗値の高いスルービアということもできる。
　なお、ここでいう「１Ω」などのような数値は、この数のみだけでなく、例えばモデル誤差や計測誤差などに起因する誤差範囲をも含むものとする。 For example, the electrical resistance value of through vias such as TGV6 due to copper plating is almost much lower than about 1Ω. For example, when a TGV having a diameter of 20 μm and a copper plating thickness of 5 μm is formed on a glass core having a thickness of 100 μm, the electric resistance value is 10 mΩ or less. Therefore, TGV7 can be said to be a through via having a higher electrical resistance value than TGV6.
It should be noted that the numerical value such as “1Ω” here includes not only this number but also an error range caused by, for example, a model error or a measurement error.
上記効果を示すために、ガラスコアの共振について三次元有限要素法によって、固有モード解析を行った。この解析は、共振への影響を端的に評価するために単純化した構造について行っている。図３は、固有モード解析対象のモデルを示す。モデル３００は、約３０mm角で厚みが約１００μｍのガラスコア３０の上下面に銅プレーン５０－１、５０－２を貼り付けたものである。モデル３００において、共振の腹となる位置は、例えばプレーンの四隅の位置５１である。このような場合において、以下の条件１～条件３の３つの条件の各々で、共振の安定性を表すQ値を求めた。なお、Q値は低い方が共振の減衰が早いことを示す。
　条件１：位置５１に何も配置しない
　条件２：位置５１に銅めっきによるTGVを配置して上下の銅プレーン５０－１、５０－２を電気的に接続する
　条件３：位置５１に約１Ωよりも高い電気抵抗値のTGVを配置して上下の銅プレーン５０－１、５０－２を電気的に接続する
　なお、各TGVの直径は約２０μmとし、約１Ωよりも高い電気抵抗値のTGVの、実際の電気抵抗値は一つあたり５Ωに設定した。 In order to show the above effect, eigenmode analysis was performed on the resonance of the glass core by the three-dimensional finite element method. This analysis is performed on a simplified structure in order to directly evaluate the influence on resonance. FIG. 3 shows a model for eigenmode analysis. The model 300 is obtained by bonding copper planes 50-1 and 50-2 on the upper and lower surfaces of the glass core 30 having a thickness of about 30 mm square and a thickness of about 100 μm. In the model 300, the position that becomes the antinode of resonance is, for example, the positions 51 of the four corners of the plane. In such a case, the Q value representing the stability of resonance was obtained under each of the following three conditions 1 to 3. The lower the Q value, the faster the resonance attenuation.
Condition 1: Nothing is placed at position 51 Condition 2: TGV by copper plating is placed at position 51 and upper and lower copper planes 50-1 and 50-2 are electrically connected Condition 3: From position 1 at about 1Ω The upper and lower copper planes 50-1 and 50-2 are electrically connected by arranging a TGV having a higher electrical resistance value. Each TGV has a diameter of about 20 μm and a TGV having an electrical resistance value higher than about 1Ω. The actual electric resistance value was set to 5Ω per one.
　図４は、上記モデル３００におけるQ値の比較結果である。グラフ４００は、上記条件１～３の各々について、１次モードから3次モードまでの各々の共振についてのQ値を示す。例えば、１次モードの棒４０１は条件１におけるQ値を示し、棒４０２は条件２におけるQ値を示し、棒４０３は条件３におけるQ値を示す。図示するように、条件１（棒４０１）に比較して、条件３（棒４０３）では、Q値が六分の一以下となっている。条件２（棒４０２）でもQ値の低減効果が認められるが、条件３（棒４０３）と比べると、その効果は小さいことがわかる。 FIG. 4 shows a comparison result of Q values in the model 300. The graph 400 shows the Q value for each resonance from the primary mode to the tertiary mode for each of the above conditions 1 to 3. For example, the bar 401 in the first mode indicates the Q value in the condition 1, the bar 402 indicates the Q value in the condition 2, and the bar 403 indicates the Q value in the condition 3. As shown in the figure, compared to condition 1 (bar 401), in condition 3 (bar 403), the Q value is 1/6 or less. Although the Q value reduction effect is recognized even under condition 2 (bar 402), it can be seen that the effect is small compared to condition 3 (bar 403).
　次に、電気抵抗値による影響をみるために、モデル３００についてTGVの電気抵抗値を変化させて、共振の１次モードのQ値および周波数の推移を解析した。図５は、TGVの電気抵抗値と１次モードのQ値との関係を示す。グラフ５００の横軸はTGVの電気抵抗値であり、縦軸はQ値である。 Next, in order to see the influence of the electrical resistance value, the electrical resistance value of the TGV was changed for the model 300, and the transition of the Q value and frequency of the primary mode of resonance was analyzed. FIG. 5 shows the relationship between the electrical resistance value of TGV and the Q value of the primary mode. The horizontal axis of the graph 500 is the electrical resistance value of TGV, and the vertical axis is the Q value.
　図示するように、電気抵抗値が約１Ω～約１０Ω近傍の部分でQ値が最低値を取ることが見て取れる。TGVの電気抵抗が低い場合は、TGVにおいて共振が熱エネルギーに変換される量が少ないために共振の減衰効果小さい。また、TGVの電気抵抗が高過ぎる場合は、TGVに電流が流れないために、減衰効果が小さい。TGVの電気抵抗が極端に高い場合（例えば約１０００Ω以上など）は共振減衰効果が得られず、約１００Ω以下とするとより望ましい。
　図６は、TGVの電気抵抗値と１次モードの周波数との関係を示す。グラフ６００の横軸はTGVの電気抵抗値であり、縦軸は周波数である。 As shown in the figure, it can be seen that the Q value takes the lowest value in the vicinity of the electric resistance value of about 1Ω to about 10Ω. When the electrical resistance of the TGV is low, the resonance attenuation effect is small because the amount of resonance converted into thermal energy in the TGV is small. In addition, when the electrical resistance of the TGV is too high, no current flows through the TGV, so the attenuation effect is small. When the electrical resistance of TGV is extremely high (for example, about 1000Ω or more), the resonance damping effect cannot be obtained, and it is more desirable to set the electrical resistance to about 100Ω or less.
FIG. 6 shows the relationship between the electrical resistance value of TGV and the frequency of the primary mode. The horizontal axis of the graph 600 is the electrical resistance value of TGV, and the vertical axis is the frequency.
　図示するように、周波数は、低抵抗側と高抵抗側とでそれぞれ異なり、約１Ω～約１０Ωの間で遷移している。高抵抗側の周波数の値はTGVを挿入しない場合の周波数に一致しており、低抵抗側の周波数の値は通常のTGVを挿入した場合の周波数に等しい。これは約１Ω以下のスルービアを挿入した場合は、共振の腹・節の位置が変化してしまうことを示している一方で、約１Ω～約１０Ωより大きいTGVを挿入した場合は、共振の腹・節の位置が変化しないことを意味している。 As shown in the figure, the frequency is different between the low resistance side and the high resistance side, and transitions between about 1Ω and about 10Ω. The frequency value on the high resistance side matches the frequency when TGV is not inserted, and the frequency value on the low resistance side is equal to the frequency when normal TGV is inserted. This indicates that if a through via of about 1Ω or less is inserted, the position of the resonance antinode / node changes, while if a TGV greater than about 1Ω to about 10Ω is inserted, the resonance antinode -This means that the position of the clause does not change.
　これらの結果から、約１Ωより大きい電気抵抗値を持つTGVを挿入することで、共振の腹・節を変化させることなく、効果的にQ値を下げることができることがわかる。なお、モデル３００におけるTGV構造の場合、例えば体積抵抗率が５μΩｍ程度の銀ペースト等を用いることで、電気抵抗値が約５ΩのTGVを実現することができる。
　図７は、TGV形成の一例を説明する図である。図では、簡略化のためにガラスコア３０に対する形成のみを説明する。 From these results, it can be seen that by inserting a TGV having an electric resistance value greater than about 1Ω, the Q value can be effectively lowered without changing the resonance antinodes and nodes. In the case of the TGV structure in the model 300, a TGV having an electric resistance value of about 5Ω can be realized by using, for example, a silver paste having a volume resistivity of about 5 μΩm.
FIG. 7 is a diagram for explaining an example of TGV formation. In the figure, only the formation with respect to the glass core 30 will be described for simplification.
　図７（Ａ）から（Ｅ）の順の工程によりTGVが形成される。図７（Ａ）はガラスコア３０のみを示す。図７（Ｂ）は、ガラスコア３０にレーザなどで貫通孔３１－１を設けた例である。ここでは、TGV７を形成する位置にのみ貫通孔３１－１が設けられる。図７（Ｃ）は、貫通孔３１－１に所定材料を充填した例である。このようにして、電気抵抗値が１Ωより大きいTGV７が形成される。図７（Ｄ）は、ガラスコア３０にレーザなどで貫通孔３１－２を設けた例である。ここでは、TGV６を形成する位置に貫通孔３１－２が設けられる。図７（Ｅ）は、貫通孔３１－２を形成したガラスコア３０に銅めっきを施した例である。これにより、TGV６が形成される。また、この工程の場合、この銅めっきにより、TGV６の形成と同時に導体層１１の形成が可能である。 TGV is formed by the steps in the order of FIG. 7 (A) to (E). FIG. 7A shows only the glass core 30. FIG. 7B shows an example in which a through hole 31-1 is provided in the glass core 30 with a laser or the like. Here, the through hole 31-1 is provided only at a position where the TGV 7 is formed. FIG. 7C shows an example in which the through hole 31-1 is filled with a predetermined material. In this way, the TGV 7 having an electrical resistance value greater than 1Ω is formed. FIG. 7D shows an example in which a through hole 31-2 is provided in the glass core 30 with a laser or the like. Here, a through hole 31-2 is provided at a position where the TGV 6 is formed. FIG. 7E shows an example in which copper plating is applied to the glass core 30 in which the through hole 31-2 is formed. Thereby, TGV6 is formed. In the case of this step, the conductor layer 11 can be formed simultaneously with the formation of the TGV 6 by this copper plating.
　なお、TGV形成は上記に限らない。例えば、１つのプロセスで、TGV６又はTGV７を設ける位置に貫通孔を形成し、貫通孔への充填のときには、TGV６を形成する貫通孔にマスクをすることで形成してもよい。
[実施例２] Note that TGV formation is not limited to the above. For example, a through hole may be formed in a position where the TGV 6 or TGV 7 is provided in one process, and when filling the through hole, the through hole forming the TGV 6 may be masked.
[Example 2]
　図８は、実施例２のチップモジュール１００Ｂの縦断面図の例であり、図９はチップモジュール１００Ｂの横断面図の例である。より詳細には、図８の線Ｃ－Ｃにおける断面図の例が図９であり、図９の線Ｄ－Ｄにおける断面図の例が図８である。 FIG. 8 is an example of a longitudinal sectional view of the chip module 100B of the second embodiment, and FIG. 9 is an example of a transverse sectional view of the chip module 100B. More specifically, FIG. 9 is an example of a cross-sectional view taken along line CC in FIG. 8, and FIG. 8 is an example of a cross-sectional view taken along line DD in FIG.
　上記実施例１と実施例２との違いは、電気抵抗が１Ωよりも大きいスルービアを実現するために、貫通孔に所定材料を充填したTGVの代わりに、導体薄膜とレジストとで構成されたTGVを用いる点である。導体薄膜の電気抵抗値は高いことから、上記実施例と同様の共振減衰効果を得ることができる。 The difference between the first embodiment and the second embodiment is that a TGV composed of a conductive thin film and a resist is used in place of the TGV in which a through hole is filled with a predetermined material in order to realize a through via having an electric resistance larger than 1Ω. It is a point to use. Since the electric resistance value of the conductor thin film is high, the same resonance attenuation effect as that in the above embodiment can be obtained.
　TGV１３の電気抵抗値は、上記のように、約１Ωより大きいことが好ましい。また、TGV１３を形成する位置についても、上記のように、共振の腹の位置に配置するのが最も効果的である。
　図１０は、TGV形成の一例を説明する図である。図では、簡略化のためにガラスコア３０に対する形成のみを説明する。 The electrical resistance value of TGV13 is preferably greater than about 1Ω as described above. Further, as described above, it is most effective to arrange the TGV 13 at the antinode of resonance as described above.
FIG. 10 is a diagram for explaining an example of TGV formation. In the figure, only the formation with respect to the glass core 30 will be described for simplification.
　図１０（Ａ）から（Ｅ）の順の工程によりTGVが形成される。図１０（Ａ）はガラスコア３０のみを示す。図１０（Ｂ）は、ガラスコア３０にレーザなどで貫通孔３１を設けた例である。ここでは、TGV６又はTGV１３を形成する位置に貫通孔３１が設けられる。図１０（Ｃ）は、例えば無電解めっきなどによって、貫通孔３１の内側に導体薄膜３２を形成した例である。導体薄膜３２は、例えばP-Ni合金のような抵抗率の高い導体を用いて約１um以下の厚みで形成する。図１０（Ｄ）は、導体薄膜３２を形成した貫通孔３１のうちTGV１３を形成する位置にあるものに、レジスト３３を充填した例である。これにより、TGV１３が形成される。レジスト３３及びその固化などは、例えばフォトリソグラフィ（Photolithography）技術を用いることが可能であるが、これに限定しない。図１０（Ｅ）は、TGV１３を形成したガラスコア３０に銅めっきを施した例である。これにより、導体薄膜３２を形成した貫通孔３１のうち、レジスト３３を充填していないものの内側に、銅めっきが形成され、TGV６及び導体層１１が形成される。
　本変形例では、上記したマスク等の工程を含めることなく、TGVの穴あけプロセスを一回とすることができる。 TGV is formed by the steps in the order of FIGS. FIG. 10A shows only the glass core 30. FIG. 10B is an example in which a through hole 31 is provided in the glass core 30 with a laser or the like. Here, the through hole 31 is provided at a position where the TGV 6 or TGV 13 is formed. FIG. 10C shows an example in which the conductive thin film 32 is formed inside the through hole 31 by, for example, electroless plating. The conductor thin film 32 is formed with a thickness of about 1 μm or less using a conductor having a high resistivity such as a P—Ni alloy. FIG. 10D shows an example in which a resist 33 is filled in the through hole 31 in which the conductive thin film 32 is formed at the position where the TGV 13 is formed. Thereby, TGV13 is formed. For example, photolithography (Photolithography) technology can be used for the resist 33 and its solidification, but the resist 33 is not limited thereto. FIG. 10E shows an example in which copper plating is applied to the glass core 30 on which the TGV 13 is formed. Thereby, copper plating is formed inside the through-hole 31 in which the conductive thin film 32 is formed but the resist 33 is not filled, and the TGV 6 and the conductor layer 11 are formed.
In this modification, the TGV drilling process can be performed once without including the steps such as the mask described above.
　なお、本変形例では、TGV１３の中空部はレジストにより充填されているが、中空のままとしても良い。ただし、レジスト等で中空部を充填したほうがガラスコア３０の強度が増加する。
[実施例３] In this modification, the hollow portion of the TGV 13 is filled with a resist, but it may be left hollow. However, the strength of the glass core 30 increases when the hollow portion is filled with a resist or the like.
[Example 3]
　図１１は、実施例３のチップモジュール１００Ｃの縦断面図の例である。本実施例では、TGV７で接続されるガラスコア３０の上下面のプレーンが同電位でない場合に対応可能なものである。そのために、チップモジュール１００Ｃは、TGV７の近傍にコンデンサ１４を設け、このコンデンサ１４とTGV７との両方を介して、ガラスコア３０の上下プレーンを電気的に接続している。この上下プレーンは、図１１では導体層１１の例を示しているが、これに限定しない。 FIG. 11 is an example of a longitudinal sectional view of the chip module 100C of the third embodiment. In this embodiment, it is possible to cope with the case where the planes of the upper and lower surfaces of the glass core 30 connected by the TGV 7 are not at the same potential. For this purpose, the chip module 100C is provided with a capacitor 14 in the vicinity of the TGV 7, and the upper and lower planes of the glass core 30 are electrically connected through both the capacitor 14 and the TGV 7. Although the upper and lower planes show an example of the conductor layer 11 in FIG. 11, the upper and lower planes are not limited to this.
　図１２は、接続関係を示す回路図の例である。下部プレーン４３と接続されたTGV７と直列にコンデンサ１４が接続され、その先が上部プレーン４２と接続される。即ち、２つのプレーンは、直列に接続されたTGV７及びコンデンサ１４を介して電気的に接続される。 FIG. 12 is an example of a circuit diagram showing a connection relationship. The capacitor 14 is connected in series with the TGV 7 connected to the lower plane 43, and the tip is connected to the upper plane 42. That is, the two planes are electrically connected via the TGV 7 and the capacitor 14 connected in series.
　コンデンサ１４は、実装スペースの関係から、小さいサイズのものが好ましい。そのようなコンデンサとしては、例えば薄膜コンデンサがあるが、これに限定しない。 The capacitor 14 is preferably a small size because of the mounting space. An example of such a capacitor is a thin film capacitor, but is not limited thereto.
　このように、直列に接続されたTGV７とコンデンサとを介して２つのプレーンを接続することで、これらのプレーンがDC的に同電位でない場合でも、共振減衰効果を得ることが可能である。プレーンがDC的に同電位でない場合としては、例えば一方が電源、他方がグラウンドプレーンであるような場合である。
　なお、ここでは、コンデンサをガラスコア３０の上部に配置しているが、これに限らず、コンデンサは、ガラスコア３０の下部に配置されても良い。 In this way, by connecting the two planes via the TGV 7 and the capacitor connected in series, it is possible to obtain a resonance damping effect even when these planes are not DC in the same potential. The case where the plane is not at the same potential in terms of DC is, for example, the case where one is a power supply and the other is a ground plane.
In addition, although the capacitor | condenser is arrange | positioned here at the upper part of the glass core 30, not only this but a capacitor | condenser may be arrange | positioned at the lower part of the glass core 30. FIG.
　また、TGV７ではなく、TGV１３とコンデンサとを介して２つのプレーンを直列に接続してもよい。即ち、電気抵抗値が約１Ωよりも大きいTGVとコンデンサとを介して２つのプレーンを直列に接続できればよい。 Also, instead of TGV7, two planes may be connected in series via TGV13 and a capacitor. That is, it is only necessary that two planes can be connected in series via a TGV and a capacitor having an electrical resistance value greater than about 1Ω.
　また、ガラスコア３０の上下部のプレーンが同電位である部分と、同電位でない部分とが混在する場合は、上記実施例１、２のように、コンデンサなしで接続する構造を混在させることができる。
[実施例４] In addition, when the upper and lower planes of the glass core 30 have the same potential and the non-equal potential, a structure connected without a capacitor can be mixed as in the first and second embodiments. it can.
[Example 4]
　図１３は、実施例４のガラスインターポーザの縦断面図の例である。本実施例のチップモジュール１００Ｄは、実施例２と比較して、導体薄膜３４を設ける範囲が異なる。チップモジュール１００Ｄでは、導体薄膜３４が、貫通孔の内側だけではなく、ガラスコア３０の上面及び下面の各々（例えば面１３０１、面１３０２）にも形成され、その上に銅メッキ３５が施されて、導体層が形成される。この点を除き、チップモジュール１００Ｄの構造はチップモジュール１００Ｂと同じである。 FIG. 13 is an example of a longitudinal sectional view of the glass interposer of Example 4. The chip module 100D of the present embodiment is different from the second embodiment in the range in which the conductor thin film 34 is provided. In the chip module 100D, the conductor thin film 34 is formed not only on the inside of the through hole but also on each of the upper and lower surfaces (for example, the surface 1301 and the surface 1302) of the glass core 30, and the copper plating 35 is applied thereon. A conductor layer is formed. Except for this point, the structure of the chip module 100D is the same as that of the chip module 100B.
　本実施例の構造では、上記実施例と同様に、電気抵抗が約１Ωよりも大きいTGVによって、共振ノイズの減衰効果が得られる。また、ガラスコア内に励起された共振ノイズの電流は表皮効果によって、上下面プレーンのガラスコア３０側に集中するため、ガラスコア３０の上面及び下面に設けた導体薄膜３４によっても、共振ノイズの減衰効果が得られる。
[実施例５] In the structure of the present embodiment, the resonance noise attenuation effect can be obtained by the TGV having an electric resistance larger than about 1Ω as in the above embodiment. Moreover, since the resonance noise current excited in the glass core is concentrated on the glass core 30 side of the upper and lower planes due to the skin effect, the conductive thin film 34 provided on the upper and lower surfaces of the glass core 30 also causes resonance noise. A damping effect is obtained.
[Example 5]
　図１４は、実施例５のチップモジュール１００Ｅの縦断面図の例であり、図１５はチップモジュール１００Ｅの横断面図の例である。より詳細には、図１４の線Ｅ－Ｅにおける断面図の例が図１５であり、図１５の線Ｆ－Ｆにおける断面図の例が図１４である。 FIG. 14 is an example of a longitudinal sectional view of the chip module 100E of Example 5, and FIG. 15 is an example of a transverse sectional view of the chip module 100E. More specifically, FIG. 15 is an example of a cross-sectional view taken along line EE in FIG. 14, and FIG. 14 is an example of a cross-sectional view taken along line FF in FIG.
　本実施例と上記実施例との差異は、パッケージ基板３上に、Siインターポーザ６０がさらに搭載され、Siインターポーザ６０及びガラスインターポーザ５の各々に跨ってASIC１が搭載される点である。 The difference between the present embodiment and the above embodiment is that a Si interposer 60 is further mounted on the package substrate 3 and the ASIC 1 is mounted across the Si interposer 60 and the glass interposer 5.
　図１４、図１５の場合、チップモジュール１００Ｅには、１つのパッケージ基板３上に、４つのガラスインターポーザ５－１～５－４が搭載される。ガラスインターポーザ５の各々には、１つのIC２が搭載され、１つのチップモジュール１００Ｅは合計４つの光IC２－１～２－４を含むことになる。 14 and 15, four glass interposers 5-1 to 5-4 are mounted on one package substrate 3 in the chip module 100E. Each glass interposer 5 has one IC 2 mounted thereon, and one chip module 100E includes a total of four optical ICs 2-1 to 2-4.
　セラミックパッケージ基板３の中央又はその近傍にはSiインターポーザ６０が配置され、その周囲のうち少なくとも一部に、ガラスインターポーザ５が配置される。Siインターポーザ６０の上には、少なくとも１つのASIC１が配置される。ASIC１は、ガラスインターポーザ５－１～５－４の各々とSiインターポーザ６０との両方に跨るように配置される。即ち、ASIC１は、ガラスインターポーザ５とSiインターポーザ６０との各々を介して、パッケージ基板３と電気的に接続される。 The Si interposer 60 is disposed at the center of the ceramic package substrate 3 or in the vicinity thereof, and the glass interposer 5 is disposed at least partially around the periphery. At least one ASIC 1 is disposed on the Si interposer 60. The ASIC 1 is disposed so as to straddle both the glass interposers 5-1 to 5-4 and the Si interposer 60. That is, the ASIC 1 is electrically connected to the package substrate 3 via each of the glass interposer 5 and the Si interposer 60.
　従って、チップモジュール１００Ｅを上面から見たときの、Siインターポーザ６０の占有範囲のうち少なくとも一部は、ASIC１の占有範囲内に含まれる。また、チップモジュール１００Ｅを上面から見たときの、Siインターポーザ６０及びASIC１の占有範囲は、４つのガラスインターポーザ５－１～５－４の各々の占有範囲の一部と重なるように配置される。また、チップモジュール１００Ｅを上面から見たときの、Siインターポーザ６０及びASIC１の占有範囲は、ガラスインターポーザ５の各々に搭載されたIC２の各々の占有範囲とは、重ならないように配置される。 Therefore, at least a part of the occupation range of the Si interposer 60 when the chip module 100E is viewed from above is included in the occupation range of the ASIC 1. Further, when the chip module 100E is viewed from above, the occupation range of the Si interposer 60 and the ASIC 1 is arranged so as to overlap a part of the occupation range of each of the four glass interposers 5-1 to 5-4. Further, when the chip module 100E is viewed from above, the occupation range of the Si interposer 60 and the ASIC 1 is arranged so as not to overlap with the occupation range of each IC 2 mounted on each of the glass interposers 5.
　ASIC１は、ガラスインターポーザ５と接続するための、高速信号用の電極部が設けられている。この電極部は、限定はしないが、例えばピン、バンプやリードなどであり（例えばバンプ１４０１）、この場合は、ASIC１の外周縁に沿って設けられている。この高速信号の配線はガラスインターポーザ５－１～５－４の各々の信号配線（図示略）を介して、光IC２－１～２－４の各々に接続される。このように、高速な信号については、低損失なガラスインターポーザを介して伝送することで、信号品質の劣化を抑えることができる。 The ASIC 1 is provided with an electrode portion for high-speed signals for connecting to the glass interposer 5. Although this electrode part is not limited, it is a pin, a bump, a lead, etc. (for example, bump 1401), for example, and is provided along the outer periphery of ASIC1 in this case. The high-speed signal wiring is connected to each of the optical ICs 2-1 to 2-4 via each signal wiring (not shown) of the glass interposers 5-1 to 5-4. As described above, the high-speed signal can be transmitted through the low-loss glass interposer to suppress the deterioration of the signal quality.
　ASICは、Siインターポーザ６０と接続するための、低速な信号およびコア回路の電源・グラウンなどのための電極部が設けられている。この電極部は、限定はしないが、例えばピン、バンプやリードなどであり（例えばバンプ１４０２）、この場合は、ASIC１の中央近傍に設けられている。この配線は、Siインターポーザ６０のスルービア６１を介してパッケージ基板３と接続される。このように、大電流であるコア回路の電源・グラウンドについては、損失が大きいSiインターポーザを介して給電するため、共振ノイズの問題を起きにくくすることができる。 The ASIC is provided with electrodes for low-speed signals and power supply / ground of the core circuit for connection with the Si interposer 60. Although this electrode part is not limited, it is a pin, a bump, a lead, etc. (for example, bump 1402), for example, and is provided in the center vicinity of ASIC1 in this case. This wiring is connected to the package substrate 3 through the through via 61 of the Si interposer 60. As described above, since power is supplied to the power source / ground of the core circuit having a large current through the Si interposer having a large loss, the problem of resonance noise can be made difficult to occur.
　加えて、ガラスインターポーザ５の各々は、上記した実施例１～実施例４のいずれかの構成を含む。図１４では、実施例１のような、TGV７を含む例を示しているが、TGV１３であってもよい。TGV７及びTGV１３のいずれであっても、その配置位置は上記実施例と同じである。また、複数のガラスインターポーザ５が搭載される場合は、それぞれのガラスインターポーザ５が、上記した実施例１～実施例４のうち異なる実施例の構成を含んでもよい。これにより、上記のように、ガラスインターポーザ側の共振を減衰させることができる。 In addition, each of the glass interposers 5 includes any one of the configurations of the first to fourth embodiments described above. FIG. 14 shows an example including TGV7 as in the first embodiment, but TGV13 may be used. In any of TGV7 and TGV13, the arrangement position is the same as in the above embodiment. When a plurality of glass interposers 5 are mounted, each glass interposer 5 may include a configuration of a different example among the above-described first to fourth examples. Thereby, as described above, the resonance on the glass interposer side can be attenuated.
　なお、１つのパッケージ基板３上に搭載するSiインターポーザ６０、ガラスインターポーザ５、ASIC１の各々の数は１つ以上であればよく、図示するものに限らない。
[実施例６]
　図１６は、チップモジュール１００を組み込んだ情報処理機器の基板部分を側面から見た図である。
　なお、ここでいう情報処理機器は、ICやLSIなどの演算装置を含み、所望の演算を実行可能なものをいう。 Note that the number of each of the Si interposer 60, the glass interposer 5, and the ASIC 1 mounted on one package substrate 3 may be one or more, and is not limited to that illustrated.
[Example 6]
FIG. 16 is a side view of the substrate portion of the information processing apparatus in which the chip module 100 is incorporated.
Note that the information processing equipment here refers to a device that includes an arithmetic device such as an IC or LSI and that can execute a desired arithmetic operation.
　情報処理機器２００は、複数のチップモジュール１００、複数のマザーボード７１、複数のコネクタ７２、バックプレーンボード７３及び光ファイバ７４等を含む。これらの数は、単数でも複数でもよく、図示するものに限定しない。ただし、複数のチップモジュール１００及びマザーボード７１が同時に処理を行うことで、効率的な情報処理を行うことができる。 The information processing apparatus 200 includes a plurality of chip modules 100, a plurality of motherboards 71, a plurality of connectors 72, a backplane board 73, an optical fiber 74, and the like. These numbers may be singular or plural and are not limited to those shown. However, efficient information processing can be performed by performing processing simultaneously by the plurality of chip modules 100 and the motherboard 71.
　実施例１～実施例５のいずれか又は複数のチップモジュール１００－１～１００－３は、マザーボード７１－１～７１－３の各々上に搭載される。図１６では、チップモジュール１００Ｅが搭載された例を示している。マザーボード７１－１～７１－３の各々は、コネクタ７２－１～７２－３によってバックプレーンボード７３に電気的に接続される。チップモジュール１００－１～１００－３の各々の上に搭載された光ICには、光ファイバ７４－１、７４－２が接続され、チップモジュール１００－１～１００－３同士が光信号で通信可能である。 Any one or a plurality of chip modules 100-1 to 100-3 of the first to fifth embodiments are mounted on each of the mother boards 71-1 to 71-3. FIG. 16 shows an example in which the chip module 100E is mounted. Each of the mother boards 71-1 to 71-3 is electrically connected to the backplane board 73 by connectors 72-1 to 72-3. Optical fibers 74-1 and 74-2 are connected to the optical ICs mounted on each of the chip modules 100-1 to 100-3, and the chip modules 100-1 to 100-3 communicate with each other by optical signals. Is possible.
　チップモジュール１００－１～１００－３はASICと光ICが高密度かつ低ノイズに接続されているため、上記のように実装することで、広帯域な信号伝送能力を持つことが可能となる。また、チップモジュール１００－１～１００－３同士でも、高速な光信号伝送を行うことが可能となる。これにより、情報処理能力の向上が可能となる。 Since the ASIC and the optical IC are connected to the chip modules 100-1 to 100-3 with high density and low noise, the chip modules 100-1 to 100-3 can have a broadband signal transmission capability by being mounted as described above. In addition, high-speed optical signal transmission can be performed between the chip modules 100-1 to 100-3. Thereby, the information processing capability can be improved.
[実施例７]
　図１７は、実施例７のチップモジュール１００Fの縦断面図の例である。上記実施例１～６では、ガラスインターポーザを対象とした実施例であったが、低損失なセラミックス等の基板を用いたモジュールにおいても同様に共振問題が起こりうる。そこで、実施例７では、セラミックスインターポーザにおいて高抵抗のビアホールを配置し、プレーン間の共振を抑えて、特性劣化を回避する。 [Example 7]
FIG. 17 is an example of a vertical cross-sectional view of the chip module 100F of the seventh embodiment. In the first to sixth embodiments, the glass interposer is used as an object. However, a resonance problem may also occur in a module using a substrate such as a low-loss ceramic. Thus, in the seventh embodiment, via holes having high resistance are arranged in the ceramic interposer to suppress resonance between planes and avoid characteristic deterioration.
　チップモジュール１００Ｆでは、セラミックスインターポーザ３００の上面に、ASIC１および光IC２が配置されている。ASIC1と光IC2は、バンプ４－２および４－３によって、それぞれセラミックスインターポーザ３００の表層の導体層３０２と接続されている。一方で、セラミックスインターポーザ３００は、下面に配置されたBGAボール８によって、プリント基板等に電気的に接続される。 In the chip module 100F, the ASIC 1 and the optical IC 2 are arranged on the upper surface of the ceramic interposer 300. The ASIC 1 and the optical IC 2 are connected to the surface conductor layer 302 of the ceramic interposer 300 by bumps 4-2 and 4-3, respectively. On the other hand, the ceramic interposer 300 is electrically connected to a printed circuit board or the like by BGA balls 8 arranged on the lower surface.
　セラミックスインターポーザ３００は、セラミックス基板３０５－１～３０５－５と導体層３０２が積層された構造となっている。導体層３０２には、配線パターンや電源・GNDプレーンが形成される。セラミックス基板３０５の上面と下面の導体層３０２を電気的に接続するために、電気抵抗の低いビアホール３０３がセラミックス基板３０５を貫通するように配置される。 The ceramic interposer 300 has a structure in which ceramic substrates 305-1 to 305-5 and a conductor layer 302 are laminated. A wiring pattern and a power / GND plane are formed on the conductor layer 302. In order to electrically connect the upper and lower conductor layers 302 of the ceramic substrate 305, a via hole 303 having a low electrical resistance is disposed so as to penetrate the ceramic substrate 305.
　セラミックス基板３０５－１～３０５－５間の空洞共振を回避するために、高抵抗のビアホール３０４が共振電圧の腹の位置に配置される。ビアホール３０４は、セラミックス基板３０５－１～３０５－５の隅や外周淵沿いなどに配置されると効果的である。 In order to avoid cavity resonance between the ceramic substrates 305-1 to 305-5, a high-resistance via hole 304 is disposed at the antinode of the resonance voltage. The via holes 304 are effective if they are arranged at the corners of the ceramic substrates 305-1 to 305-5 or along the outer periphery of the ceramic substrate.
　共振低減を効果的にするために、高抵抗のビアホール３０４は、ガラスインターポーザの場合と同様に１Ω以上である必要がある。高抵抗のビアホール３０４の電気抵抗の影響をみるために、大きさが３０mm角で厚みが８０μｍのセラミックス基板の上下に、銀によってGNDプレーンを形成したモデルを用意した。そして、前記セラミック基板の四隅に抵抗性のビアホールを配置した場合の構造について、ビアホールの抵抗値を変えながら電磁界解析を行い、プレーン共振の変化を解析した。 In order to effectively reduce resonance, the high-resistance via hole 304 needs to be 1Ω or more as in the case of the glass interposer. In order to examine the influence of the electrical resistance of the high-resistance via hole 304, a model was prepared in which a GND plane was formed of silver on the upper and lower sides of a ceramic substrate having a size of 30 mm square and a thickness of 80 μm. And about the structure at the time of arrange | positioning a resistive via hole in the four corners of the said ceramic substrate, the electromagnetic field analysis was performed changing the resistance value of a via hole, and the change of plane resonance was analyzed.
　図１８は、セラミックスインターポーザのビア抵抗値と１次モードのQ値との関係を示す。グラフ５０１の横軸はビアホール３０４の電気抵抗値であり、縦軸は１次モードのQ値である。図示するように、ガラスインターポーザの場合と同様に１Ωから１０Ωの近傍の部分でQ値が最低値を取ることが見て取れる。 FIG. 18 shows the relationship between the via resistance value of the ceramic interposer and the Q value of the primary mode. The horizontal axis of the graph 501 is the electrical resistance value of the via hole 304, and the vertical axis is the Q value of the primary mode. As shown in the figure, it can be seen that the Q value takes the lowest value in the vicinity of 1Ω to 10Ω as in the case of the glass interposer.
　図１９は、セラミックスインターポーザのビア抵抗値と１次モードの周波数との関係を示す。グラフ６０１の横軸はビアホール３０４の電気抵抗値であり、縦軸は１次モードの周波数である。図示するように、セラミックスインターポーザの場合もガラスインターポーザと同様に、約１Ω～１０Ωの間で共振周波数が変化している。これは、１Ω以下のビアホールを挿入した場合は、共振の腹・節の位置が変化してしまうことを示している一方で、約１Ω～約１０Ωより大きいビアホールを挿入した場合は、共振の腹・節の位置が変化しないことを意味している。 FIG. 19 shows the relationship between the via resistance value of the ceramic interposer and the frequency of the primary mode. The horizontal axis of the graph 601 is the electrical resistance value of the via hole 304, and the vertical axis is the frequency of the primary mode. As shown in the figure, in the case of the ceramic interposer, the resonance frequency changes between about 1Ω and 10Ω as in the case of the glass interposer. This indicates that when a via hole of 1Ω or less is inserted, the position of the resonance antinode / node changes, whereas when a via hole larger than about 1Ω to about 10Ω is inserted, the resonance antinode -This means that the position of the clause does not change.
　これらの結果から、約１Ωより大きい電気抵抗値を持つビアホールを挿入することで、共振の腹・節を変化させることなく、効果的にQ値を下げることができることがわかる。 From these results, it can be seen that by inserting a via hole having an electrical resistance value greater than about 1Ω, the Q value can be effectively lowered without changing the antinode or node of resonance.
　また、実施例７では、基板材料としてセラミックを用いた例を示したが、低損失な樹脂基材などを用いても良い。 In Example 7, an example in which ceramic is used as the substrate material is shown, but a low-loss resin base material or the like may be used.
[実施例８]
　図２０は、実施例８のチップモジュール１００Gの縦断面図の例である。実施例８のチップモジュール１００Gでは、実施例７のチップモジュール１００Ｆに対し、コンデンサ３０６がセラミックスインターポーザ３００の上面に配置されている。 [Example 8]
FIG. 20 is an example of a longitudinal sectional view of the chip module 100G of the eighth embodiment. In the chip module 100G of the eighth embodiment, the capacitor 306 is disposed on the upper surface of the ceramic interposer 300 with respect to the chip module 100F of the seventh embodiment.
　実施例３の場合と同様に、セラミックス基板３０５－１～３０５～５の上下プレーンが同電位でない場合は、高抵抗のビアホール３０４とコンデンサ３０６とを直列に接続し、コンデンサ３０６を介して上下プレーンを接続する。内層の高抵抗のビアホール３０４とコンデンサ３０６とを接続する際には、低抵抗のビアホール３０３を介して接続される。このようにすることで、電源とGNDのように、電位が異なるプレーン間の共振を抑えることができる。 As in the case of the third embodiment, when the upper and lower planes of the ceramic substrates 305-1 to 305-5 are not at the same potential, a high resistance via hole 304 and a capacitor 306 are connected in series, and the upper and lower planes are connected via the capacitor 306. Connect. When the inner layer high resistance via hole 304 and the capacitor 306 are connected, the connection is made through the low resistance via hole 303. By doing so, resonance between planes with different potentials such as the power supply and GND can be suppressed.
　なお、図２０の例では、セラミックスインターポーザ３００の上面にコンデンサ３０６を配置しているが、下面に配置しても良い。また、コンデンサとしてはセラミックスインターポーザ３００内に形成した容量を用いても良い。 In the example of FIG. 20, the capacitor 306 is disposed on the upper surface of the ceramic interposer 300, but may be disposed on the lower surface. Further, a capacitor formed in the ceramic interposer 300 may be used as the capacitor.
[実施例９]
　図２１は、実施例９のチップモジュール１００Hの縦断面図の例である。実施例９のチップモジュール１００Ｈでは、実施例７、８のチップモジュール１００Ｆ、１００Ｇに対し、セラミックスインターポーザ３００の上面に、狭ピッチ配線が形成可能なビルドアップ層３０７を有している。ビルドアップ層３０７は、通常ポリイミドなどの薄膜を誘電体材料として使用するが、材料はこれに限らない。 [Example 9]
FIG. 21 is an example of a vertical cross-sectional view of the chip module 100H of the ninth embodiment. The chip module 100H according to the ninth embodiment has a buildup layer 307 capable of forming a narrow pitch wiring on the upper surface of the ceramic interposer 300 as compared with the chip modules 100F and 100G according to the seventh and eighth embodiments. The build-up layer 307 normally uses a thin film such as polyimide as a dielectric material, but the material is not limited to this.
　ビルドアップ層３０７は、セラミックスインターポーザ３００内よりも細い配線によって、ASIC1と光IC２などを多数の配線で接続する。ビルドアップ層３０７上には、必要に応じて給電を助けるためのコンデンサ３０６が配置される。コンデンサ３０６は、上記実施例８と同様にセラミックス基板３０５－１～３０５－５の共振を抑えるための高抵抗のビアホール３０４と直列に接続され、電位の異なるプレーン間の共振を抑えることができる。 The build-up layer 307 connects the ASIC 1 and the optical IC 2 with a large number of wires by using finer wires than those in the ceramic interposer 300. On the build-up layer 307, a capacitor 306 for assisting power supply is disposed as necessary. The capacitor 306 is connected in series with the high resistance via hole 304 for suppressing the resonance of the ceramic substrates 305-1 to 305-5 in the same manner as in the eighth embodiment, and can suppress the resonance between the planes having different potentials.
　以上、本発明者によってなされた発明を、一例に基づき具体的に説明した。サーバ等の情報機器の分野では、装置の高性能化のために装置内の伝送スループットの向上が望まれている。たとえば、処理ノードとスイッチノードを繋ぐ６０ｃｍ程度の基板間伝送では、高速化に伴う損失増大においても伝送性能トレンドを維持するために、例えばシグナルコンディショナや光モジュールのような、伝送距離を延長するための中継LSIを用いている。また、情報機器の分野では、演算装置（例えばCPUなど）のマルチコア化に伴って演算装置－メモリ（例えばDRAMなど)間の要求スループットも年々向上しており、これらを高密度に接続する技術が必要である。 As mentioned above, the invention made by the present inventor has been specifically described based on an example. In the field of information equipment such as servers, it is desired to improve the transmission throughput in the apparatus in order to improve the performance of the apparatus. For example, in inter-substrate transmission of about 60 cm connecting a processing node and a switch node, in order to maintain a transmission performance trend even in a loss increase accompanying an increase in speed, for example, a transmission distance such as a signal conditioner or an optical module is extended. For this purpose, a relay LSI is used. In the field of information equipment, the required throughput between computing devices and memories (such as DRAM) is increasing year by year as the computing devices (such as CPUs) become multi-core, and there is a technology for connecting them at high density. is necessary.
　これらのような技術の実現には、基板内伝送スループットの向上が必要である。従来では、配線一本あたりの伝送速度の向上により、スループット向上を実現してきた。しかし、25Gbps超の伝送速度では、損失等による技術困難度が増す。そこで、スループット向上のための他の技術として、配線密度を高くすることが考えられる。配線密度を高くすることで、全体としてのスループットが向上可能である。配線密度を高くするために、コア材としてＳｉ基板を用いる技術がある。 In order to realize such technologies, it is necessary to improve the transmission throughput within the substrate. Conventionally, throughput has been improved by improving the transmission speed per wiring. However, at a transmission rate exceeding 25 Gbps, the technical difficulty due to loss increases. Thus, it is conceivable to increase the wiring density as another technique for improving the throughput. By increasing the wiring density, the overall throughput can be improved. In order to increase the wiring density, there is a technique using a Si substrate as a core material.
　この場合、Ｓｉ基板をコア材として、その平面上にμｍオーダーの微細な配線を形成して、半導体チップ間を高密度に電気接続する。また下側のパッケージ（有機またはセラミック製）とはTSV(Through Si Via)を介して電気的に接続する。このような実装は、２．５次元実装と呼ばれている。 In this case, using a Si substrate as a core material, fine wiring of the order of μm is formed on the plane, and the semiconductor chips are electrically connected with high density. The lower package (made of organic or ceramic) is electrically connected via TSV (Through Si Via). Such an implementation is called a 2.5-dimensional implementation.
　また、他の要求として、コスト低減がある。コストを低減するために、コア材として、ガラスを用いる技術がある。ガラスは低損失であるため、信号波形の劣化が少ないという利点がある。 Another requirement is cost reduction. In order to reduce costs, there is a technique using glass as a core material. Since glass has a low loss, there is an advantage that the signal waveform is hardly deteriorated.
　しかし、コア材としてガラスを用いる場合、信号波形の劣化が少ないゆえに、ノイズの減衰も少ない。従って、コア材両面のプレーンが空洞共振器のように作用し、特性劣化を引き起こす。これにより、電源やグランドインピーダンスの劣化や、コア材を貫通する信号配線の特性劣化などが発生する。 However, when glass is used as the core material, there is little deterioration of the signal waveform, so there is little attenuation of noise. Therefore, the planes on both sides of the core material act like a cavity resonator and cause characteristic deterioration. As a result, the power supply and the ground impedance are degraded, and the characteristics of the signal wiring penetrating the core material are degraded.
　上記した実施例は、ガラスコアに、約１Ωより大きい電気抵抗値を持つTGVを設けている。ガラスコア内に発生した共振ノイズ電圧により、このTGVの両端にかかる際に電流が流れる。これにより、共振ノイズの電磁的なエネルギーが熱エネルギーに変換され、共振ノイズを効率的に減衰させることができる。また、このTGVに流れる電流は微小であるため、このTGVの追加が共振の腹・節の位置に与える影響を無視することができる。このため、１Ωより大きい電気抵抗値を持たないTGVを追加する場合とは異なり、一度、共振ノイズの分布を計算すれば、その分布に基づいて、共振の腹の位置にTGVを配置すれば良く、共振ノイズを対策した設計が容易となる。 In the above-described embodiment, a TGV having an electric resistance value greater than about 1Ω is provided on the glass core. The resonance noise voltage generated in the glass core causes a current to flow when applied to both ends of the TGV. Thereby, the electromagnetic energy of the resonance noise is converted into heat energy, and the resonance noise can be efficiently attenuated. Further, since the current flowing through the TGV is very small, the influence of the addition of the TGV on the position of the resonance antinode or node can be ignored. For this reason, unlike the case of adding a TGV that does not have an electrical resistance value greater than 1Ω, once the resonance noise distribution is calculated, the TGV may be placed at the antinode position of the resonance based on the distribution. This makes it easy to design with countermeasures against resonance noise.
　以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は上記に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。例えば、上記の実施例は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることも可能である。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることが可能である。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above, and various modifications can be made without departing from the scope of the invention. Nor. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.
　１００：チップモジュール、１：ASIC、２：光IC、３：パッケージ基板、４：バンプ、５：ガラスインターポーザ、６：TGV、７：TGV、８：バンプ、９：スルービア、１０：導体層、１１：導体層、１３：TGV、６０：Siインターポーザ、２００：情報処理機器、３００：セラミックスインターポーザ、３０３：ビアホール、３０４：ビアホール、３０７：ビルドアップ層。 100: chip module, 1: ASIC, 2: optical IC, 3: package substrate, 4: bump, 5: glass interposer, 6: TGV, 7: TGV, 8: bump, 9: through via, 10: conductor layer, 11 : Conductor layer, 13: TGV, 60: Si interposer, 200: Information processing device, 300: Ceramic interposer, 303: Via hole, 304: Via hole, 307: Build-up layer.

Claims (8)

  1. 　半導体チップとインターポーザを有し、
    　前記インターポーザは、電気抵抗値が約１Ωよりも大きいスルービアを有すること
    　を特徴とするチップモジュール。     Having a semiconductor chip and an interposer,
    The interposer has a through via having an electric resistance value larger than about 1Ω.
  2. 　請求項１に記載のチップモジュールであって、
    　前記インターポーザは、
    　スルービアに所定材料を充填することで、電気抵抗値が約１Ωよりも大きいスルービアを実現すること
    　を特徴とするチップモジュール。     The chip module according to claim 1,
    The interposer is
    A chip module characterized by realizing a through via having an electrical resistance value larger than about 1Ω by filling the through via with a predetermined material.
  3. 　請求項１に記載のチップモジュールであって、
    　前記インターポーザは、
    　スルービアの内側に形成された導体薄膜によって、電気抵抗値が約１Ωよりも大きいスルービアを実現すること
    　を特徴とするチップモジュール。     The chip module according to claim 1,
    The interposer is
    A chip module characterized by realizing a through via having an electrical resistance value greater than about 1Ω by a conductive thin film formed inside the through via.
  4. 　請求項３に記載のチップモジュールであって、
    　前記インターポーザは、ガラスコアを含み、
    　前記ガラスコアの上面および下面に、導体薄膜がさらに形成されていること
    　を特徴とするチップモジュール。     The chip module according to claim 3,
    The interposer includes a glass core;
    A chip module, wherein a conductive thin film is further formed on the upper and lower surfaces of the glass core.
  5. 　請求項１に記載のチップモジュールであって、
    　前記スルービアとコンデンサとが直列に接続されていること
    　を特徴とするチップモジュール。     The chip module according to claim 1,
    The chip module, wherein the through via and the capacitor are connected in series.
  6. 　請求項１に記載のチップモジュールであって、
    　前記スルービアが、前記インターポーザの隅と、外周縁沿いと、電気抵抗値が約１Ωよりも大きいスルービアではないスルービア間とのうち少なくとも１つに配置されること
    　を特徴とするチップモジュール。     The chip module according to claim 1,
    The chip module, wherein the through via is arranged at least one of a corner of the interposer, along an outer peripheral edge, and between through vias that are not through vias having an electric resistance value larger than about 1Ω.
  7. 　請求項１に記載のチップモジュールであって、
    　前記半導体チップと前記パッケージ基板との間に、Siインターポーザをさらに有し、
    　前記半導体チップは、前記インターポーザと前記Siインターポーザとの各々を介して、前記パッケージ基板と電気的に接続されること
    　を特徴するチップモジュール。     The chip module according to claim 1,
    Further comprising a Si interposer between the semiconductor chip and the package substrate,
    The chip module, wherein the semiconductor chip is electrically connected to the package substrate via each of the interposer and the Si interposer.
  8. 　請求項１乃至７のうちいずれか１つに記載のチップモジュールを１つ又は複数有する情報処理機器。 An information processing device having one or a plurality of chip modules according to any one of claims 1 to 7.
PCT/JP2015/064270 2014-06-10 2015-05-19 Chip module and information processing device WO2015190236A1 (en)

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