WO2015190236A1 - Module de puce et dispositif de traitement d'informations - Google Patents

Module de puce et dispositif de traitement d'informations Download PDF

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Publication number
WO2015190236A1
WO2015190236A1 PCT/JP2015/064270 JP2015064270W WO2015190236A1 WO 2015190236 A1 WO2015190236 A1 WO 2015190236A1 JP 2015064270 W JP2015064270 W JP 2015064270W WO 2015190236 A1 WO2015190236 A1 WO 2015190236A1
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Prior art keywords
interposer
chip module
tgv
glass
resonance
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PCT/JP2015/064270
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English (en)
Japanese (ja)
Inventor
仁博 遠山
植松　裕
智子 依田
大坂　英樹
敬 飯田
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株式会社日立製作所
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Publication of WO2015190236A1 publication Critical patent/WO2015190236A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to a chip module and information processing equipment.
  • the present invention claims the priority of Japanese Patent Application No. 2014-119565 filed on June 10, 2014, and for the designated countries where weaving by reference is allowed, the contents described in the application are as follows: Is incorporated into this application by reference.
  • Patent Document 1 (U.S. Pat. No. 2013/0119555) states that “a small electronic package, wherein a plurality of through vias have a wall in a glass interposer having a top, and a stress relaxation barrier is formed on the top of the glass interposer.
  • the plurality of metallization seed layers being at least part of the stress relaxation barrier, the conductor being at least part of the metallization seed layer and forming a plurality of metallized through package substrate vias; Through vias, and at least some of the through vias are filled with the stress relaxation layer or metallization seed layer (A microelectronic package comprising: a plurality of through vias having walls in a glass interposer having a top portion; a stress relief barrier on at least a portion of the top portion of the glass interposer; a metallization seed layer on at least a portion of the stress relief layer; and a conductor on at least a port of the portionofa the through vias forming a plurality of metalized through package vias, wherein at least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.
  • a glass interposer In a glass interposer, conductor layers are arranged on both sides of a glass core, and the upper and lower sides of the glass core are electrically connected by TGV (Trough Glass Via) penetrating the glass core. Because the loss of the glass core is small, the glass core part sandwiched between both sides works as a cavity resonator, and the electromagnetic field caused by the signal passing through the TGV and the current of the power supply / GND leaks into the core. Is excited, and there is a problem that signal quality and power supply characteristics deteriorate.
  • the present invention has been made in view of such circumstances, and an object thereof is to provide a technique for improving signal quality deterioration and power supply characteristic deterioration due to resonance generated in a glass interposer.
  • the present application includes a plurality of means for solving the above-described problems.
  • the chip module includes a semiconductor chip and an interposer, and the interposer has an electrical resistance value greater than about 1 ⁇ . Has through vias.
  • FIG. 1 is an example of a longitudinal sectional view of a chip module of Example 1.
  • FIG. It is an example of the cross-sectional view of a chip module.
  • the model for eigenmode analysis is shown. It is a comparison result of Q value in the model.
  • the relationship between the electrical resistance value of TGV and the Q value of the primary mode is shown.
  • the relationship between the electrical resistance value of TGV and the frequency of the primary mode is shown. It is a figure explaining an example of TGV formation.
  • FIG. 10 is an example of a vertical cross-sectional view of a chip module of Example 7. The relationship between the via resistance value of the ceramic interposer and the Q value of the primary mode is shown. The relationship between the via resistance value of a ceramic interposer and the frequency of a primary mode is shown.
  • FIG. 10 is an example of a longitudinal sectional view of a chip module according to an eighth embodiment. It is an example of the longitudinal cross-sectional view of the chip module of Example 9.
  • FIG. 1 is an example of a longitudinal sectional view of the chip module 100A of the first embodiment
  • FIG. 2 is an example of a transverse sectional view of the chip module 100A. More specifically, FIG. 2 is an example of a cross-sectional view taken along line AA in FIG. 1, and FIG. 1 is an example of a cross-sectional view taken along line BB in FIG.
  • the chip module includes a package substrate and a glass interposer, and one or more semiconductor chips are mounted on the glass interposer.
  • the semiconductor chip is, for example, LSI (Large Scale Integration) or IC (Integrated Circuit), but is not limited thereto.
  • the package substrate is not particularly limited as long as it can be electrically connected to the glass interposer via the electrode portion.
  • the package substrate is made of ceramic, but is not limited to this, and any other material such as an organic resin may be adopted.
  • the glass interposer includes a glass core formed of a glass-based material, has conductive planes on the upper and lower surfaces of the glass core, and includes at least one through via that connects the conductive planes. I just need it. Examples of the glass material include, but are not limited to, glass ceramics, borosilicate glass, quartz glass, and high silicate glass.
  • the chip module 100A is an example of a module in which an ASIC (Application Specific Integrated Circuit) and an optical IC are mounted on the same package substrate, but is not limited thereto.
  • the chip module 100A may be mounted with any semiconductor chip such as an IC other than an ASIC or an optical IC, or an LSI.
  • the ASIC may be, for example, an FPGA (Field-Programmable Gate Array), a CPU (Central Processing Unit), or a GPU (Graphics Processing Unit), and the optical IC may be, for example, a signal conditioner (electric signal relay LSI).
  • the chip module 100 ⁇ / b> A includes a glass interposer 5 and a package substrate 3. A glass interposer 5 is mounted on the upper surface of the package substrate 3.
  • Package board 3 includes via hole 9, conductor layer 10, and the like.
  • BGA All Grid Array
  • balls 8 are formed on the lower surface of the package substrate 3.
  • Each of the bumps 4-2 and 4-3 is formed on the upper surface of the glass interposer 5 (the surface not connected to the package substrate 3).
  • the glass interposer 5 and the ASIC 1 and the optical IC 2 are electrically connected by the bumps 4-2 and 4-3, respectively.
  • Bumps 4-1 are formed on the lower surface of glass interposer 5 (the surface connected to package substrate 3).
  • the package substrate 3 and the glass interposer 5 are electrically connected by bumps 4-1.
  • the glass interposer 5 includes at least a glass core 30 and a conductor layer 11.
  • the conductor layer 11 is disposed on each of the upper surface and the upper surface of the glass core 30.
  • Each of TGV6 and TGV7 is formed in the glass core 30.
  • TGV6 is formed by copper plating inside the through hole. Electrical connection between the upper and lower sides of the glass core 30 is established by the TGV 6. As a result, a high-density signal wiring between the ASIC 1 and the optical IC 2 is formed.
  • the treatment applied to the inside of the TGV 6 is not limited to copper plating, and any material or technique can be used.
  • the conductor layer 11 includes a wide plane to serve as a return plane for signal wiring. Therefore, the structure composed of the conductor layer 11 and the glass core 30 functions like a cavity resonator, and resonance noise is excited by a signal passing through the TGV 6 and a current change in the power supply / ground.
  • a broken line 20 in FIG. 1 schematically shows the electric field strength of resonance noise. As shown in the figure, the place connected by TGV6 is a node of resonance voltage.
  • TGV7 is formed by filling a through hole with a predetermined material.
  • the planes of the upper and lower conductor layers 11 of the glass core 30 are electrically connected by the TGV 7.
  • both ends of the TGV 7 are effective when placed at positions where the electric field strength is large and the antinodes of the noise voltage are present, but the present invention is not limited to this.
  • the position where the antinode of resonance is an intermediate point between the nodes, and the end of the glass core 30 also becomes the antinode of resonance. Therefore, as shown in FIG. 2, it is effective that the position where the TGV 7 is disposed is at least one of the corners of the glass core 30, along the outer peripheral edge of the glass core 30, and between the TGVs 6.
  • TGV7 is arranged between TGV6, it is preferable that the intermediate point between TGV6 or near the intermediate point.
  • the electrical resistance value of TGV7 needs to be higher than about 1 ⁇ in order to give a sufficient resonance damping effect.
  • an electric resistance value higher than about 1 ⁇ is realized by a predetermined material filled in the through hole.
  • the planes connected by the TGV 7 must have the same potential in terms of DC (Direct Current).
  • DC Direct Current
  • the case of the same potential in terms of DC is, for example, the case where both are ground planes or both are power supply planes.
  • the electrical resistance value of through vias such as TGV6 due to copper plating is almost much lower than about 1 ⁇ .
  • the electric resistance value is 10 m ⁇ or less. Therefore, TGV7 can be said to be a through via having a higher electrical resistance value than TGV6.
  • the numerical value such as “1 ⁇ ” here includes not only this number but also an error range caused by, for example, a model error or a measurement error.
  • FIG. 3 shows a model for eigenmode analysis.
  • the model 300 is obtained by bonding copper planes 50-1 and 50-2 on the upper and lower surfaces of the glass core 30 having a thickness of about 30 mm square and a thickness of about 100 ⁇ m.
  • the position that becomes the antinode of resonance is, for example, the positions 51 of the four corners of the plane.
  • the Q value representing the stability of resonance was obtained under each of the following three conditions 1 to 3. The lower the Q value, the faster the resonance attenuation.
  • Condition 1 Nothing is placed at position 51
  • Condition 2 TGV by copper plating is placed at position 51 and upper and lower copper planes 50-1 and 50-2 are electrically connected
  • Condition 3 From position 1 at about 1 ⁇ The upper and lower copper planes 50-1 and 50-2 are electrically connected by arranging a TGV having a higher electrical resistance value. Each TGV has a diameter of about 20 ⁇ m and a TGV having an electrical resistance value higher than about 1 ⁇ . The actual electric resistance value was set to 5 ⁇ per one.
  • FIG. 4 shows a comparison result of Q values in the model 300.
  • the graph 400 shows the Q value for each resonance from the primary mode to the tertiary mode for each of the above conditions 1 to 3.
  • the bar 401 in the first mode indicates the Q value in the condition 1
  • the bar 402 indicates the Q value in the condition 2
  • the bar 403 indicates the Q value in the condition 3.
  • the Q value is 1/6 or less.
  • the Q value reduction effect is recognized even under condition 2 (bar 402), it can be seen that the effect is small compared to condition 3 (bar 403).
  • FIG. 5 shows the relationship between the electrical resistance value of TGV and the Q value of the primary mode.
  • the horizontal axis of the graph 500 is the electrical resistance value of TGV, and the vertical axis is the Q value.
  • the Q value takes the lowest value in the vicinity of the electric resistance value of about 1 ⁇ to about 10 ⁇ .
  • the electrical resistance of the TGV is low, the resonance attenuation effect is small because the amount of resonance converted into thermal energy in the TGV is small.
  • the electrical resistance of the TGV is too high, no current flows through the TGV, so the attenuation effect is small.
  • the electrical resistance of TGV is extremely high (for example, about 1000 ⁇ or more), the resonance damping effect cannot be obtained, and it is more desirable to set the electrical resistance to about 100 ⁇ or less.
  • FIG. 6 shows the relationship between the electrical resistance value of TGV and the frequency of the primary mode.
  • the horizontal axis of the graph 600 is the electrical resistance value of TGV, and the vertical axis is the frequency.
  • the frequency is different between the low resistance side and the high resistance side, and transitions between about 1 ⁇ and about 10 ⁇ .
  • the frequency value on the high resistance side matches the frequency when TGV is not inserted, and the frequency value on the low resistance side is equal to the frequency when normal TGV is inserted. This indicates that if a through via of about 1 ⁇ or less is inserted, the position of the resonance antinode / node changes, while if a TGV greater than about 1 ⁇ to about 10 ⁇ is inserted, the resonance antinode -This means that the position of the clause does not change.
  • FIG. 7 is a diagram for explaining an example of TGV formation. In the figure, only the formation with respect to the glass core 30 will be described for simplification.
  • FIG. 7A shows only the glass core 30.
  • FIG. 7B shows an example in which a through hole 31-1 is provided in the glass core 30 with a laser or the like. Here, the through hole 31-1 is provided only at a position where the TGV 7 is formed.
  • FIG. 7C shows an example in which the through hole 31-1 is filled with a predetermined material. In this way, the TGV 7 having an electrical resistance value greater than 1 ⁇ is formed.
  • FIG. 7D shows an example in which a through hole 31-2 is provided in the glass core 30 with a laser or the like. Here, a through hole 31-2 is provided at a position where the TGV 6 is formed.
  • FIG. 7A shows only the glass core 30.
  • FIG. 7B shows an example in which a through hole 31-1 is provided in the glass core 30 with a laser or the like. Here, the through hole 31-1 is provided only at a position where the TGV 7 is formed.
  • FIG. 7C shows an example in which the through hole 31-1 is filled with a predetermined
  • FIG 7E shows an example in which copper plating is applied to the glass core 30 in which the through hole 31-2 is formed. Thereby, TGV6 is formed.
  • the conductor layer 11 can be formed simultaneously with the formation of the TGV 6 by this copper plating.
  • TGV formation is not limited to the above.
  • a through hole may be formed in a position where the TGV 6 or TGV 7 is provided in one process, and when filling the through hole, the through hole forming the TGV 6 may be masked.
  • FIG. 8 is an example of a longitudinal sectional view of the chip module 100B of the second embodiment
  • FIG. 9 is an example of a transverse sectional view of the chip module 100B. More specifically, FIG. 9 is an example of a cross-sectional view taken along line CC in FIG. 8, and FIG. 8 is an example of a cross-sectional view taken along line DD in FIG.
  • the difference between the first embodiment and the second embodiment is that a TGV composed of a conductive thin film and a resist is used in place of the TGV in which a through hole is filled with a predetermined material in order to realize a through via having an electric resistance larger than 1 ⁇ . It is a point to use. Since the electric resistance value of the conductor thin film is high, the same resonance attenuation effect as that in the above embodiment can be obtained.
  • the electrical resistance value of TGV13 is preferably greater than about 1 ⁇ as described above. Further, as described above, it is most effective to arrange the TGV 13 at the antinode of resonance as described above.
  • FIG. 10 is a diagram for explaining an example of TGV formation. In the figure, only the formation with respect to the glass core 30 will be described for simplification.
  • FIG. 10A shows only the glass core 30.
  • FIG. 10B is an example in which a through hole 31 is provided in the glass core 30 with a laser or the like. Here, the through hole 31 is provided at a position where the TGV 6 or TGV 13 is formed.
  • FIG. 10C shows an example in which the conductive thin film 32 is formed inside the through hole 31 by, for example, electroless plating. The conductor thin film 32 is formed with a thickness of about 1 ⁇ m or less using a conductor having a high resistivity such as a P—Ni alloy.
  • FIG. 10D shows an example in which a resist 33 is filled in the through hole 31 in which the conductive thin film 32 is formed at the position where the TGV 13 is formed.
  • TGV13 is formed.
  • photolithography Photolithography
  • FIG. 10E shows an example in which copper plating is applied to the glass core 30 on which the TGV 13 is formed.
  • copper plating is formed inside the through-hole 31 in which the conductive thin film 32 is formed but the resist 33 is not filled, and the TGV 6 and the conductor layer 11 are formed.
  • the TGV drilling process can be performed once without including the steps such as the mask described above.
  • the hollow portion of the TGV 13 is filled with a resist, but it may be left hollow.
  • the strength of the glass core 30 increases when the hollow portion is filled with a resist or the like.
  • FIG. 11 is an example of a longitudinal sectional view of the chip module 100C of the third embodiment.
  • the chip module 100C is provided with a capacitor 14 in the vicinity of the TGV 7, and the upper and lower planes of the glass core 30 are electrically connected through both the capacitor 14 and the TGV 7.
  • the upper and lower planes show an example of the conductor layer 11 in FIG. 11, the upper and lower planes are not limited to this.
  • FIG. 12 is an example of a circuit diagram showing a connection relationship.
  • the capacitor 14 is connected in series with the TGV 7 connected to the lower plane 43, and the tip is connected to the upper plane 42. That is, the two planes are electrically connected via the TGV 7 and the capacitor 14 connected in series.
  • the capacitor 14 is preferably a small size because of the mounting space.
  • An example of such a capacitor is a thin film capacitor, but is not limited thereto.
  • two planes may be connected in series via TGV13 and a capacitor. That is, it is only necessary that two planes can be connected in series via a TGV and a capacitor having an electrical resistance value greater than about 1 ⁇ .
  • FIG. 13 is an example of a longitudinal sectional view of the glass interposer of Example 4.
  • the chip module 100D of the present embodiment is different from the second embodiment in the range in which the conductor thin film 34 is provided.
  • the conductor thin film 34 is formed not only on the inside of the through hole but also on each of the upper and lower surfaces (for example, the surface 1301 and the surface 1302) of the glass core 30, and the copper plating 35 is applied thereon. A conductor layer is formed. Except for this point, the structure of the chip module 100D is the same as that of the chip module 100B.
  • the resonance noise attenuation effect can be obtained by the TGV having an electric resistance larger than about 1 ⁇ as in the above embodiment. Moreover, since the resonance noise current excited in the glass core is concentrated on the glass core 30 side of the upper and lower planes due to the skin effect, the conductive thin film 34 provided on the upper and lower surfaces of the glass core 30 also causes resonance noise. A damping effect is obtained. [Example 5]
  • FIG. 14 is an example of a longitudinal sectional view of the chip module 100E of Example 5, and FIG. 15 is an example of a transverse sectional view of the chip module 100E. More specifically, FIG. 15 is an example of a cross-sectional view taken along line EE in FIG. 14, and FIG. 14 is an example of a cross-sectional view taken along line FF in FIG.
  • a Si interposer 60 is further mounted on the package substrate 3 and the ASIC 1 is mounted across the Si interposer 60 and the glass interposer 5.
  • each glass interposer 5 has one IC 2 mounted thereon, and one chip module 100E includes a total of four optical ICs 2-1 to 2-4.
  • the Si interposer 60 is disposed at the center of the ceramic package substrate 3 or in the vicinity thereof, and the glass interposer 5 is disposed at least partially around the periphery. At least one ASIC 1 is disposed on the Si interposer 60. The ASIC 1 is disposed so as to straddle both the glass interposers 5-1 to 5-4 and the Si interposer 60. That is, the ASIC 1 is electrically connected to the package substrate 3 via each of the glass interposer 5 and the Si interposer 60.
  • the occupation range of the Si interposer 60 when the chip module 100E is viewed from above is included in the occupation range of the ASIC 1. Further, when the chip module 100E is viewed from above, the occupation range of the Si interposer 60 and the ASIC 1 is arranged so as to overlap a part of the occupation range of each of the four glass interposers 5-1 to 5-4. Further, when the chip module 100E is viewed from above, the occupation range of the Si interposer 60 and the ASIC 1 is arranged so as not to overlap with the occupation range of each IC 2 mounted on each of the glass interposers 5.
  • the ASIC 1 is provided with an electrode portion for high-speed signals for connecting to the glass interposer 5.
  • this electrode part is not limited, it is a pin, a bump, a lead, etc. (for example, bump 1401), for example, and is provided along the outer periphery of ASIC1 in this case.
  • the high-speed signal wiring is connected to each of the optical ICs 2-1 to 2-4 via each signal wiring (not shown) of the glass interposers 5-1 to 5-4. As described above, the high-speed signal can be transmitted through the low-loss glass interposer to suppress the deterioration of the signal quality.
  • the ASIC is provided with electrodes for low-speed signals and power supply / ground of the core circuit for connection with the Si interposer 60.
  • this electrode part is not limited, it is a pin, a bump, a lead, etc. (for example, bump 1402), for example, and is provided in the center vicinity of ASIC1 in this case.
  • This wiring is connected to the package substrate 3 through the through via 61 of the Si interposer 60. As described above, since power is supplied to the power source / ground of the core circuit having a large current through the Si interposer having a large loss, the problem of resonance noise can be made difficult to occur.
  • each of the glass interposers 5 includes any one of the configurations of the first to fourth embodiments described above.
  • FIG. 14 shows an example including TGV7 as in the first embodiment, but TGV13 may be used. In any of TGV7 and TGV13, the arrangement position is the same as in the above embodiment.
  • each glass interposer 5 may include a configuration of a different example among the above-described first to fourth examples. Thereby, as described above, the resonance on the glass interposer side can be attenuated.
  • FIG. 16 is a side view of the substrate portion of the information processing apparatus in which the chip module 100 is incorporated.
  • the information processing equipment here refers to a device that includes an arithmetic device such as an IC or LSI and that can execute a desired arithmetic operation.
  • the information processing apparatus 200 includes a plurality of chip modules 100, a plurality of motherboards 71, a plurality of connectors 72, a backplane board 73, an optical fiber 74, and the like. These numbers may be singular or plural and are not limited to those shown. However, efficient information processing can be performed by performing processing simultaneously by the plurality of chip modules 100 and the motherboard 71.
  • any one or a plurality of chip modules 100-1 to 100-3 of the first to fifth embodiments are mounted on each of the mother boards 71-1 to 71-3.
  • FIG. 16 shows an example in which the chip module 100E is mounted.
  • Each of the mother boards 71-1 to 71-3 is electrically connected to the backplane board 73 by connectors 72-1 to 72-3.
  • Optical fibers 74-1 and 74-2 are connected to the optical ICs mounted on each of the chip modules 100-1 to 100-3, and the chip modules 100-1 to 100-3 communicate with each other by optical signals. Is possible.
  • the chip modules 100-1 to 100-3 can have a broadband signal transmission capability by being mounted as described above.
  • high-speed optical signal transmission can be performed between the chip modules 100-1 to 100-3. Thereby, the information processing capability can be improved.
  • FIG. 17 is an example of a vertical cross-sectional view of the chip module 100F of the seventh embodiment.
  • the glass interposer is used as an object.
  • a resonance problem may also occur in a module using a substrate such as a low-loss ceramic.
  • via holes having high resistance are arranged in the ceramic interposer to suppress resonance between planes and avoid characteristic deterioration.
  • the ASIC 1 and the optical IC 2 are arranged on the upper surface of the ceramic interposer 300.
  • the ASIC 1 and the optical IC 2 are connected to the surface conductor layer 302 of the ceramic interposer 300 by bumps 4-2 and 4-3, respectively.
  • the ceramic interposer 300 is electrically connected to a printed circuit board or the like by BGA balls 8 arranged on the lower surface.
  • the ceramic interposer 300 has a structure in which ceramic substrates 305-1 to 305-5 and a conductor layer 302 are laminated. A wiring pattern and a power / GND plane are formed on the conductor layer 302. In order to electrically connect the upper and lower conductor layers 302 of the ceramic substrate 305, a via hole 303 having a low electrical resistance is disposed so as to penetrate the ceramic substrate 305.
  • a high-resistance via hole 304 is disposed at the antinode of the resonance voltage.
  • the via holes 304 are effective if they are arranged at the corners of the ceramic substrates 305-1 to 305-5 or along the outer periphery of the ceramic substrate.
  • the high-resistance via hole 304 needs to be 1 ⁇ or more as in the case of the glass interposer.
  • a model was prepared in which a GND plane was formed of silver on the upper and lower sides of a ceramic substrate having a size of 30 mm square and a thickness of 80 ⁇ m. And about the structure at the time of arrange
  • FIG. 18 shows the relationship between the via resistance value of the ceramic interposer and the Q value of the primary mode.
  • the horizontal axis of the graph 501 is the electrical resistance value of the via hole 304, and the vertical axis is the Q value of the primary mode.
  • the Q value takes the lowest value in the vicinity of 1 ⁇ to 10 ⁇ as in the case of the glass interposer.
  • FIG. 19 shows the relationship between the via resistance value of the ceramic interposer and the frequency of the primary mode.
  • the horizontal axis of the graph 601 is the electrical resistance value of the via hole 304, and the vertical axis is the frequency of the primary mode.
  • the resonance frequency changes between about 1 ⁇ and 10 ⁇ as in the case of the glass interposer. This indicates that when a via hole of 1 ⁇ or less is inserted, the position of the resonance antinode / node changes, whereas when a via hole larger than about 1 ⁇ to about 10 ⁇ is inserted, the resonance antinode -This means that the position of the clause does not change.
  • Example 7 an example in which ceramic is used as the substrate material is shown, but a low-loss resin base material or the like may be used.
  • FIG. 20 is an example of a longitudinal sectional view of the chip module 100G of the eighth embodiment.
  • the capacitor 306 is disposed on the upper surface of the ceramic interposer 300 with respect to the chip module 100F of the seventh embodiment.
  • a high resistance via hole 304 and a capacitor 306 are connected in series, and the upper and lower planes are connected via the capacitor 306. Connect.
  • the connection is made through the low resistance via hole 303.
  • the capacitor 306 is disposed on the upper surface of the ceramic interposer 300, but may be disposed on the lower surface. Further, a capacitor formed in the ceramic interposer 300 may be used as the capacitor.
  • FIG. 21 is an example of a vertical cross-sectional view of the chip module 100H of the ninth embodiment.
  • the chip module 100H according to the ninth embodiment has a buildup layer 307 capable of forming a narrow pitch wiring on the upper surface of the ceramic interposer 300 as compared with the chip modules 100F and 100G according to the seventh and eighth embodiments.
  • the build-up layer 307 normally uses a thin film such as polyimide as a dielectric material, but the material is not limited to this.
  • the build-up layer 307 connects the ASIC 1 and the optical IC 2 with a large number of wires by using finer wires than those in the ceramic interposer 300.
  • a capacitor 306 for assisting power supply is disposed as necessary.
  • the capacitor 306 is connected in series with the high resistance via hole 304 for suppressing the resonance of the ceramic substrates 305-1 to 305-5 in the same manner as in the eighth embodiment, and can suppress the resonance between the planes having different potentials.
  • the invention made by the present inventor has been specifically described based on an example.
  • the transmission throughput in the apparatus in order to improve the performance of the apparatus.
  • a transmission distance such as a signal conditioner or an optical module is extended.
  • a relay LSI is used.
  • the required throughput between computing devices and memories is increasing year by year as the computing devices (such as CPUs) become multi-core, and there is a technology for connecting them at high density. is necessary.
  • Another requirement is cost reduction.
  • the core material when glass is used as the core material, there is little deterioration of the signal waveform, so there is little attenuation of noise. Therefore, the planes on both sides of the core material act like a cavity resonator and cause characteristic deterioration. As a result, the power supply and the ground impedance are degraded, and the characteristics of the signal wiring penetrating the core material are degraded.
  • a TGV having an electric resistance value greater than about 1 ⁇ is provided on the glass core.
  • the resonance noise voltage generated in the glass core causes a current to flow when applied to both ends of the TGV.
  • the electromagnetic energy of the resonance noise is converted into heat energy, and the resonance noise can be efficiently attenuated.
  • the current flowing through the TGV is very small, the influence of the addition of the TGV on the position of the resonance antinode or node can be ignored. For this reason, unlike the case of adding a TGV that does not have an electrical resistance value greater than 1 ⁇ , once the resonance noise distribution is calculated, the TGV may be placed at the antinode position of the resonance based on the distribution. This makes it easy to design with countermeasures against resonance noise.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

　L'invention concerne une technique permettant d'améliorer la dégradation de la qualité du signal et la dégradation des caractéristiques d'alimentation électrique dues à la résonance survenant dans un élément d'interposition. Un module de puce comporte une puce de semi-conducteur et un élément d'interposition, et l'élément d'interposition a un trou d'interconnexion traversant ayant une valeur de résistance électrique en excès d'environ 1 Ω.
PCT/JP2015/064270 2014-06-10 2015-05-19 Module de puce et dispositif de traitement d'informations WO2015190236A1 (fr)

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JP2014-119565 2014-06-10
JP2014119565A JP2015233084A (ja) 2014-06-10 2014-06-10 チップモジュールおよび情報処理機器

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EP3482494A1 (fr) * 2016-07-05 2019-05-15 Raytheon Company Circuit intégré monolithique hyperfréquence (mmic) amplifié ayant une section de suppression des oscillations avec un trou d'interconnexion résistif

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JPH09246424A (ja) * 1996-03-14 1997-09-19 Fujitsu Ltd 半導体チップキャリヤ及びその製造方法
JPH1126907A (ja) * 1997-07-01 1999-01-29 Canon Inc プリント配線板および電子機器
JP2002353398A (ja) * 2001-05-25 2002-12-06 Nec Kyushu Ltd 半導体装置
JP2002359446A (ja) * 2001-05-31 2002-12-13 Hitachi Ltd 配線基板およびその製造方法
JP2006121086A (ja) * 2004-10-18 2006-05-11 E I Du Pont De Nemours & Co 容量性／抵抗性デバイス、有機誘電ラミネート、およびそのようなデバイスを組み込むプリント配線板、ならびにその作製の方法
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JP2009212309A (ja) * 2008-03-04 2009-09-17 Mitsubishi Electric Corp 半導体パッケージ
JP2010272585A (ja) * 2009-05-19 2010-12-02 Mitsubishi Electric Corp フリップチップ実装構造
WO2011030504A1 (fr) * 2009-09-11 2011-03-17 パナソニック株式会社 Corps ayant un composant électronique monté sur lui, procédé pour sa fabrication et interposeur
WO2012018415A1 (fr) * 2010-08-03 2012-02-09 Xilinx, Inc. Structure d'interconnexion verticale

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246424A (ja) * 1996-03-14 1997-09-19 Fujitsu Ltd 半導体チップキャリヤ及びその製造方法
JPH1126907A (ja) * 1997-07-01 1999-01-29 Canon Inc プリント配線板および電子機器
JP2002353398A (ja) * 2001-05-25 2002-12-06 Nec Kyushu Ltd 半導体装置
JP2002359446A (ja) * 2001-05-31 2002-12-13 Hitachi Ltd 配線基板およびその製造方法
JP2006121086A (ja) * 2004-10-18 2006-05-11 E I Du Pont De Nemours & Co 容量性／抵抗性デバイス、有機誘電ラミネート、およびそのようなデバイスを組み込むプリント配線板、ならびにその作製の方法
JP2007194400A (ja) * 2006-01-19 2007-08-02 Nec Corp 高周波パッケージ
JP2008270363A (ja) * 2007-04-17 2008-11-06 Mitsubishi Electric Corp 高周波パッケージ
JP2009212309A (ja) * 2008-03-04 2009-09-17 Mitsubishi Electric Corp 半導体パッケージ
JP2010272585A (ja) * 2009-05-19 2010-12-02 Mitsubishi Electric Corp フリップチップ実装構造
WO2011030504A1 (fr) * 2009-09-11 2011-03-17 パナソニック株式会社 Corps ayant un composant électronique monté sur lui, procédé pour sa fabrication et interposeur
WO2012018415A1 (fr) * 2010-08-03 2012-02-09 Xilinx, Inc. Structure d'interconnexion verticale

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