CN113727513B - Package substrate, printed circuit board, package device, and electronic apparatus - Google Patents
Package substrate, printed circuit board, package device, and electronic apparatus Download PDFInfo
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- CN113727513B CN113727513B CN202110848282.0A CN202110848282A CN113727513B CN 113727513 B CN113727513 B CN 113727513B CN 202110848282 A CN202110848282 A CN 202110848282A CN 113727513 B CN113727513 B CN 113727513B
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present disclosure provides a package substrate and an electronic device. The package substrate includes: the signal layer is provided with a first differential wire and a second differential wire, the first differential wire and the second differential wire are respectively and electrically connected with the first signal via hole and the second signal via hole so as to transmit positive and negative differential signals, a first filtering wiring is further arranged between the first differential wire and the second differential wire, the first filtering wiring is electrically connected with one opening end of the first common mode suppression via hole, the first common mode suppression via hole extends from the opening end and penetrates through at least one layer of the layers, and the other opening end is electrically connected with the ground layer or the power layer. The package substrate forms a common mode rejection structure by using the first filtering wiring and the first common mode rejection via, thereby realizing common mode rejection in a three-dimensional space.
Description
Technical Field
The present disclosure relates to semiconductor devices, and more particularly, to a package substrate, a printed circuit board, a package device, and an electronic apparatus.
Background
With the high-speed development of the modern electronic design field, the signal working speed is higher and higher, the differential signal is more and more widely applied in the high-speed circuit design, and in an actual circuit, the asymmetry of the differential signal is inevitably caused by factors such as the asymmetry of the rising edge and the falling edge of the signal, the difference of line length, etching change, proximity effect, routing bending and the like, so that common mode noise is generated. Common mode noise can cause problems with signal integrity in high speed circuitry. If the signal reaches the end of the signal in the circuit with the correct timing, duration and signal amplitude, it is stated that the system has good signal integrity. To address common mode noise, high speed circuitry typically designs common mode noise rejection structures to reject common mode noise without affecting the transmission of differential signals.
The differential signal is widely used in the packaging device (such as the packaging device 700 shown in fig. 7), and the existing common mode rejection structure is not suitable for being directly used in the packaging device (the packaging device has higher size requirement for the common mode rejection structure due to the trend of increasing miniaturization of the packaging device), so that it is necessary to design a more suitable common mode noise rejection structure for the packaging device.
Disclosure of Invention
In view of the above, it is an object of the present disclosure to provide a package substrate, a printed circuit board, a package device, and an electronic apparatus to apply an improved common mode noise suppressing structure.
According to a first aspect of embodiments of the present disclosure, there is provided a package substrate, including: a plurality of layers including a signal layer, a ground layer and a power layer, a first differential wire and a second differential wire being disposed on the signal layer, the first differential wire and the second differential wire being electrically connected with the first signal via and the second signal via, respectively, to transmit positive and negative differential signals,
and a first filtering wire is further arranged between the first differential wire and the second differential wire, the first filtering wire is electrically connected with an opening end of the first common mode rejection via hole, the first common mode rejection via hole extends from the opening end and penetrates through at least one layer of the layers, and the other opening end is electrically connected with the grounding layer or the power supply layer.
Optionally, the first filtering trace, the first differential conductor, and the second differential conductor are located on the same signal layer.
Optionally, the first signal via, the second signal via, and the first common mode rejection via are axisymmetric vias, respectively, and a center axis of the first signal via and a center axis of the second signal via are equal to a straight line distance of the center axis of the first common mode rejection via, respectively.
Optionally, the central axis of the first signal via, the central axis of the second signal via, and the point where the central axis of the first common mode rejection via intersects the signal layer are respectively on the same straight line.
Optionally, a second common mode rejection via is further disposed between the first signal via and the second signal via, an open end of the second common mode rejection via is located on the same layer as a corresponding open end of the first common mode rejection via, and the second common mode rejection via extends from the open end and passes through at least one layer of the plurality of layers and is electrically connected with the ground layer or the power layer;
the second common mode rejection via is an axisymmetric via, and the center axes of the first signal via and the second signal via are respectively equal to the straight line distance of the center axes of the second common mode rejection via.
Optionally, the second common mode rejection via is electrically connected with the first filtering trace.
Optionally, the package substrate further includes a second filtering trace, and the second common mode rejection via is electrically connected to the second filtering trace.
According to a second aspect of embodiments of the present disclosure, there is provided a packaged device comprising:
the package substrate;
a first connector on a first surface of the package substrate;
the chip assembly is provided with a plurality of chip modules,
the chip assembly is electrically connected with the first differential wire and the second differential wire through the first connecting piece.
Optionally, the package device further includes:
and a second connector on a second surface of the package substrate, the first surface being opposite to the second surface, the second connector being for electrical connection with an external printed circuit board.
According to a third aspect of embodiments of the present disclosure, there is provided an electronic device, comprising:
the package substrate;
a first connector on a first surface of the package substrate;
the chip assembly is electrically connected with the first differential wire and the second differential wire through the first connecting piece;
a printed circuit board;
and a second connector on a second surface of the package substrate for electrically connecting with the printed circuit board, the first surface being opposite to the second surface.
According to a fourth aspect of embodiments of the present disclosure, there is provided a printed circuit board comprising: a plurality of layers including a signal layer, a ground layer, and a power layer, on which a first differential wire and a second differential wire are disposed, the first differential wire and the second differential wire being electrically connected with the first signal via and the second signal via, respectively, the first differential wire and the first signal via being for transmitting a positive differential signal, the second differential wire and the second signal via being for transmitting a negative differential signal,
the first filtering wire is further arranged between the first differential wire and the second differential wire, the first common mode suppression via hole is further arranged between the first signal via hole and the second signal via hole, the first filtering wire is electrically connected with one opening end of the first common mode suppression via hole, and the other opening end of the first common mode suppression via hole is electrically connected with the ground layer or the power layer.
Optionally, a second common mode rejection via is further disposed between the first signal via and the second signal via, an open end of the second common mode rejection via is located on the same layer as a corresponding open end of the first common mode rejection via, and the second common mode rejection via extends from the open end and passes through at least one layer of the plurality of layers and is electrically connected with the ground layer or the power layer.
According to a fifth aspect of embodiments of the present disclosure, there is provided a method for common mode rejection at a package substrate, including:
before constructing the packaging substrate, determining the frequency range of noise to be filtered;
determining the length of a first filtering wire and the length of a first common mode rejection via according to the frequency range and the size information of the packaging substrate;
when the packaging substrate is constructed, the first filtering bus is constructed through metal patterning according to the length of the first filtering wiring, and the first common mode suppression via is constructed through drilling according to the length of the first common mode suppression via.
In summary, the package substrate provided in the embodiments of the present disclosure includes an improved common mode rejection structure. Because the common mode rejection structure realizes common mode rejection in three-dimensional space (i.e. three-dimensional space formed by the plane where the first filtering trace is located and the direction of the through hole of the first common mode rejection via hole), the length of the filtering trace and/or the length of the first common mode rejection via hole in the common mode rejection structure can be selected according to the frequency band range needing filtering, so that common mode rejection is realized.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing embodiments thereof with reference to the following drawings in which:
FIGS. 1 and 2 are perspective views of a package substrate according to an embodiment of the present disclosure;
FIG. 3 is a plan view of layer 122 of FIG. 1;
FIG. 4 is a schematic cross-sectional view of an exemplary first common mode rejection via;
FIG. 5a is an electric field diagram of common mode signal generation of a package substrate according to an embodiment of the present disclosure;
FIG. 5b is an electric field diagram of differential signal generation of a package substrate according to an embodiment of the present disclosure;
fig. 6 is a perspective view of a package substrate provided by another embodiment of the present disclosure;
fig. 7 is a schematic diagram of the structure of a packaged device 700;
FIG. 8 is a schematic illustration of the packaged device shown in FIG. 7 interconnected with another substrate 707;
fig. 9 is a more detailed schematic diagram of an electronic device.
Reference numerals:
121: a first planar layer; 122-126: second to sixth planar layers; 127-132: seventh to tenth planar layers; 104: a first differential conductor; 105: a second differential conductor; 106: a first filtering trace; point A: an end point of the first filtering wire; 107: a first signal via; 108: a second signal via; 109: a first common mode rejection via; l: the distance between the endpoint a and the first open end of the first common mode rejection via;
Detailed Description
The present disclosure is described below based on embodiments, but the present disclosure is not limited to only these embodiments. In the following detailed description of the present disclosure, certain specific details are set forth in detail. The present disclosure may be fully understood by one skilled in the art without a description of these details. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the disclosure. The figures are not necessarily drawn to scale.
The following terms are referred to herein.
Differential signal: differential transmission is a signal transmission technology, and is different from the conventional method of one signal line and one ground line, and the differential transmission transmits signals on the two lines, wherein the amplitudes of the two signals are the same, and the phases of the two signals are opposite. The transmitted signals on these two wires are differential signals.
Differential line: two transmission lines having equal lengths and being coupled in parallel are used to transmit differential signals (signals 180 degrees out of phase).
Differential signal: if the polarity of the signals is opposite (and likewise the direction of the current is opposite) as seen from a pair of inputs of a system, such signals are differential signals.
Common mode signal: if the polarity of the signals is the same (and the direction of the current is the same) as seen from a pair of inputs of a system, such signals are referred to as common mode signals. The common mode signal present in differential signal transmission is also referred to as common mode noise.
Electromagnetic interference: refers to any electromagnetic phenomenon that is caused by conduction or electromagnetic field with the action of voltage and current, and can reduce the performance of a device, equipment or system or can adversely affect organisms or substances.
Common mode filter: the design is relatively simple, including common mode capacitance, unbalanced transformers or common mode inductances. The common mode capacitor bypasses the common mode current of the two input lines to ground, and the common mode inductor presents a balanced impedance, that is, the impedance in the power line and the ground line are equal, and the impedance presents impedance characteristics to common mode noise.
Fig. 1 and 2 are perspective views illustrating a package substrate according to an embodiment of the present disclosure. The package substrate 100 includes a plurality of layers including, as an example, layers 121 to 132. The layers 121 to 132 include an insulating layer, a ground layer, a signal layer, a power supply layer, and the like, and each layer is generally made of a conductive material or an insulating material, for example, the signal layer is made of a conductive metal such as copper foil, and the ground layer is made of an insulating material. Electrical interconnection between the different layers is achieved using vias. The via hole is a hole realized by adopting a mode of copper electroplating hole filling or copper electroplating convex point after laser drilling.
As shown in fig. 1 and 2, the package substrate 100 further includes a first differential wire 104, a second differential wire 105, a first filter trace 106, a first signal via 107, a second signal via 108, and a first common mode rejection via 109. The first differential wire 104 and the second differential wire 105 are arranged in parallel in the signal layer, the first differential wire 104 is electrically connected to the first signal via 107, and the second differential wire 105 is electrically connected to the second signal via 108. The first signal via 107 is electrically connected to an external circuit after extending from the signal layer through several layers. The second signal vias 108, after extending from the signal layer through several layers, are also electrically connected to external circuitry. The external circuit is, for example, an external PCB (Printed Circuit Board ) or an external chip module (die).
Thus, the first differential conductor 104, the second differential conductor 105, the first signal via 107, and the second signal via 108 constitute a transmission line that transmits differential signals. The differential signals come from external circuitry, such as external PCBs (Printed Circuit Board, printed circuit boards) or external chip assemblies (die) that are electrically connected from the package substrate 100. As already described above, the vias may be implemented by means of copper-filled or copper-bumped plating after laser drilling, so that for the first signal via 107 and the second signal via 108, it is understood that the inner wall has a conductive material and is insulated from the surrounding respective materials, so that the differential signal can be transferred through the first signal via 107 and the second signal via 108.
The first filter wire 106 is disposed between the first differential wire 104 and the second differential wire 105, and the first filter wire 106 and the first differential wire 104 and the second differential wire 105 may be disposed in the same layer, that is, the first filter wire 106 is disposed in the signal layer. The first filter trace 106 extends from point a to electrically connect with the first open end of the first common mode rejection via 109, where L represents the distance between point a and the first open end B of the first common mode rejection via 109. The first open end of the first common mode rejection via 109 may be understood as the portion of the first common mode rejection via 109 intersecting the planar layer where the first filter trace 106 is located. A first common mode rejection via 109 is disposed between the first signal via 107 and the second signal via 108, the first common mode rejection via 109 extending from the first open end through several layers, reaching the second open end and electrically connected to the ground layer or the power layer. The second open end of the first common mode rejection via 109 may be understood as the portion of the first common mode rejection via 109 that intersects the ground layer or the power layer. The first common mode rejection via 109 is a hole having a conductive material on the inner wall, and the first common mode rejection via 109 should be insulated from the layers through which it passes so that the common mode signal can be transferred to the ground layer or the power layer via the first common mode rejection via 109.
In some embodiments, the first signal via 107, the second signal via 108, and the first common mode rejection via 109 are axisymmetric vias (e.g., are all cylindrical vias) and are all perpendicular to the signal layer, and the center axis of the first signal via 107 and the center axis of the second signal via 108 are each equidistant from the center axis of the first common mode rejection via 109. Also optionally, the center axis of the first signal via 107, the center axis of the second signal via 108, and the point at which the center axis of the first common mode rejection via 109 intersects the signal layer are on the same straight line.
In some embodiments, the spacing of the first differential conductor 104 and the second differential conductor 105 widens near the first signal via 107 and the second signal via 108 to provide space for the first signal via 107 and the second signal via 108 and the first common mode rejection via 109, avoid interaction when drilling, and even cause the positions of the first signal via 107, the second signal via 108 and the first common mode rejection via 109 to coincide.
It should be appreciated that the transmission lines formed by the first differential conductor 104, the second differential conductor 105, the first signal via 107 and the second signal via 108 not only transmit differential signals, but also transmit common mode signals (i.e., common mode noise). And the common mode rejection structure composed of the first filter trace 106 and the first common mode rejection via 109 can reject the common mode signal while preserving the differential signal. In addition, since the common mode rejection structure realizes common mode rejection in three-dimensional space (i.e. three-dimensional space formed by the plane where the first filtering trace 106 is located and the direction of the through hole of the first common mode rejection via hole 109), the length of the filtering trace 106 and/or the length of the first common mode rejection via hole 109 in the common mode rejection structure can be selected and adjusted according to the frequency range of filtering to realize common mode rejection.
Illustrating how the length of the filter tracks 106 and/or the length of the first common mode rejection vias 109 in the common mode rejection structure may be adjusted to achieve common mode rejection according to the frequency range of the desired filtering. In order to realize the 3dB filtering frequency band of 22.55GHz-27.24GHz (i.e., 4.69GHz broadband common mode filtering), the sum of the length of the filtering trace 106 and the length of the first common mode rejection via 109 is required to be approximately 0.8mm, and then the length of the filtering trace 106 and the length of the first common mode rejection via 109 are respectively determined according to the product size requirement.
It should be noted that if a via passes through from the first layer to the last layer, it is a via. If the via extends from the first layer but stops in the middle layer, it is a blind via. If a via starts from one intermediate layer and stops at another intermediate layer, it is referred to as a buried via. In the present embodiment, as shown in the figure, the layer 121 is the first layer of the package substrate 100, the layer 132 is the last layer of the package substrate 100, the first signal via 107 and the second signal via 108 are blind vias, and the first common mode rejection via 109 is a buried via, but in the present embodiment, the three vias may be any one of a through via, a blind via, and a buried via as long as the requirement can be satisfied.
Fig. 3 is a plan view of layer 122 in fig. 1.
Thus in this embodiment, as a preferred embodiment, the common mode suppresses the via 109, i.e. the central symmetry plane between virtual planes 301 and 302.
The first filter track 106 is located between the first differential conductor 104 and the second differential conductor 105. When the first differential conductor 104 and the second differential conductor 105 are symmetrical with respect to the first filter track 106, the first filter track 106 has the best suppression effect on the common mode signal. The virtual plane 300 may be regarded as a virtual plane in which the central axis of the first filtering bus 106 extends vertically in the direction of the respective layers of the package substrate. When the first differential wire 104 and the second differential wire 105 are symmetrical with respect to the first filter track 106, i.e. the first differential wire 104 and the second differential wire 105 are symmetrical with respect to the virtual plane 300. Since the first filter trace 106 is located on the same layer as the first differential conductive line 104 and the second differential conductive line 105, for example, the first filter trace 106 and the first differential conductive line 104 and the second differential conductive line 105 are located in the layer 122, i.e. the signal layer in the figure, but this is not necessarily the case in the embodiment of the disclosure, for example, the first filter trace 106 may be located on a layer other than the signal layer 122, for example, the first differential conductive line 104 and the second differential conductive line 105 are located on the layer 122, and the first filter trace 106 is located on the layer 124, in which case the first common mode rejection via 109 electrically connected to the first filter bus 106 will extend from the layer 124.
The virtual planes 301 and 302 are virtual planes extending in the vertical direction of the package substrate along a dividing line parallel to the central axis of the first filter trace 106. As shown in the reference figures, the second signal via 108 and the first signal via 107 are symmetrical about virtual planes 301 and 302, respectively.
Fig. 4 is a schematic cross-sectional view of an exemplary first common mode rejection via. As shown in the figure, the thickness of the package substrate 100 is H. The length (along the direction of the hole) of the first common mode rejection via 109 is H1, which is smaller than the thickness of the package substrate 100. Various embodiments may be employed to obtain a first common mode rejection via. In one embodiment, drilling is started at a proper position on the lower surface of the package substrate 100 (a proper position is determined according to the positions of the second signal via hole and the first signal via hole) to obtain a grounding hole with a length of h1+h2. The conductive material (e.g., copper layer) of the inner wall surface of the portion of the hole of length H2 is then ground away so that the ground via portion of the ground inner wall has no conductive effect. At this time, the conductive material remains in the inner wall of only the portion of the ground via having the length H1 as shown in the drawing, and the portion having the length H1 is the first common mode rejection via 109. In another embodiment, if the lower surface of the package substrate 100 is a ground layer or a power layer, drilling may be performed from a proper position on the upper surface of the package substrate 100) until the lower surface, that is, a ground hole with a length H is obtained, and then the ground hole is used as the first common mode rejection via 109. The length H1 of the first common mode rejection via 109 may be determined according to the frequency band of the common mode signal to be rejected and in combination with the length L of the first filtering trace.
Fig. 5a is an electric field diagram of common mode signal generation of a package substrate according to an embodiment of the present disclosure. Fig. 5b is an electric field diagram of differential signal generation of a package substrate according to an embodiment of the disclosure.
When the transmission line constituted by the first differential conductor 104, the second differential conductor 105, the first signal via 107 and the second signal via 108 transmits a common mode signal, the electric field distribution formed by the common mode signal is as shown in fig. 5 a. Since the common mode signals are equal in size and in the same direction, the direction of the generated electric field is from the signal vias (e.g., first signal via 107, second signal via 108) and the differential conductors (e.g., first differential conductor 104, second differential conductor 105) to the virtual plane 300. Since the common mode suppressing structure composed of the first filter wiring 106 and the first common mode suppressing via 109 forms a resonant circuit, thereby exciting the resonance characteristic of the common mode signal, the common mode signal in the transmission line composed of the first differential wire 104, the second differential wire 105, the first signal via 107, and the second signal via 108 can be suppressed.
In order for the first common mode rejection via 109 and the first filter trace 106 to be located in the electric field formed by the common mode signal, the position of the first filter trace 106 on the plane needs to match the positions of the first differential conductor 104, the second differential conductor 105, specifically, the first filter trace 106 is on the centerline between the first differential conductor 104 and the second differential conductor 105.
While the extension of the first common mode rejection via 109 in the vertical direction matches the first signal via 107 and the second signal via 108, in particular the first signal via 107 and the second signal via 108 are symmetrical with respect to a virtual plane 300 along the first common mode rejection via 109.
When a differential signal is transmitted by a transmission line constituted by the first differential conductor 104, the second differential conductor 105, the first signal via 107 and the second signal via 108, the electric field distribution formed by the differential signal is as shown in fig. 5 b.
Since the differential signals are equal in size and opposite in direction, a plane with zero potential, i.e., a virtual ground plane, is formed on the central symmetry plane (i.e., virtual plane 300) of the first signal via 107 and the second signal via 108. When the first common mode rejection via 109 and the first filtering trace 106 are located in the virtual plane 300, they are electrically equivalent to being connected to a ground plane, and thus do not affect the differential signal while rejecting the common mode signal.
Fig. 6 is a perspective view of a package substrate provided in another embodiment of the present disclosure. The package substrate is deformed from the package substrate shown in fig. 1 and 2 (each layer is omitted in the figures). As can be seen, the package substrate adds a second common mode rejection via 110, the second common mode rejection via 110 being located on the central symmetry plane 300 between the first signal via 107 and the second signal via 108 as the first common mode rejection via 109. The second common mode rejection via 110 is also suspended at one end and electrically connected to the ground plane as is the first common mode rejection via 109. The common mode rejection structure consisting of the second common mode rejection via 110 and the first common mode rejection via 109 and the first filter trace 106 may achieve common mode rejection.
Alternatively, the first and second common mode rejection vias 109 and 110 are disposed on both sides of and symmetrical about a virtual plane. The virtual plane is a plane formed through the central axis of the first signal via and the central axis of the second signal via.
An embodiment variant may be added further on the basis of fig. 6. In fig. 6, the second common mode rejection via 110 is not electrically connected to one filter trace, but in a variation of this embodiment, the second common mode rejection via 110 may be electrically connected to the second filter trace, thereby forming two sets of common mode rejection structures to achieve common mode rejection.
Fig. 7 is a schematic diagram of the structure of a packaged device 700. The packaged device 700 includes a substrate 703 and a chip 701 disposed over the substrate 703.
The substrate 703 may be the package substrate mentioned above. The basic type may be plastic packaging, ceramic, carrier tape, etc. The plastic package substrate is a PCB substrate material (BT resin/glass laminate). The ceramic substrate is a multilayer ceramic wiring substrate. The carrier tape substrate type is a PI multilayer wiring substrate. Different substrates need to be built based on different manufacturing processes. And on the built substrate, it is also necessary to build the differential wires, differential vias and common mode rejection vias as mentioned in the above embodiments, so that the package substrate achieving common mode rejection as mentioned in the above embodiments can be finally obtained.
The substrate 703 further includes first connectors for electrical connection to external circuitry, such as pads 705 and solder balls 704 interconnected with the pads 705. A plurality of pads 705 are provided on the bottom surface of the substrate 703, and then a plurality of solder balls 704 are provided in correspondence with the plurality of pads 705. The arrangement of the bonding pads and the solder balls can be determined at will. The current arrangement of bonding pads and solder balls is generally of the peripheral, staggered and full array type. The peripheral type is a type in which solder balls 704 are provided on the periphery of the bottom surface of the substrate 703, and for example, a plurality of rows of solder balls 704 may be provided near four sides. The staggered type means that solder balls are simultaneously disposed at the center position and the peripheral position of the bottom surface of the substrate 703. The full array type means that the solder balls 704 are uniformly disposed on the bottom surface of the substrate 703.
The substrate 703 further comprises a second connection member for electrical connection with an external circuit, such as a second connection member 702 provided on the top surface of the substrate 703. The chip 701 disposed on the substrate 703 is typically a chip assembly (die) and is electrically connected to the chip assembly (die) using the second connection 702.
In one specific manufacturing process, the substrate 703 is first prepared and then the chip 701 is mounted to the substrate 703 using a chip bonding process. The conventional back-off bonding (Filp Chip on Board) is to make various micro solder bumps on the periphery of the chip and connect with corresponding pads on the top surface of the substrate 703, and if the solder bumps are disposed on the whole surface of the chip, the back-off bonding is specifically called C4 method (Controlled Collapsed Chip Connection). A wire bonding process is then used to connect the lands on the die 701 to the lands on the substrate 703. A mold package process is then used to mold the package to protect the chip 701, leads, and lands. Finally, the solder balls are assembled by placing solder-immersed solder balls 704 on pads 705 using specially designed tools (e.g., a solder ball pick-and-place machine), and reflow is performed in a reflow oven so that the solder balls and pads 705 on the substrate are soldered together. Finally, BGA structure 700 with solder balls 704 is attached to pads 706 by mounting, so that BGA structure 700 is attached to substrate 707. Reference is made only to substrate preparation, die attach, wire bonding, molded packaging, solder ball assembly, solder reflow, but in practice some non-mentioned steps are included in the fabrication process of the packaged device 700, but are not described here because they are not germane to the embodiments of the present disclosure. Of course, these manufacturing processes are optional and can be adjusted according to practical needs.
Fig. 8 is a schematic illustration of the packaged device shown in fig. 7 interconnected with another substrate 707. As shown in the figures, the substrate 707 is a printed circuit board, but the board may also include differential conductors, differential vias, and common mode rejection vias as mentioned in the embodiments above to achieve common mode rejection. In other words, the above embodiments can also be applied to a printed circuit board.
Fig. 9 is a more detailed schematic diagram of an electronic device. As shown in the drawing, the electronic device provides a motherboard 1000, and various components are provided on the motherboard 1000. Motherboard 1000 is, for example, a printed circuit board. The motherboard 1000 carries various components including, but not limited to, a central processor 1002, a graphics processor 1003, a dynamic random access memory 1004, a graphics card 1005, a static random access memory 1010, a flash memory 1006, a GPS chip 1008, and the like. These components are physically and electrically coupled to motherboard 1000. Motherboard 1000 provides communication functionality between the various components. In further embodiments, for example, the functionality of some of the components may be integrated in a processor, e.g., dynamic random access memory 1004, static random access memory 1010 may be integrated in a system-on-a-chip and as processor 1002 in the present embodiment.
The central processor is derived from a conventional computer system and is the processor that acts as a master control and scheduling. Central processing units are very efficient in terms of logic control, but often suffer from deficiencies in terms of specificity, so they are sometimes integrated with various specialized acceleration units, e.g., acceleration units dedicated to neural network model computation, graphics processors that are more efficient in terms of graphics processing, etc. In this embodiment, the central processor 1002 and the graphic processor 1003 are integrated in the same electronic device through the motherboard 1000.
The communication chip enables wireless communication to facilitate the transfer of data to and from the electronic device 10. The term "wireless" does not mean that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), wiMAX (IEEE 802.16 series), IEEE 802.20, long Term Evolution (LTE), ev-DO, hspa+, hsdpa+, hsupa+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, bluetooth, derivatives thereof, and any other wireless protocol designated 3G, 4G, 5G, and above. Since there are many different communication protocols, a separate communication chip can be built based on each communication protocol. For example, the motherboard 1000 is provided with a GPS chip 1008 and a bluetooth chip 1007, and the motherboard 1000 is provided with a plurality of chips dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, wiMAX, LTE, ev-DO. In addition, other functions, such as video codec 1009, a compass, various component drivers, etc., may also form various components and be integrated into electronic device 10 through motherboard 1000.
In addition, some components are included in the electronic device that are not integrated into the device 10 through the motherboard 1000, such as a sound card 1011, a keyboard 1012, a network card 1014, and a mouse 1013. These components provide input and output functions for the device 10.
Based on the package substrate or the device, the disclosure also provides a method for common mode rejection. Before constructing a packaging substrate or a packaging device, determining the frequency range of noise to be filtered, then determining the length of a first filtering wire and the length of a first common mode suppression via according to the frequency range of the noise to be filtered and the size information of the packaging substrate or the packaging device, and when constructing the packaging substrate or the packaging device, constructing a first filtering bus through metal patterning according to the length of the first filtering wire and constructing the first common mode suppression via through drilling. By the method, the lengths of the filter bus and the common mode rejection via for common mode rejection are determined in three-dimensional space when the package substrate or the device is constructed, and thus the filter bus and the common mode rejection via have more adjustable size space.
Commercial value of embodiments of the present disclosure
The package substrate and the printed circuit board provided by the embodiment of the disclosure realize common mode suppression through the combined action of the filter wiring and the common mode suppression via hole. The product process improvement can enhance the stability of the corresponding product in terms of electrical performance, and therefore has use value and economic value.
Any combination of one or more computer readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium is, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer readable storage medium include the following: in particular, the electrical connection of one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical memory, a magnetic memory, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with a processing unit, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a notch. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any other suitable combination. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.
Computer program code for carrying out embodiments of the present disclosure may be written in one or more programming languages or combinations. The programming languages include object oriented programming languages such as JAVA, c++, and may also include conventional procedural programming languages such as C. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Claims (9)
1. A package substrate, comprising: a plurality of layers including a signal layer, a ground layer and a power layer, a first differential wire and a second differential wire being disposed on the signal layer, the first differential wire and the second differential wire being electrically connected with the first signal via and the second signal via, respectively, to transmit positive and negative differential signals,
a first filtering wire is further arranged between the first differential wire and the second differential wire, wherein the first filtering wire, the first differential wire and the second differential wire are positioned on the same signal layer, the first differential wire and the second differential wire are symmetrical with respect to the first filtering wire, a first common mode suppression via hole is further arranged between the first signal via hole and the second signal via hole, the first filtering wire is electrically connected with one opening end of the first common mode suppression via hole, the first common mode suppression via hole extends from the opening end and penetrates through at least one layer of the layers, the other opening end is electrically connected with the ground layer or the power layer, and the length of the first filtering wire and the length of the first common mode suppression via hole are determined according to the frequency range of noise to be filtered and the size information of the packaging substrate or the packaging device;
the first signal via hole, the second signal via hole and the first common mode inhibition via hole are axisymmetric via holes respectively, the central axes of the first signal via hole and the central axes of the second signal via hole are respectively equal to the straight line distance of the central axes of the first common mode inhibition via hole, and the central axes of the first signal via hole, the central axes of the second signal via hole and the central axes of the first common mode inhibition via hole are respectively located on the same straight line when the central axes of the first signal via hole, the second signal via hole and the first common mode inhibition via hole intersect with the signal layer.
2. The package substrate of claim 1, wherein a second common mode rejection via is further provided between the first and second signal vias, an open end of the second common mode rejection via being in a same layer as a corresponding open end of the first common mode rejection via, the second common mode rejection via extending from the open end and through at least one of the plurality of layers, electrically connected to the ground or power plane;
the second common mode rejection via is an axisymmetric via, and the center axes of the first signal via and the second signal via are respectively equal to the straight line distance of the center axes of the second common mode rejection via.
3. The package substrate of claim 2, wherein the second common mode rejection via is electrically connected with the first filter trace.
4. The package substrate of claim 2, wherein the package substrate further comprises a second filter trace, the second common mode rejection via being electrically connected with the second filter trace.
5. A packaged device, comprising:
the package substrate of any one of claims 1 to 4;
a first connector on a first surface of the package substrate;
the chip assembly is provided with a plurality of chip modules,
the chip assembly is electrically connected with the first differential wire and the second differential wire through the first connecting piece.
6. The packaged device of claim 5, further comprising:
and a second connector on a second surface of the package substrate, the first surface being opposite to the second surface, the second connector being for electrical connection with an external printed circuit board.
7. An electronic device, comprising:
the package substrate of any one of claims 1 to 4;
a first connector on a first surface of the package substrate;
the chip assembly is electrically connected with the first differential wire and the second differential wire through the first connecting piece;
a printed circuit board;
and a second connector on a second surface of the package substrate for electrically connecting with the printed circuit board, the first surface being opposite to the second surface.
8. A printed circuit board, comprising: a plurality of layers including a signal layer, a ground layer, and a power layer, on which a first differential wire and a second differential wire are disposed, the first differential wire and the second differential wire being electrically connected with a first signal via and a second signal via, respectively, the first differential wire and the first signal via being for transmitting a positive differential signal, the second differential wire and the second signal via being for transmitting a negative differential signal,
a first filtering wire is further arranged between the first differential wire and the second differential wire, wherein the first filtering wire, the first differential wire and the second differential wire are positioned on the same signal layer, the first differential wire and the second differential wire are symmetrical with respect to the first filtering wire, a first common mode suppression via hole is further arranged between the first signal via hole and the second signal via hole, the first filtering wire is electrically connected with one opening end of the first common mode suppression via hole, the other opening end of the first common mode suppression via hole is electrically connected with the ground layer or the power layer, and the length of the first filtering wire and the length of the first common mode suppression via hole are determined according to the frequency range of noise to be filtered and the size information of a packaging substrate or a packaging device;
the first signal via hole, the second signal via hole and the first common mode inhibition via hole are axisymmetric via holes respectively, the central axes of the first signal via hole and the central axes of the second signal via hole are respectively equal to the straight line distance of the central axes of the first common mode inhibition via hole, and the central axes of the first signal via hole, the central axes of the second signal via hole and the central axes of the first common mode inhibition via hole are respectively located on the same straight line when the central axes of the first signal via hole, the second signal via hole and the first common mode inhibition via hole intersect with the signal layer.
9. The printed circuit board of claim 8, wherein a second common mode rejection via is further disposed between the first and second signal vias, an open end of the second common mode rejection via being on a same layer as a corresponding open end of the first common mode rejection via, the second common mode rejection via extending from the open end and through at least one of the plurality of layers, electrically connected to the ground or power plane.
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| CN118120052A (en) * | 2022-08-26 | 2024-05-31 | 京东方科技集团股份有限公司 | Packaging substrate and preparation method thereof, functional substrate and preparation method thereof |
| TWI838067B (en) * | 2023-01-06 | 2024-04-01 | 創意電子股份有限公司 | Interposer routing structure and semiconductor package |
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