CN110719690A - High speed multi-layer PCB stack and routing method - Google Patents
High speed multi-layer PCB stack and routing method Download PDFInfo
- Publication number
- CN110719690A CN110719690A CN201911010663.0A CN201911010663A CN110719690A CN 110719690 A CN110719690 A CN 110719690A CN 201911010663 A CN201911010663 A CN 201911010663A CN 110719690 A CN110719690 A CN 110719690A
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- layer
- speed
- hole
- signal
- signal line
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
Abstract
The invention discloses a high-speed multilayer PCB (printed circuit board) laminating and wiring method, wherein the PCB comprises a TOP layer, a GND layer, a Signal layer, a POWER layer and a BOTTOM layer, wherein a substrate is made of a high-speed plate; the upper layer and the lower layer of each Signal layer are GND layers; a component is arranged on the TOP layer BOTTOM layer, a through hole electrically connected with the Signal layer is arranged at a pad of the component, and the pad is electrically connected with the through hole; when the high-speed signal line is wired, an anti-bonding pad is arranged at the routing punching hole and used for increasing the impedance of the via hole so as to enable the via hole to be matched with the impedance of the high-speed signal line; the AC coupling capacitor needs to be subjected to adjacent layer hollowing treatment. The upper reference ground plane and the lower reference ground plane of the signal layer can reduce signal loss, effectively inhibit crosstalk between signals and simulate impedance matching. Each high-speed differential signal line is provided with 4N inflection points, N sections are arranged on the inner layer and the outer layer of each high-speed differential signal line, so that the length of two signals of each group of differential signal lines is ensured to be the same, and the impedance matching of the differential signal lines is improved.
Description
Technical Field
The invention relates to the field of PCB design and manufacture, in particular to a high-speed multilayer PCB lamination and a wiring method.
Background
The demand of the modern market for communication system products further develops towards high integration, high speed and microminiaturization, the working frequency of the chip is increased by moore's law, and instead, the packaging size of the chip is required to be smaller, and a super-large-scale circuit becomes the mainstream of chip development, which inevitably requires a PCB board with higher density and higher speed.
It is known that the transmission quality of signals on a PCB directly affects whether the performance of PCB products meets design requirements, and there are strict requirements on the impedance of signals in high-speed PCB design, so how to control the impedance of high-speed PCB signals becomes an important issue in the research of PCB design nowadays.
The existing PCB laminated arrangement is not reasonable enough, and the crosstalk between signals is difficult to be effectively inhibited.
Disclosure of Invention
The present invention is to solve the above-mentioned deficiencies of the prior art and to provide a high-speed multi-layer PCB stack and a wiring method.
In order to solve the technical problems, the invention adopts the technical scheme that: a high-speed multilayer PCB board lamination and wiring method, the PCB board includes TOP layer, GND layer, Signal layer, POWER layer and BOTTOM layer, wherein the base plate adopts the high-speed board; the upper layer and the lower layer of each Signal layer are GND layers; a component is arranged on the TOP layer BOTTOM layer, a through hole electrically connected with the Signal layer is arranged at a pad of the component, and the pad is electrically connected with the through hole; when the high-speed signal line is wired, an anti-bonding pad is arranged at the routing punching hole and used for increasing the impedance of the via hole so as to enable the via hole to be matched with the impedance of the high-speed signal line; the AC coupling capacitor needs to be subjected to adjacent layer hollowing treatment.
Furthermore, the high-speed Signal line adopts the through hole to trade the layer, carries out the back drilling to the through hole of transmission high-speed Signal line from the bottom and handles, and the length of the stake that is connected with the Signal layer after the back drilling is less than or equal to 10mil, and the length of this stake is the distance of Signal layer to back drilling top department.
Further, during high-speed differential Signal wiring, 4N inflection points with chamfers are arranged on a line segment, located on the Signal layer, of each differential Signal line, wherein N is a natural number, the differential Signal lines are bent by 90 degrees through each inflection point, and the length and the angle of each chamfer are the same.
Furthermore, ground holes are arranged at the via holes when the high-speed differential signal lines are subjected to layer changing so as to reduce signal crosstalk.
The technical scheme shows that the invention has the following advantages: the upper reference ground plane and the lower reference ground plane of the signal layer can reduce signal loss, effectively inhibit crosstalk between signals and simulate impedance matching. Each high-speed differential signal line is provided with 4N inflection points, N sections are arranged on the inner layer and the outer layer of each high-speed differential signal line, so that the length of two signals of each group of differential signal lines is ensured to be the same, and the impedance matching of the differential signal lines is improved.
Drawings
Fig. 1 is a wiring diagram of a medium-high speed differential signal according to the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
The high-speed multilayer PCB lamination and the wiring method adopt the following mode when laminating, taking 18-layer plates as an example, TOP, M6, GND02, M6, ART03, M6, GND04, M6, ART05, M6, POWER06, M6, ART07, M6, GND08, M6, POWER09, M6, POWER10, M6, GND11, M6, ART12, M6, GND13, M6, ART14, M6, GND15, M6, ART16, M6, GND17, M6 and BOTTOM from TOP to BOTTOM. Where M6 is a loose high speed board, M6 has a low node constant, and low dielectric loss ART represents the signal layer. And a component is arranged on the TOP layer BOTTOM layer, a through hole electrically connected with the Signal layer is arranged at a pad of the component, and the pad is electrically connected with the through hole. When the high-speed signal line is wired, an anti-bonding pad is arranged at the routing punching hole and used for increasing the impedance of the via hole so as to enable the via hole to be matched with the impedance of the high-speed signal line; the AC coupling capacitor needs to be subjected to adjacent layer hollowing treatment. The laminated structure can reduce signal loss, ensure high-speed signal transmission, effectively inhibit crosstalk between signals and simulate impedance matching.
The high-speed Signal line adopts the through-hole to trade the layer, carries out the backdrilling to the through-hole of transmission high-speed Signal line from the bottom and handles, and the length less than or equal to 10mil of the stake that is connected with the Signal layer after the backdrilling, and the length of this stake is the distance of Signal layer to backdrilling top department.
As shown in fig. 1, in high-speed differential Signal wiring, 4N inflection points with chamfers are provided on a line segment of each differential Signal line on a Signal layer, where N is a natural number, the differential Signal line is bent by 90 ° through each inflection point, and the length and angle of each chamfer are the same. And when the high-speed differential signal line is subjected to layer change, a ground hole is arranged at the through hole to reduce signal crosstalk. Each signal line is provided with 4N inflection points, N sections are arranged on the inner layer and the outer layer of each signal line, so that the length of two signals of each group of differential signal lines is ensured to be the same, and the impedance matching of the differential signal lines is improved.
Claims (4)
1. A high-speed multilayer PCB board lamination and wiring method, the PCB board includes TOP layer, GND layer, Signal layer, POWER layer and BOTTOM layer, wherein the base plate adopts the high-speed board; the upper layer and the lower layer of each Signal layer are GND layers; a component is arranged on the TOP layer BOTTOM layer, a through hole electrically connected with the Signal layer is arranged at a pad of the component, and the pad is electrically connected with the through hole; when the high-speed signal line is wired, an anti-bonding pad is arranged at the routing punching hole and used for increasing the impedance of the via hole so as to enable the via hole to be matched with the impedance of the high-speed signal line; the AC coupling capacitor needs to be subjected to adjacent layer hollowing treatment.
2. A high speed multi-layer PCB board stack up and routing method as recited in claim 1, wherein: the high-speed Signal line adopts the through-hole to trade the layer, carries out the backdrilling to the through-hole of transmission high-speed Signal line from the bottom and handles, and the length less than or equal to 10mil of the stake that is connected with the Signal layer after the backdrilling, and the length of this stake is the distance of Signal layer to backdrilling top department.
3. A high speed multi-layer PCB board stack up and routing method as recited in claim 1, wherein: when high-speed differential Signal wiring is carried out, 4N inflection points with chamfers are arranged on a line segment, located on a Signal layer, of each differential Signal line, wherein N is a natural number, the differential Signal line bends 90 degrees through each inflection point, and the length and the angle of each chamfer are the same.
4. A high speed multi-layer PCB board stack up and routing method as recited in claim 3, wherein: and when the high-speed differential signal line is subjected to layer change, a ground hole is arranged at the through hole to reduce signal crosstalk.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911010663.0A CN110719690A (en) | 2019-10-23 | 2019-10-23 | High speed multi-layer PCB stack and routing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911010663.0A CN110719690A (en) | 2019-10-23 | 2019-10-23 | High speed multi-layer PCB stack and routing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110719690A true CN110719690A (en) | 2020-01-21 |
Family
ID=69213163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911010663.0A Withdrawn CN110719690A (en) | 2019-10-23 | 2019-10-23 | High speed multi-layer PCB stack and routing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110719690A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113960857A (en) * | 2021-10-29 | 2022-01-21 | 歌尔光学科技有限公司 | DMD circuit board and DLP ray apparatus module |
| CN114071857A (en) * | 2020-08-05 | 2022-02-18 | 深南电路股份有限公司 | Circuit board |
| CN114501850A (en) * | 2022-01-14 | 2022-05-13 | 苏州浪潮智能科技有限公司 | Via hole design method, via hole, PCB (printed Circuit Board), PCB design and production method |
| CN114615797A (en) * | 2022-05-11 | 2022-06-10 | 成都英思嘉半导体技术有限公司 | Multi-channel high-speed flexible board |
| CN115279038A (en) * | 2022-09-26 | 2022-11-01 | 深圳国人无线通信有限公司 | Wiring method suitable for high-speed signal transmission and PCB |
-
2019
- 2019-10-23 CN CN201911010663.0A patent/CN110719690A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114071857A (en) * | 2020-08-05 | 2022-02-18 | 深南电路股份有限公司 | Circuit board |
| CN114071857B (en) * | 2020-08-05 | 2024-04-05 | 深南电路股份有限公司 | Circuit board |
| CN113960857A (en) * | 2021-10-29 | 2022-01-21 | 歌尔光学科技有限公司 | DMD circuit board and DLP ray apparatus module |
| CN114501850A (en) * | 2022-01-14 | 2022-05-13 | 苏州浪潮智能科技有限公司 | Via hole design method, via hole, PCB (printed Circuit Board), PCB design and production method |
| CN114501850B (en) * | 2022-01-14 | 2023-08-08 | 苏州浪潮智能科技有限公司 | Via hole design method, via hole, PCB board, PCB design and production method |
| CN114615797A (en) * | 2022-05-11 | 2022-06-10 | 成都英思嘉半导体技术有限公司 | Multi-channel high-speed flexible board |
| CN114615797B (en) * | 2022-05-11 | 2022-07-29 | 成都英思嘉半导体技术有限公司 | Multi-channel high-speed flexible board |
| CN115279038A (en) * | 2022-09-26 | 2022-11-01 | 深圳国人无线通信有限公司 | Wiring method suitable for high-speed signal transmission and PCB |
| CN115279038B (en) * | 2022-09-26 | 2022-12-27 | 深圳国人无线通信有限公司 | Wiring method suitable for high-speed signal transmission and PCB |
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| Date | Code | Title | Description |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20200121 |