WO2016202152A1

WO2016202152A1 - Chip packaging carrier, chip and circuit board

Info

Publication number: WO2016202152A1
Application number: PCT/CN2016/083307
Authority: WO
Inventors: 沈晓兰
Original assignee: 华为技术有限公司
Priority date: 2015-06-16
Filing date: 2016-05-25
Publication date: 2016-12-22
Also published as: CN106257661B; CN106257661A

Abstract

A chip packaging carrier (20), a chip and a PCB board, which relate to the field of microelectronics. A capacitor is mounted on the surface of the carrier for filtering, so that the electromagnetic radiation interference of the carrier is reduced, the integrity of a system signal is improved, the problem that a filtering effect is not good, caused due to the fact that the filtering capacitor is isolated due to a path ESL effect, is solved, thereby effectively utilizing a 3D space in a package and simplifying a circuit design on a product single board. The chip packaging carrier comprises: a top layer (201) for arranging a power supply network and communicating with a power supply pin of a capacitor or for arranging a ground wire and communicating with a ground pin of the capacitor, wherein the capacitor is arranged on the top layer; a second wiring layer (202) arranged below the top layer, wherein when the top layer is used for arranging the power supply network, the second wiring layer is used for arranging the ground wire and communicating with the ground pin of the capacitor, and when the top layer is used for arranging the ground wire, the second wiring layer is used for arranging the power supply network and communicating with the power supply pin of the capacitor; and a third wiring layer (203) arranged below the second wiring layer for arranging an IO lead wire.

Description

Chip package carrier, chip and board

Technical field

The present invention relates to the field of microelectronics, and more particularly to a chip package carrier board, a chip and a circuit board.

Background technique

An electronic system is generally an objective entity that consists of electronic components or components that can generate, transmit, collect, or process electrical signals and information. With the in-depth development of informatization and intelligence, electronic systems are increasingly used in mobile phones, computers, automotive electronics, industrial control and so on.

The electronic system design generally considers DIE (die of a single unit before packaging, referred to as bare chip), carrier board, package, and product board. Among them, DIE, chip package carrier board, and product board are especially considered. Division of labor. For example, in the traditional design division, the working frequency of the discrete device filter capacitors of the product boards is generally below 100 MHz. The reason is that the loop inductance of the product board interconnection channel has a similar isolation effect on the capacitance of the higher frequency band. , we call the Equivalent Series Inductance (ESL) effect; while the metal layer of DIE is limited, the total amount of capacitance that can be designed in the DIE part has its upper limit, when the demand of dynamic current exceeds the load capacity of the existing DIE After that, the designer began to consider an additional filtering scheme on the carrier board, that is, designing the filter capacitor on the carrier board.

Capacitors are generally available in both buried and planar mounting on the carrier board. The embedded design is complicated by the embedded device, the production process is long, the yield is low, the cost is high, and the design is increased. The thickness of the carrier is therefore generally not used. However, the planar installation method currently has a wiring path problem. As shown in FIG. 1 , the peripheral pins of the existing DIE 10 are generally arranged with a high-speed IO (Input/output) line 11 and a power supply ground pin 12 on the inner ring. It is possible to increase the density of the outlet and facilitate the appearance of the surface. However, the inventor found that there are two problems with such a design. First, the high-speed IO line is connected by the surface layer of the carrier 20, and it takes a long time. The surface line will cause more serious Electromagnetic Interference (EMI) problems and Signal integrity (SI) problems. Even if the shielding Shield can partially solve the external EMI problem, each package There is still no way to solve the EMI and SI problems between signals. Second, the power/ground pin is distributed in the inner ring, connected to the inner layer by the large hole of the inner ring, and then connected to the bottom pad (PAD), so that the power/ground and the filter device mounted on the surface of the carrier board can only be connected. Through the inner layer communication, this not only increases the number of wiring layers in the inner layer of the carrier, but also avoids many large holes in the inner layer, and the remaining communication paths are also limited, and the path ESL effect generated by this connection method is isolated. The filtering effect of the filter capacitor does not provide enough dynamic current.

Summary of the invention

The embodiment of the invention provides a chip package carrier board, a chip and a circuit board, which realizes filtering on the surface of the carrier board for filtering, reduces loop inductance, improves filtering effect, and reduces electromagnetic interference of the carrier board, and improves System signal integrity, improved path ESL effect isolation filter capacitor results in poor filtering effect, effectively utilizing the 3D space inside the package, simplifying the circuit design on the product board.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

A first aspect of the present invention provides a chip package carrier board, including:

a top layer of the chip package carrier: the top layer is used to route a power supply network and is connected to a power supply pin of the capacitor or for routing a ground line and is connected to a ground pin of the capacitor, the capacitor being disposed on the top layer;

a second wiring layer disposed under the top layer: the top layer is used to route a power network, the second wiring layer is used to lay a ground line and communicate with a ground pin of the capacitor; When the ground wire is disposed, the second wiring layer is used to lay a power network and communicate with a power pin of the capacitor;

a third wiring layer disposed under the second wiring layer: the third wiring layer is used for cloth Set the IO lead connected to the IO port of the die.

In a first possible implementation manner of the present invention, the top layer is used to lay a ground wire and communicate with a ground pin of the capacitor; the second wiring layer is used to lay a power network and a power source of the capacitor Pin connected.

In conjunction with the first possible implementation manner of the present invention, in a second possible implementation manner of the present invention, the power supply pin of the capacitor is connected to the power supply network of the second wiring layer through the first via hole; The aperture of the first via is less than or equal to 20 um.

In conjunction with the second possible implementation of the present invention, in a third possible implementation of the present invention, the first via hole is processed by a laser drilling micro blind hole technique.

In conjunction with the first aspect of the present invention and the foregoing possible implementation manner, in a fourth possible implementation manner of the present invention, the IO port of the die is connected to the IO lead of the third wiring layer through the second via hole The aperture of the second via hole is less than or equal to 20 um.

In conjunction with the fourth possible implementation manner of the present invention, in a fifth possible implementation manner of the present invention, the second via hole is a second-order stacked hole processed by a laser drilling micro blind hole technology.

With reference to the fifth possible implementation manner of the present invention, in a sixth possible implementation manner of the present invention, the top layer is provided with a binding at a corresponding position of the first via hole and the second via hole The pads, the projections of the first vias and the second vias on the top layer do not exceed the coverage of the corresponding bonding pads.

In conjunction with the first aspect of the present invention, in a seventh possible implementation, the capacitor includes a filter capacitor, and the number of the filter capacitors is optimized as follows: a port loop impedance slope of any of the power pins It is no longer reduced with the increase of the number of filter capacitors installed on the surface of the chip package carrier, or the loop impedance slope meets the design requirements within the working bandwidth range. At this time, the number of filter capacitors on the chip package carrier is optimal. If the total capacitance of the filter capacitor still does not meet the design requirements, and the number of filter capacitors needs to be increased, the added filter capacitor is mounted on the PCB.

In conjunction with the first aspect or the first to third, or the seventh possible implementation of the present invention, in the eighth possible implementation, the top layer is further provided with other non-capacitive components.

In conjunction with an eighth possible implementation of the present invention, in a ninth possible implementation of the present invention, the other non-capacitive devices are devices that do not need to be interconnected on a PCB.

A second aspect of the present invention provides a chip using the chip package carrier of any one of the above aspects of the present invention.

A third aspect of the present invention provides a circuit board comprising a PCB board and a chip disposed on the PCB board, wherein the chip uses the chip package carrier board according to any one of the above aspects of the present invention.

The chip package carrier board, the chip and the circuit board provided by the embodiments of the present invention optimize the carrier layer stack by mounting the capacitor on the surface of the chip package carrier board: the power supply network is arranged on the top layer of the carrier board and the capacitor is The power pin is connected, and the second wiring layer under the top layer is grounded and connected to the ground pin of the capacitor (or the ground wire is disposed at the top and connected to the ground pin of the capacitor, and the second wiring layer is disposed with the power network and the capacitor The power supply pin is connected); the IO lead connected to the IO port of the die is disposed on the third wiring layer under the second wiring layer. The above technical solution provided by the present invention can achieve the following effects:

1. The invention arranges the capacitor on the surface of the chip package carrier board, can solve the problem of high dynamic load current of the chip power supply pin, and can also effectively utilize the 3D space in the package. At the same time, the high-frequency filter capacitor on the product board can be transferred to the chip package carrier board, thereby reducing the number of high-frequency filter capacitors on the product board, thereby reducing the layout area of the product board and simplifying the power supply. The ESL limit requirements for the channel from the chip package carrier to the product board routing path;

2. The invention separately sets two layers for respectively laying the power network and the ground line, enlarges the width of the power channel and the ground channel, reduces the loop inductance, and improves the filtering effect;

3. The third wiring layer under the top layer and the second wiring layer of the present invention is provided with IO leads, that is, the present invention embeds the IO signal, reduces EMI interference, and improves signal SI performance.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.

1 is a schematic diagram of wiring of a surface layer of a conventional chip package carrier;

2 is a schematic diagram showing the positional relationship of each wiring layer of a chip package carrier according to an embodiment of the present invention;

3 is a schematic diagram showing the layout of a top-level power supply line and a surface mount capacitor of a carrier according to Embodiment 2 of the present invention;

4 is a schematic cross-sectional structural view of a second via hole according to an embodiment of the present invention;

5 is a schematic diagram showing a layout of a chip package carrier provided with a filter capacitor and other non-capacitor devices according to Embodiment 3 of the present invention;

6(a) is a circuit diagram showing a sample-chip package carrier board and a PCB board provided in Embodiment 3 of the present invention, and 6 filter capacitors are mounted on the PCB board;

6(b) is a schematic circuit diagram of installing two filter capacitors on a sample two-chip package carrier board provided in Embodiment 3 of the present invention;

7 is a schematic diagram showing a comparison of port loop impedances of the same DIE side power supply observation pins in the two filtering modes shown in FIG. 6(a) and FIG. 6(b);

FIG. 8 is a partially enlarged schematic view of FIG. 7 in a low frequency band.

Reference numeral

10-die, 11-IO line, 12-power pin, 20-chip package carrier,

201- top layer, 202-second wiring layer, 203-third wiring layer,

21-second via, 21a-bonded pad, 22-capacitor routing area,

22a-one pin of the capacitor, 23-non-capacitor device layout area, 30-PCB board,

24-filter capacitor, 25-resistor.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments.

An embodiment of the present invention provides a chip package carrier. As shown in FIG. 2, the chip package carrier 20 includes a top layer 201 of a chip package carrier. The top layer 201 is used to connect a power supply network and is connected to a power supply pin of the capacitor. For routing the ground wire and communicating with the ground pin of the capacitor, the capacitor is disposed on the top layer 201; the second wiring layer 202 disposed under the top layer 201, and the second wiring layer 202 when the top layer 201 is used for routing the power network The second wiring layer 202 is configured to connect the power supply network and communicate with the power supply pin of the capacitor, and is disposed on the second wiring layer 202. a third wiring layer 203 for laying an IO lead connected to the IO port of the die 10

Die (DIE) is a chip produced in a processing factory, that is, a chip that has not been packaged after the wafer has been cut and tested. Only the pad used for packaging on this die cannot be directly applied to the actual chip. Among the circuits. However, the die is highly susceptible to the external environment's temperature, impurities and physical forces, and is easily damaged. Therefore, it must be enclosed in a confined space to lead the corresponding pins to be used as a basic component. The die is usually mounted on a chip package carrier board. The internal circuit of the die is connected to the package pin by gold bonding. After bonding, the die is packaged with black colloid to form a chip package (Chip). Package).

This embodiment provides a carrier board (generally referred to as a chip package carrier board, which is also referred to herein as a carrier board for simplicity) in the packaging of a die. The carrier board is surface mounted on the top layer 201. The mode is provided with a capacitor, for which the carrier board is powered on the top layer 201. The network is connected to the power supply pin of the capacitor, and the second wiring layer 202 under the top layer 201 is grounded and communicated with the ground pin of the capacitor, and the third wiring layer 203 under the second wiring layer 202 is disposed with the die. IO pin connected to the IO port. Of course, the top layer 201 can be changed to the grounding line and communicate with the ground pin of the capacitor. The second wiring layer 202 is disposed with a power supply network and is connected to the power supply pin of the capacitor.

Thus, the top layer 201 and the second wiring layer 202 are respectively used for laying the power network and the ground line, expanding the width of the power channel and the ground channel, reducing the loop inductance, and improving the filtering effect; under the top layer 201 and the second wiring layer 202 The third wiring layer 203 is provided with IO leads, so that the IO signal is buried, and the top layer 201 and the second wiring layer 202 EMI shield the third wiring layer 203 and the IO leads in the layer, thereby reducing EMI interference and Improved signal SI performance.

It should be noted that, in this embodiment, only the relative positions of the chip package carrier top layer 201, the second wiring layer 202, and the third wiring layer 203 are limited. Those skilled in the art can understand that any two of the above layers are actually used. There is also an insulating layer disposed therebetween, or other wiring layers are disposed between any two layers, which is not limited in this embodiment.

The chip package carrier provided by the invention can be arranged with a capacitor on the surface thereof, which not only solves the problem of high dynamic load current of the chip power supply pin, but also can effectively utilize the 3D space in the package. In the specific implementation, the high-frequency filter capacitor on the product board can be transferred to the chip package carrier board to reduce the number of high-frequency capacitors on the product board, thereby reducing the layout area of the product board and simplifying the power channel. The ESL limit requirements for the chip package carrier to the product board routing path.

For a better understanding of the chip package carrier board provided by the embodiment of the present invention, a detailed description will be given below through specific embodiments.

Example 1:

The chip package carrier board provided in this embodiment has a filter capacitor mounted on the surface of the package carrier board. Specifically, the present embodiment does not need to change the existing die surface layer (DIE TOP layer) and the package bottom layer pin arrangement. Compared with the existing carrier board shown in FIG. 1 , the solution provided by this embodiment is equivalent to Adding two wiring layers, namely a top layer 201 and a second wiring layer 202, on the surface of the existing chip package carrier, wherein the top layer 201 is used to arrange a capacitor and a power network, and the power network is fully connected to the power supply pin of the capacitor The second wiring layer 202 is used for routing the ground line, and the ground pin of the capacitor is connected to the ground line disposed by the second wiring layer 202 by the first via hole, and the projected area of the first via hole on the top layer is not Exceeding the size of the corresponding surface pad, the first via is preferably processed by laser drilling micro blind hole technology. The TOP layer of the original IO lead is changed to the third wiring layer 203, and the high-speed IO port of the original outer ring is directly connected to the IO lead of the third wiring layer 203 through the second via at the original bonding pad, and the third wiring layer The manner in which the wiring of 203 is in communication with the bonding pad of the bottom surface can be the same as in the prior art.

Preferably, the apertures of the first via hole and the second via hole are both 20 um or less, and can be formed by using a small-sized processing capability of the laser blind via technology of the carrier plate in a specific implementation, and the via hole of 20 um or less can be used to expand the surface. Install the width of the power/ground channel in the filtering scheme to reduce loop inductance and improve filtering.

For details, the second via hole 21 is taken as an example. Referring to FIG. 4, the corresponding position of the second via hole 21 is also provided with a binding pad 21a, and the minimum aperture d of the second via hole 21 should not exceed the The minimum diameter D of the bonding pad 21a (i.e., d ≤ D), that is, the projection of the second via 21 at the top layer does not exceed the coverage of the corresponding bonding pad 21a. In a specific implementation, the second via hole may be set as a second-order stack hole (FIG. 4 is a cross-sectional view of the second-order stack hole), and is processed by laser drilling micro blind hole technology to fully utilize the laser blind hole hole technology of the carrier plate. The small size processing capability maximizes the width of the power/ground channel in the surface mount filter scheme, reduces loop inductance, and improves filtering.

Wherein, the second-order stacked hole sectional view is as shown in FIG. 4 . Where d is the diameter of the via of the second-order stack, D is the minimum diameter of the bond pad at the via, and the area of the second via does not exceed the minimum diameter of the surface bond pad within the processing tolerance (first Vias have the same requirements), The machining tolerance is typically 10% of the target size. D and d have a quantitative relationship according to the processing capability of the through-hole of the carrier. Generally, it is defined as: D=d+2A. The value range of A is based on the existing processing capability, and the value is generally 10~40um. Where d is the diameter of the borehole, which is d≤20um according to the current process level. d. When selecting the minimum value that can be achieved by the existing process capability, A also takes the minimum value that can be achieved by the existing process capability to make full use of the process window capability.

The chip package carrier board provided in this embodiment can increase the number of mounting capacitors of the carrier board, and fully utilize the 3D space in the chip package; the embodiment also fully utilizes the small-size processing capability of the carrier laser blind hole technology, and expands The width of the power/ground channel in the surface-mounted filtering scheme reduces the loop inductance and improves the filtering effect. Secondly, this embodiment also fully utilizes the small-size processing capability of the carrier laser blind hole technology to embed the high-speed IO signal, and newly increase The top layer and the second wiring layer simultaneously form an EMI shielding effect on the high-speed IO traces in the third wiring layer (or below) (the EMI and SI problems between signals in the DIE are also improved), and the EMI is reduced. Interfering with and improving the performance of the signal SI; in addition, since the corresponding ball grid array package (BGA package) solder ball arrangement can be eliminated by the pin that is connected in the chip package carrier, the embodiment can also reduce BGA package size; in addition, the pins that are connected in the chip package carrier can eliminate the corresponding ball grid array package solder ball arrangement, thus freeing up the design space In order to increase the number of pins in the original package size, increase the connectivity, and improve the signal integrity; the capacitor can be installed on the carrier board. Therefore, the electronic system of the carrier of the embodiment is used, and the product board can be used. The high-frequency filter capacitor is transferred to the chip package carrier board, thereby reducing the number of high-frequency capacitors on the product board, thereby reducing the layout area of the product board, simplifying the power channel from the chip package carrier board to the product board layout. The ESL limit requirements for the path.

Example 2:

Another embodiment of the present invention provides another chip package carrier board, which is different from Embodiment 1 in The top layer 201 of the carrier of the present embodiment is used for routing the ground line and directly communicating with the ground pin of the capacitor. The second wiring layer 202 is used for routing the power supply network and is connected to the power supply pin of the capacitor through the first via hole. The projected area of the via hole and the second via hole on the top layer does not exceed the size of the corresponding surface pad, and is preferably processed by laser drilling micro blind hole technology.

Specifically, FIG. 3 is a schematic diagram showing the layout of the top layer power supply and the surface mount capacitor of the carrier according to the embodiment: the top layer 201 of the carrier is used to lay the capacitor and the ground, and the capacitor in FIG. On the top layer of the board, and below the DIE 10 mounting position, the left side area is a

capacitor routing area

22, 22a is a pin of the capacitor, wherein a first via is disposed at the power supply pin of the capacitor, the power pin The power supply network of the second wiring layer 202 is connected by the first via. The high speed IO port on the DIE 10 is directly connected to the IO lead of the third wiring layer 203 through the second via 21a at the bonding pad.

In this embodiment, the third wiring layer 203 is provided with IO leads, and the second wiring layer 202 above the third wiring layer 203 is used for laying the power supply network, and the top layer 201 for laying the ground lines is disposed at the top, such a laminated arrangement shielding The effect is better, which is more conducive to further reducing the external radiation level of the chip package. Except for this, the solution of the embodiment 2 and the effect of the implementation thereof are substantially the same as those of the embodiment 1, and details are not described herein again.

Example 3:

Another embodiment of the present invention provides a chip package carrier. In this embodiment, the stacking of the wiring layers of the chip package carrier is performed in the manner shown in Embodiment 1 or Embodiment 2. The difference from the first embodiment and the second embodiment is that the capacitance of the top layer of the chip package carrier provided by the embodiment is a filter capacitor, and the number of filter capacitors is optimized. The standard is: if any power pin The slope of the port loop impedance does not decrease with the increase of the number of filter capacitors installed on the surface of the chip package carrier board, or the loop impedance slope satisfies the design requirements within the working bandwidth range, then the number of filter capacitors is optimal, no longer If the number of filter capacitors needs to be increased according to the design requirements, install the additional filter capacitors on the PCB (Printed Circuit Board). Of course, if the number of filter capacitors required by the design requirements is less than or equal to the above, For the best value, all of the above capacitors can be mounted on the chip package carrier.

In addition, other non-capacitive components are disposed on the top layer of the embodiment. Further preferably, the other non-capacitive components of the top layer arrangement of the present embodiment are devices that do not need to be interconnected on the PCB. In this way, after these devices are placed on the chip package carrier board, they only need to be connected on the chip package carrier board, and the connection of the network on the BGA package can be eliminated without the need to be connected to the PCB board, thereby reducing the BGA. The number of pins is packaged to reduce the BGA package size.

For example, it can be optimized by simulating experimental data. If the slope of the port loop impedance of any power supply pin does not decrease with the increase of the number of filter capacitors installed on the surface of the chip package carrier board, then the number of filter capacitors should be increased only. Contribution to the total filter capacitor capacity without further reducing the loop inductance, that is, at this point we have fully utilized the surface mount capacitor of the chip package carrier for high frequency filtering to provide dynamic current, which will then be needed The increased capacitance capacity placed on the surface of the chip package carrier layer does not contribute to reducing the loop inductance, so the increased capacitance capacity can be arranged to the PCB portion of the product board.

In this way, if the surface of the chip package carrier still has the remaining installation space, this space can be used to install some of the other non-capacitive components originally placed on the product PCB, preferably the device that completes the network connection relationship in one connection (ie, preferably not Devices that need to be interconnected on the PCB), thus eliminating the pin placement of the network on the BGA package, thereby reducing the number of pins in the BGA package, thereby reducing the BGA package size.

For example, as shown in FIG. 5, a package-on-package (POP) device is used as an example, and a filter capacitor, a precision voltage dividing resistor, a reference reference capacitor, and the like of a POP-mounted memory device can be mounted on a chip. The board is packaged, and the pinouts on this part of the package can be eliminated.

In order to further illustrate the advantages of the carrier board filtering scheme (chip package carrier board mounting filter capacitor), the following is a specific simulation experiment:

Simulation experiment process: According to the circuit diagram shown in Fig. 6(a), the sample 1 is built. The sample 1 adopts the PCB filtering scheme, specifically including the die 10, the chip package carrier board, and the PCB board connected to the die 10 through the package carrier board, sample one The chip package carrier board adopts the existing scheme (for example, the chip package carrier board shown in FIG. 1), and the sample one is provided with six filter capacitors 24 on the PCB board, and then the ports of the power supply pins on the chip package carrier board are made. Loop impedance observation, the specific results are shown in Fig. 7, the curve group A in Fig. 8; at the same time, the circuit diagram is constructed according to the circuit diagram shown in Fig. 6(b), except that the sample 2 uses the chip provided by the embodiment 1 of the present invention. The package carrier board, that is, the sample 2 adopts a carrier board filtering scheme, and the carrier board is provided with the same two filter capacitors 24 as the sample one PCB board, and cancels the level connection relationship with the PCB board, and the DIE on the chip package carrier board Port loop impedance observation is performed on each power supply pin with the same side. The specific results are shown in curve group B in FIG. 7 and FIG. Among them, 25 in FIGS. 6(a) and 6(b) is a resistor.

The observation and comparison results are shown in Fig. 7 and Fig. 8. As shown in the figure, although the number of capacitors in the PCB filtering scheme used in the sample is three times that of the sample two filter capacitors, the measured impedance line (the curve group) A) is still above the impedance line of sample 2 (curve group B), that is, the impedance of the sample is much higher than the impedance of sample 2. This comparison diagram fully demonstrates the efficiency and high performance of the chip package carrier filter; aspect. This also shows that the chip package carrier board filter can save the filter capacitor, which greatly reduces the need for PCB board filter space. In addition, it should be noted that the above discussion is mainly for the signal frequency band above 25MHZ. If the operating frequency is lower than 25 MHz, the two filtering schemes are not comparable due to the difference in total filter capacitance.

According to the above experimental results, the present embodiment preferably mounts the low parasitic inductance capacitance (providing a low parasitic inductance characteristic of 25 MHz or more) on the chip package carrier board, and mounts the low frequency filter bulk capacitor to the PCB board. On the one hand, the low parasitic inductance capacitor is mounted on the chip package carrier board, which can share the pressure of the PCB board level filtering space, and can greatly improve the high frequency filtering effect; on the other hand, the low frequency filter is mounted on the PCB board with a large capacity capacitor. The communication channel between the chip package carrier board and the PCB board only needs to ensure the current capability of the power supply of the circuit board, which can greatly reduce the wiring resources from the chip package carrier board to the filter capacitor channel on the PCB board, that is, the power supply of the circuit can be reduced. The number of pins on the BGA package.

Example 4:

This embodiment provides a chip that uses any core provided by the embodiment of the present invention. The chip package carrier. The present embodiment further provides a circuit board including a PCB board and a chip disposed on the PCB board, and the chip adopts any chip package carrier board provided by the embodiment of the present invention.

The embodiment provides a chip and a circuit board, which solves the problem of high dynamic load current of the chip power supply pin, and effectively utilizes the 3D space mounting capacitor and other devices in the package, thereby reducing the number of high frequency capacitors and other devices on the product board. In turn, the layout area of the product boards and the BGA package size of the carrier board are reduced, and the ESL limitation requirements of the power channel from the chip package carrier board to the product board routing path are simplified.

In the frequency range above 25MHZ, the carrier board filtering effect is better than the PCB board level filtering effect, so each power supply network surface on the carrier board is used to preferentially install low parasitic inductance capacitance (providing low parasitic inductance characteristics above 25MHZ), the number Generally, it is larger than two, and the filter capacitor on the carrier board is preferably a capacitor with a low ESL effect such as a three-terminal capacitor, which together constitute a power supply filter network with low loop impedance, which greatly improves the frequency response characteristics of the power supply and can provide a larger high frequency. Dynamic current. The bulk capacitor for low frequency filtering is placed on the PCB.

However, it should be noted that since the carrier board filtering effect is better than the PCB board level filtering effect in the frequency range higher than 25 MHz, if the same filtering effect is achieved, the low parasitic inductance capacitance that is transferred to the chip package carrier board for mounting is provided (provided The number of low parasitic inductance characteristics above 25 MHz is reduced. That is, under the same filtering effect, the number of high-frequency filter capacitors required for mounting on the chip package carrier board is less than the number of high-frequency filter capacitors required for PCB board-level filter installation.

The circuit board provided in this embodiment adopts a filtering scheme of a chip package carrier board and a PCB, and the power supply loop impedance thereof is significantly reduced, and is even better than a simple chip package carrier board filtering scheme (only the filter capacitor is mounted on the chip package carrier board) The main reason is that the pure chip package carrier filter scheme uses the same planar layout (ie, at the top) filter capacitor, while the chip package carrier plus PCB filter scheme uses a two-sided layout (ie, simultaneously in the chip package) The filter capacitor is placed on the carrier board and the PCB, which can greatly reduce the area of the power supply loop. The power supply loop impedance is proportional to the power supply loop area. As the power supply loop area shrinks, the loop impedance of the power loop is also significantly reduced. . Therefore, by using the design architecture of the embodiment, the chip package carrier filter and the PCB filtering scheme can be combined, and the effect is better.

The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Claims

A chip package carrier board, comprising:

a top layer of the chip package carrier: the top layer is used to route a power supply network and is connected to a power supply pin of the capacitor or for routing a ground line and is connected to a ground pin of the capacitor, the capacitor being disposed on the top layer;

a second wiring layer disposed under the top layer: the top layer is used to route a power network, the second wiring layer is used to lay a ground line and communicate with a ground pin of the capacitor; When the ground wire is disposed, the second wiring layer is used to lay a power network and communicate with a power pin of the capacitor;

a third wiring layer disposed under the second wiring layer: the third wiring layer is used to route an IO lead connected to an IO port of the die.
The chip package carrier of claim 1 wherein

The top layer is for routing a ground line and is in communication with a ground pin of the capacitor; the second wiring layer is for routing a power supply network and is in communication with a power supply pin of the capacitor.
The chip package carrier of claim 2, wherein

The power supply pin of the capacitor is connected to the power supply network of the second wiring layer through the first via hole; the aperture of the first via hole is less than or equal to 20 um.
The chip package carrier of claim 3, wherein

The first via hole is processed by laser drilling micro blind hole technology.
The chip package carrier according to any one of claims 1 to 4, wherein

The IO port of the die is connected to the IO lead of the third wiring layer through the second via hole; the aperture of the second via hole is less than or equal to 20 um.
The chip package carrier of claim 5, wherein

The second via hole is a second-order stack hole processed by a laser drilling micro blind hole technique.
The chip package carrier according to claim 6, wherein the top layer is provided with a binding pad at a corresponding position of the first via and the second via, the first via And the projection of the second via hole on the top layer does not exceed the coverage of the corresponding bonding pad.
The chip package carrier of claim 1 wherein

The capacitor includes a filter capacitor, and the number of the filter capacitors is optimized according to the following criteria: if the slope of the port loop impedance of any of the power pins is no longer related to the number of filter capacitors mounted on the surface of the chip package carrier Increase or decrease, or the loop impedance slope meets the design requirements within the working bandwidth. At this time, the number of filter capacitors on the chip package carrier is optimal. If the total capacitance of the filter capacitor still does not meet the design requirements. If you need to increase the number of filter capacitors, install the added filter capacitors on the PCB.
A chip package carrier according to any one of claims 1 to 4, wherein the top layer is further provided with other non-capacitive members.
The chip package carrier of claim 9 wherein:

The other non-capacitive devices are devices that do not need to be interconnected on the PCB.
A chip characterized by using the chip package carrier according to any one of claims 1 to 10.
A circuit board comprising a PCB board and a chip disposed on the PCB board, wherein the chip uses the chip package carrier board according to any one of claims 1-10.