JP7010314B2 - Through Silicon Via Substrate - Google Patents

Description

The present invention relates to a method for manufacturing a through silicon via substrate.

In recent years, integrated circuits have become finer and more complicated as the performance of integrated circuits has improved. In such an integrated circuit, a connection terminal for inputting a power supply and a logic signal necessary for driving the circuit from an external device is arranged. However, due to the miniaturization and complexity of integrated circuits, the connection terminals on the integrated circuit are arranged at a very narrow pitch, which is several to several tens of times smaller than the pitch of the connection terminals of the external device.

As described above, when connecting an integrated circuit having a different pitch of each connection terminal to an external device, an interposer serving as an intermediary board for converting the pitch of the connection terminals is used. In the interposer, an integrated circuit is mounted on the first terminal arranged on one surface of the board, an external device is mounted on the second terminal arranged on the other surface, and the first terminal and the second terminal are It is connected by a through electrode that penetrates the substrate.

Further, as interposers, TSV (Through-Silicon Via), which is a through electrode substrate using a silicon substrate, and TGV (Through-Glass Via), which is a through electrode substrate using a glass substrate, have been developed (for example, patents). Document 1). In particular, the TGV is advantageous in that the manufacturing cost can be reduced because it can be manufactured using a large glass substrate having a vertical and horizontal size of 730 mm × 920 mm, which is called, for example, the 4.5 generation. ..

Here, in order to form a structure such as a multilayer wiring structure on a substrate, many processes such as a film forming process, a photolithography process, and a processing process are required. Since the substrate is required to have a certain degree of rigidity for these processes, it is necessary to have a thickness of the substrate that can secure the rigidity enough to withstand the process. On the other hand, in the process of forming a through hole in a substrate, the depth (aspect ratio) of the hole with respect to the hole diameter is limited, and it is difficult to form a through hole in a thick substrate. Therefore, for example, in Patent Document 1, after forming a bottomed hole in a substrate, the substrate is thinned from a surface opposite to the surface on which the bottomed hole is formed, or processing is performed from the front and back surfaces of the substrate. In order to form the through hole, it was necessary to process the substrate multiple times.

Japanese Unexamined Patent Publication No. 2011-178642

However, as described above, if the process of processing the substrate multiple times to form the through hole is performed, not only the number of processes increases and the manufacturing period becomes longer, but also the probability of occurrence of defects in each process increases. , Yield decreases. Further, in order to make the substrate thinner, it is necessary to attach the support substrate to the substrate on which the circuit is formed in order to maintain the rigidity, and further the attachment step and the peeling step of the support substrate are required, and the manufacturing period is further increased. It becomes longer and the yield decreases.

In view of the above circumstances, it is an object of the present invention to provide a method for manufacturing a through silicon via substrate, which can reduce the number of steps, shorten the manufacturing period, and improve the yield.

In the method for manufacturing a through electrode substrate according to an embodiment of the present invention, a alteration layer is formed on a first substrate, and a first wiring layer is formed on the first substrate via a first wiring layer in contact with the alteration layer and an insulating layer. A multi-layer wiring structure having a second wiring layer connected to is formed, and a chip having an electronic circuit is mounted on the multi-layer wiring structure via a first bump in contact with the second wiring layer, and the first bump of the chip is formed. The second substrate is attached to the opposite side via the adhesive layer, the first substrate is thinned by the first etching from the side opposite to the multilayer wiring structure of the first substrate, and the multilayer wiring structure of the first substrate is formed. Selectively removes the altered layer from the opposite side by the second etching, forms a through hole that penetrates the first substrate and exposes the first wiring layer, and forms a second bump that connects to the first wiring layer. ..

According to the above-mentioned manufacturing method of the through electrode substrate, the first substrate on which the multilayer wiring structure is formed can be thinned by using the second substrate which is a support substrate for an external device such as a chip. It is possible to omit the step of attaching / peeling the support substrate for the conversion. Further, by forming a alteration layer in the region where the through hole of the first substrate is to be formed, forming the multilayer wiring structure, and then removing the alteration layer, the multilayer wiring structure is formed on an unprocessed flat substrate. can do.

Further, in another embodiment, the second substrate may have a higher thermal conductivity than the third substrate on which the chip is formed.

According to the above-mentioned manufacturing method of the through electrode substrate, the first substrate on which the multilayer wiring structure is formed can be thinned by using the second substrate which is a heat dissipation plate of an external device such as a chip. It is possible to omit the step of attaching / peeling the support substrate for the conversion.

Further, in another embodiment, the etching conditions of the first etching and the etching conditions of the second etching may be the same etching conditions.

According to the above-mentioned manufacturing method of the through electrode substrate, by forming a alteration layer having an etching rate faster than that of the first substrate in the region where the through holes of the first substrate are desired to be formed, the first substrate can be made thinner and penetrated. Pore formation can be done in the same process.

Further, in another embodiment, a spacer for maintaining the distance between the multilayer wiring structure and the second substrate is further formed in the second region located on the outer peripheral side of the first region of the multilayer wiring structure on which the chip is mounted. You may.

According to the above-mentioned method for manufacturing a through silicon via substrate, the first substrate and the second substrate on which the multilayer wiring structure is formed can be firmly fixed as compared with the structure without spacers. Therefore, in the process of thinning the first substrate, the in-plane uniformity of the thinning can be improved.

Further, in another embodiment, a third bump may be further formed between the multilayer wiring structure and the spacer in the same process as the first bump.

According to the above-mentioned method for manufacturing a through silicon via substrate, the height of the spacer can be reduced by the height at which the third bump is formed, so that the material used for the spacer can be reduced. Further, when forming the spacer, the third bump can be used as an alignment marker.

In the method for manufacturing a through electrode substrate according to an embodiment of the present invention, a bottomed hole is formed in the first substrate, a part of the surface of the first substrate and the first electrode are formed inside the bottomed hole, and the first electrode is formed. A first layer wiring structure having a first wiring layer in contact with the first electrode and a second wiring layer connected to the first wiring layer via an insulating layer is formed on one substrate, and the first wiring structure is in contact with the second wiring layer. A chip having an electronic circuit is mounted on a multi-layer wiring structure via bumps, a second substrate is attached via an adhesive layer on the side opposite to the first bump of the chip, and the multi-layer wiring structure of the first substrate is attached. Thins the first substrate from the opposite side, forms a through hole that penetrates the first substrate and exposes the first electrode, and forms a second bump that connects to the first electrode.

According to the above-mentioned manufacturing method of the through electrode substrate, the first substrate on which the multilayer wiring structure is formed can be thinned by using the second substrate which is a support substrate for an external device such as a chip. It is possible to omit the step of attaching / peeling the support substrate for the conversion.

Further, in another embodiment, the second substrate may have a higher thermal conductivity than the third substrate on which the chip is formed.

According to the above-mentioned manufacturing method of the through electrode substrate, the substrate on which the multilayer wiring structure is formed can be thinned by using the heat sink of an external device such as a chip, so that the support substrate for thinning can be thinned. The pasting / peeling step can be omitted.

Further, in another embodiment, the first film-like resin covering the bottomed hole is attached on the first substrate and the first electrode, and the first electrode is exposed to the first film-like resin. The first wiring layer may be connected to the first electrode via the first opening.

According to the above-mentioned method for manufacturing a through silicon via substrate, by covering the bottomed holes formed in the substrate with the first film-like resin, the step formed by the bottomed holes can be relaxed.

Further, in another embodiment, a film-like second film-like resin covering the through hole is attached to the thinned side of the first substrate, and a second opening for exposing the first electrode to the second film-like resin is provided. The second bump may be formed and connected to the first electrode via the second opening.

According to the above-mentioned manufacturing method of the through electrode substrate, by covering the through holes formed in the substrate with the second film-like resin, the step formed by the through holes can be relaxed.

Further, in another embodiment, the second electrode connected to the first electrode is formed on the thinned side of the first substrate, and the second film-like resin is the thinned side of the first substrate and the second. It may be attached on the electrode so as to cover the through hole.

According to the above-mentioned manufacturing method of the through electrode substrate, the second opening may be provided so as to expose the second electrode. Therefore, by adjusting the pattern of the second electrode, the alignment accuracy of the second opening can be relaxed. can do.

Further, in another embodiment, a spacer for maintaining the distance between the multilayer wiring structure and the second substrate is further formed in the second region located on the outer peripheral side of the first region of the multilayer wiring structure on which the chip is mounted. You may.

According to the above-mentioned method for manufacturing a through silicon via substrate, the first substrate and the second substrate on which the multilayer wiring structure is formed can be firmly fixed as compared with the structure without spacers. Therefore, in the process of thinning the first substrate, the in-plane uniformity of the thinning can be improved.

Further, in another embodiment, a third bump may be further formed between the multilayer wiring structure and the spacer in the same process as the first bump.

According to the above-mentioned method for manufacturing a through silicon via substrate, the height of the spacer can be reduced by the height at which the third bump is formed, so that the material used for the spacer can be reduced. Further, when forming the spacer, the third bump can be used as an alignment marker.

In the method for manufacturing a through electrode substrate according to an embodiment of the present invention, a first substrate is prepared, and a second wiring layer is connected to the first wiring layer on the first substrate via a first wiring layer and an insulating layer. A multi-layer wiring structure having a The second substrate is attached via the above, the first substrate is thinned from the side opposite to the multilayer wiring structure of the first substrate, the first wiring layer and the insulating layer are exposed, and the second is connected to the first wiring layer. Form a bump.

According to the above-mentioned manufacturing method of the through electrode substrate, the first substrate on which the multilayer wiring structure is formed can be thinned by using the second substrate which is a support substrate for an external device such as a chip. It is possible to omit the step of attaching / peeling the support substrate for the conversion. Further, since the first wiring layer and the insulating layer are exposed after the multilayer wiring structure is formed, the multilayer wiring structure can be formed on a flat substrate that has not been processed.

Further, in another embodiment, the second substrate may have a higher thermal conductivity than the third substrate on which the chip is formed.

According to the above-mentioned manufacturing method of the through electrode substrate, the first substrate on which the multilayer wiring structure is formed can be thinned by using the second substrate which is a heat dissipation plate of an external device such as a chip. It is possible to omit the step of attaching / peeling the support substrate for the conversion.

Further, in another embodiment, a spacer for maintaining the distance between the multilayer wiring structure and the second substrate is further formed in the second region located on the outer peripheral side of the first region of the multilayer wiring structure on which the chip is mounted. You may.

According to the above-mentioned method for manufacturing a through silicon via substrate, the first substrate and the second substrate on which the multilayer wiring structure is formed can be firmly fixed as compared with the structure without spacers. Therefore, in the process of thinning the first substrate, the in-plane uniformity of the thinning can be improved.

Further, in another embodiment, a third bump may be further formed between the multilayer wiring structure and the spacer in the same process as the first bump.

According to the above-mentioned method for manufacturing a through silicon via substrate, the height of the spacer can be reduced by the height at which the third bump is formed, so that the material used for the spacer can be reduced. Further, when forming the spacer, the third bump can be used as an alignment marker.

According to the present invention, it is possible to provide a method for manufacturing a through silicon via substrate, which can reduce the number of steps, shorten the manufacturing period, and improve the yield.

It is sectional drawing which shows the outline of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of irradiating the inside of the 1st substrate with a laser beam in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the alteration layer inside the 1st substrate in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the 1st wiring layer on the alteration layer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the insulating layer on the 1st wiring layer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the seed layer on the 1st wiring layer and the insulating layer in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the resist mask on the seed layer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the plating layer on the seed layer exposed from the resist mask in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of removing the resist mask on the seed layer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of etching the seed layer exposed from the plating layer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the process of forming the multilayer wiring structure on the 1st wiring layer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of mounting the chip which has an electronic circuit on the multilayer wiring structure through the 1st bump in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the process of forming a spacer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of attaching the 2nd substrate to the back surface side of the chip in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of thinning the 1st substrate from the back surface side in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of selectively removing a alteration layer from the back surface side of the 1st substrate in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the outline of the through silicon via substrate which concerns on the modification of one Embodiment of this invention. It is sectional drawing which shows the outline of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the bottom hole in the 1st substrate in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the 1st electrode in the bottomed hole in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the 1st film-like resin which covers the bottom hole on the 1st substrate and 1st electrode in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the 1st opening which exposes the 1st electrode in the 1st film-like resin in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the 1st wiring layer connected to the 1st electrode through the 1st opening in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the process of forming the multilayer wiring structure on the 1st wiring layer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of attaching the 2nd substrate to the back surface side of the chip in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of thinning the 1st substrate from the back surface side in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of removing the 1st electrode and forming a through hole in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the conductive layer connected to the 1st electrode in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the 2nd electrode connected to the 1st electrode in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the 2nd film-like resin which covers the through hole on the 1st substrate and 2nd electrode in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the 2nd opening which exposes a 2nd electrode in the 2nd film-like resin in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the wiring layer connected to the 2nd electrode through the 2nd opening in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the opening which reaches the through hole in the 2nd film-like resin in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the outline of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the 1st wiring layer on the 1st substrate in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the insulating layer on the 1st wiring layer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the process of forming the multilayer wiring structure on the 1st wiring layer in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of attaching the 2nd substrate to the back surface side of the chip in the manufacturing method of the through silicon via substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of thinning the 1st substrate from the back surface side in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing which shows the step of forming the insulating layer which has the opening which exposes the 1st wiring layer in the manufacturing method of the through electrode substrate which concerns on one Embodiment of this invention. It is a figure which shows the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows another example of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows still another example of the semiconductor device which concerns on one Embodiment of this invention.

<Embodiment 1>
Hereinafter, the structure of the through silicon via substrate and the manufacturing method thereof according to the first embodiment of the present invention will be described in detail with reference to the drawings. The embodiments shown below are examples of the embodiments of the present invention, and the present invention is not limited to these embodiments. In the drawings referred to in the present embodiment, the same parts or parts having similar functions are designated by the same reference numerals or similar reference numerals, and the repeated description thereof may be omitted. Further, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing. Further, for convenience of explanation, the terms "upper" and "lower" will be used for explanation, but for example, the vertical relationship between the first substrate and the second substrate may be arranged so as to be reversed from the drawing. Further, in the following description, the first surface and the second surface of the substrate do not refer to a specific surface of the substrate, but specify the front surface direction or the back surface direction of the substrate, that is, to specify the vertical direction with respect to the substrate. It is a name.

[Construction of through silicon via board]
The configuration of the through silicon via substrate according to the first embodiment of the present invention will be described in detail with reference to FIG. In the first embodiment, on one surface (first surface 101 side) of the first substrate 100, a second layer that also functions as a heat dissipation plate for an external device such as a multilayer wiring structure 199, chips 230 and 232, and an external device. A structure in which the substrate 200 is arranged and the second bump 115 connected to the multilayer wiring structure 199 is arranged on the other surface (second surface 102) of the first substrate 100 will be described. However, the structure is not limited to this, and for example, a multilayer wiring structure, an external device, and a heat radiating plate may be arranged on the lower surface of the first substrate 100. Further, the multilayer wiring structure may include elements such as transistors, resistance elements, capacitive elements, diode elements, and coils.

FIG. 1 is a cross-sectional view showing an outline of a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 1, the through electrode substrate 10 according to the first embodiment of the present invention has a first surface 101 and a second surface 102 on the opposite side of the first surface 101, and the first surface 101 and the second surface 101. It has a first substrate 100 provided with a through hole 120 penetrating the surface 102, and a through electrode 110 arranged inside the through hole 120 and connecting the first surface 101 and the second surface 102.

Further, the through electrode substrate 10 is arranged on the first surface 101 of the first substrate 100, is arranged on the first wiring layer 130 connected to the through electrode 110, and is arranged on the first wiring layer 130, and the opening 137 is provided. An insulating layer 139 provided, a wiring layer 140 including a first conductive layer 142 and a second conductive layer 144 arranged on the insulating layer 139 and connected to the first wiring layer 130 via an opening 137, and wiring. An insulating layer 149 arranged on the layer 140 and provided with an opening 147, and a first conductive layer 152 and a second conductive layer arranged on the insulating layer 149 and connected to the wiring layer 140 via the opening 147. The wiring layer 150 including 154, the insulating layer 159 arranged on the wiring layer 150 and provided with the opening 157, and the insulating layer 159 arranged on the insulating layer 159 and connected to the wiring layer 150 via the opening 157. It has a second wiring layer 160 including one conductive layer 162 and a second conductive layer 164, and an insulating layer 169 arranged on the second wiring layer 160 and provided with an opening 167. Here, the plurality of wiring layers and the plurality of insulating layers arranged from the first wiring layer 130 to the second wiring layer 160 are referred to as a multilayer wiring structure 199. The minimum processing dimensions of the first wiring layer 130, the wiring layers 140, 150, and the second wiring layer 160 are L / S (line / space) = 2/2 μm.

Further, the through silicon via substrate 10 has chips 230 and 232 having an electronic circuit and chips 230 and 232 mounted via a first bump 210 connected to the second wiring layer 160 via an opening 167. The outer peripheral side of the first region 201 of the multilayer wiring structure 199 corresponding to the region where the second substrate 200 attached via the adhesive layer 240 and the chips 230 and 232 are mounted on the side opposite to the one bump 210. In the second region 202 located in, the multilayer wiring structure 199 has a spacer 220 for maintaining a distance between the second substrate 200 and the second substrate 200.

[Manufacturing method of through silicon via board]
A method for manufacturing a through silicon via substrate according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 16. In FIGS. 2 to 16, the same elements as those shown in FIG. 1 are designated by the same reference numerals. Here, a manufacturing method when a glass substrate is used as the through silicon via substrate will be described.

FIG. 2 is a cross-sectional view showing a step of irradiating the inside of a first substrate with a laser beam in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. In FIG. 2, by irradiating the first substrate 100 with a femtosecond laser, the material of the first substrate 100 in the region where the through hole 120 is desired to be formed is changed. Here, the laser beam 301 emitted from the light source 300 is incident from the first surface 101 side of the first substrate 100, and focuses on the region where the through hole 120 inside the first substrate 100 is desired to be formed. At the position where the laser beam 301 is focused, high energy is supplied to the first substrate 100, and the material of the first substrate 100 changes to form the altered layer 103.

FIG. 2 illustrates a manufacturing method in which the altered layer 103 is formed in a rectangular shape in a direction orthogonal to the first surface 101 of the first substrate 100, but the manufacturing method is not limited to this manufacturing method. For example, the alteration layer 103 may be formed so that the side wall of the through hole 120 is inclined with respect to a surface orthogonal to the surface of the substrate. More specifically, the altered layer 103 may be formed so as to be trapezoidal in the cross-sectional view so that the diameter of the through hole 120 becomes smaller from the first surface 101 of the first substrate 100 toward the inside of the substrate. .. When the altered layer 103 is formed so that the diameter of the altered layer 103 changes in the depth direction of the first substrate 100, the focal depth of the light source 300 can be scanned in the plate thickness direction while changing the focal size of the laser beam 301. good.

FIG. 3 is a cross-sectional view showing a step of forming a alteration layer inside the first substrate in the method for manufacturing a through silicon via according to an embodiment of the present invention. The shape of the altered layer 103 can be appropriately changed according to the shape of the desired through hole. In the manufacturing method of the first embodiment, the first substrate 100 is thinned from the second surface 102 side to expose the bottom side of the altered layer 103, and the exposed altered layer 103 is etched to form a through hole. 2 and FIG. 3 illustrate a method in which the altered layer 103 is not formed in all directions of the plate thickness of the first substrate 100 (that is, the altered layer 103 is formed in the shape of the bottomed hole). On the other hand, when the through hole 120 is formed only by the step of etching the alteration layer 103 without providing the step of thinning the first substrate 100, the substrate may be entirely altered in the plate thickness direction. Here, since the region of the altered layer 103 becomes the diameter of the through hole later, the diameter of the altered layer may be adjusted according to the desired diameter of the through hole.

FIG. 4 is a cross-sectional view showing a step of forming a first wiring layer on a altered layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 4, a first wiring layer 130 in contact with the altered layer 103 is formed on the first substrate 100. The first wiring layer 130 can be formed by a PVD (Physical Vapor Deposition) method (vacuum deposition method, sputtering method, etc.), a CVD (Chemical Vapor Deposition) method, or a plating method. Further, the first wiring layer 130 may be formed by a single layer or may be formed by stacking.

When the first wiring layer 130 is formed by laminating, a plurality of the above forming methods can be combined. For example, after the first conductive layer is formed by the sputtering method, the second conductive layer can be formed by the plating method using the first conductive layer as a seed layer, and the first conductive layer is laminated by the first conductive layer and the second conductive layer. The wiring layer 130 can be formed. Here, although the altered layer 103 is formed on the first substrate 100, the first surface 101 of the first substrate 100 is not formed with irregularities such as bottomed holes, so that the first wiring layer 130 is formed. There are few restrictions on.

FIG. 5 is a cross-sectional view showing a step of forming an insulating layer on the first wiring layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 5, the insulating layer 139 is formed on the first surface 101 of the first substrate 100 and on the first wiring layer 130. Here, the insulating layer 139 is formed on the entire surface of the substrate so as to cover the pattern end portion of the first wiring layer 130, and an opening 137 that exposes a part of the first wiring layer 130 is provided. The insulating layer 139 can be formed by an inorganic insulating layer using a CVD method or an organic insulating layer using a coating method. Further, the insulating layer 139 may be formed by a single layer or may be formed by laminating.

When the insulating layer 139 is formed by laminating, materials having different properties can be formed depending on the purpose. For example, when a material such as Cu that easily diffuses heat is used as the material of the first wiring layer 130, the insulating layer 139 is made of a first inorganic insulating layer, a second inorganic insulating layer, and a layer having different properties of the organic insulating layer. A laminated structure can be used. As the first inorganic insulating layer, a layer having a property of suppressing thermal diffusion of Cu can be formed on the first wiring layer 130 by a CVD method. Further, as the second inorganic insulating layer, a layer having better adhesion to the organic insulating layer than the first inorganic insulating layer can be formed on the first inorganic insulating layer by the CVD method. Further, as the organic insulating layer, the step formed by the pattern of the first wiring layer 130 can be relaxed or flattened, and a layer having a low dielectric constant can be formed on the second inorganic insulating layer by a coating method. Here, a photosensitive resin or a non-photosensitive resin can be used as the organic insulating layer.

FIG. 6 is a cross-sectional view showing a step of forming a seed layer on the first wiring layer and the insulating layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 6, a seed layer 325, which will later become the first conductive layer 142, is formed on the insulating layer 139 and on the first wiring layer 130 exposed at the bottom of the opening 137. The seed layer 325 can be formed by a PVD method, a CVD method, or the like. As the material used for the seed layer 325, the same material as the plating layer 326 formed on the seed layer 325 later can be selected. The seed layer 325 is used as a seed in the electrolytic plating method when the plating layer 326 is formed in a later step. Here, the seed layer 325 is preferably formed with a film thickness of 20 nm or more and 1 μm or less. Further, the seed layer 325 is more preferably formed with a film thickness of 100 nm or more and 300 nm or less.

FIG. 7 is a cross-sectional view showing a step of forming a resist mask on a seed layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 7, a resist pattern 329 is formed by applying a photoresist on the seed layer 325 and then exposing and developing the resist. The resist pattern 329 is formed so as to expose at least the region where the pattern of the wiring layer 140 shown in FIG. 1 is formed.

FIG. 8 is a cross-sectional view showing a step of forming a plating layer on a seed layer exposed from a resist mask in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 8, after forming the resist pattern 329, the seed layer 325 is energized to perform an electrolytic plating method, and the pattern of the wiring layer 140 shown in FIG. 1 is placed on the seed layer 325 exposed from the resist pattern 329. The plating layer 326 is formed in the region where the plating layer is formed.

FIG. 9 is a cross-sectional view showing a step of removing a resist mask on a seed layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 9, after forming the plating layer 326, the photoresist constituting the resist pattern 329 is removed with an organic solvent. For removing the photoresist, ashing with oxygen plasma can be used instead of using an organic solvent.

FIG. 10 is a cross-sectional view showing a step of etching a seed layer exposed from a plating layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 10, each wiring is electrically separated by removing (etching) the seed layer 325 in the region covered by the resist pattern 329 and on which the plating layer 326 was not formed. Since the surface of the plating layer 326 is also etched and thinned by etching the seed layer 325, it is preferable to set the film thickness of the plating layer 326 in consideration of the influence of this thinning. Wet etching or dry etching can be used as the etching in this step. By this step, the first conductive layer 142 formed from the seed layer 325 and the second conductive layer 144 formed from the plating layer 326 are formed, and the wiring layer 140 is formed.

FIG. 11 is a cross-sectional view showing a step of forming a multilayer wiring structure on a first wiring layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. By repeating the steps shown in FIGS. 5 to 10 for the structure shown in FIG. 10, the wiring layer 150 (the first conductive layer 152 and the second conductive layer 154 are laminated on the wiring layer 140 via the insulating layer 149). (Structure) is formed, and a second wiring layer 160 (a laminated structure of a first conductive layer 162 and a second conductive layer 164) is formed on the wiring layer 150 via an insulating layer 159. Further, an insulating layer 169 having an opening 167 provided at a position corresponding to an external terminal of the chip 230 and 232 is formed on the second wiring layer 160. That is, by the steps shown in FIGS. 4 to 11, the first wiring layer 130 is electrically connected to the first wiring layer 130 via the plurality of insulating layers and the plurality of wiring layers on the first substrate 100. A multi-layer wiring structure 199 having two wiring layers 160 is formed.

FIG. 12 is a cross-sectional view showing a step of mounting a chip having an electronic circuit on a multilayer wiring structure via a first bump in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 12, the first bump 210 in contact with the second wiring layer 160 is formed through the opening 167. The first bump 210 is provided at a position corresponding to the external terminal of the chips 230 and 232. Further, chips 230 and 232 having electronic circuits such as logic circuits and memory circuits are mounted on the multilayer wiring structure 199 via the first bump 210. Here, the chips 230 and 232 include a third substrate and an electronic circuit formed on the third substrate. When the external terminals of the chips 230 and 232 are arranged on the surface side where the electronic circuit of the third substrate is formed, they are mounted in a face-down manner so that the external terminals come into contact with the first bump 210.

FIG. 13 is a cross-sectional view showing a step of forming a spacer in the method for manufacturing a through silicon via according to an embodiment of the present invention. As shown in FIG. 13, the spacer 220 is formed on the insulating layer 169 on the outer peripheral side of the region where the chips 230 and 232 are arranged. In other words, the spacer 220 is the multilayer wiring structure 199 and the second shown in FIG. 1 in the second region 202 located on the outer peripheral side of the first region 201 of the multilayer wiring structure 199 on which the chips 230 and 232 are mounted. The distance from the substrate 200 is maintained.

Here, the spacer 220 is formed so that the height of the spacer 220 is substantially the same as the height of the chips 230 and 232 (the height of the back surface of the third substrate). The spacer 220 can be formed only in a required region of the second region 202 by a dip method or the like. Here, in FIG. 13, the second region 202 corresponds to the outer circumference of the first substrate 100, but is not limited to this example. For example, the spacer 220 may be formed in the region between the chip 230 and the chip 232. Further, the spacer 220 may be continuously formed so as to surround the outer periphery of the first region 201. On the other hand, the spacer 220 may be formed discretely in the second region 202.

FIG. 14 is a cross-sectional view showing a step of attaching a second substrate to the back surface side of the chip in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 14, the second substrate 200 is attached to the side of the chips 230 and 232 opposite to the first bump 210 via the adhesive layer 240.

Here, the adhesive layer 240 has heat resistance to the process after the second substrate 200 is attached. For example, the adhesive layer 240 may have heat resistance to the reflow temperature of the through silicon via 110 and the second bump 115 shown in FIG. More specifically, the adhesive layer 240 may have a heat resistance of 250 ° C. or higher. Here, the fact that the adhesive layer 240 has heat resistance means that the shape change or physical property change of the adhesive layer 240 does not occur due to the heat treatment.

Further, the second substrate 200 can be made of a material having high thermal conductivity. For example, the second substrate 200 may have a higher thermal conductivity than the third substrate on which the chips 230 and 232 are formed. More specifically, a metal plate can be used as the second substrate 200. As the above-mentioned metal plate, a metal plate having a high thermal conductivity such as a copper plate can be used as the second substrate 200. Here, in order to suppress the generation of internal stress due to thermal shrinkage, the coefficient of thermal expansion of the second substrate 200 is close to the coefficient of thermal expansion of the third substrate on which the chips 230 and 232 are formed. Can be used.

Further, when the spacer 220 is continuously formed so as to surround the outer periphery of the first region 201, the space sealed by the first substrate 100 (multilayer wiring structure 199), the second substrate 200, and the spacer 220 is formed. It may be filled with an inert gas. Alternatively, the space may be in a vacuum state or a reduced pressure state.

FIG. 15 is a cross-sectional view showing a step of thinning the first substrate from the back surface side in the method for manufacturing a through silicon via according to an embodiment of the present invention. As shown in FIG. 15, the first substrate 100 is thinned by the first etching from the second surface 102 side opposite to the multilayer wiring structure 199 of the first substrate 100. For the first etching, for example, wet etching or CMP (Chemical Mechanical Polishing) can be used. Here, FIG. 15 illustrates a manufacturing method in which the first substrate 100 is thinned until the altered layer 103 is exposed by the first etching, but the first etching is not limited to this manufacturing method, and the altered layer 103 is used in the first etching. It is not necessary to thin the first substrate 100 until it is exposed. That is, the first etching may be performed so that the plate thickness of the first substrate 100 after thinning is thicker than the depth of the altered layer 103. In this case, a dicing method or a grinding method can be used as the first etching. That is, as the first etching, rough cutting capable of thinning the substrate at high speed can be used.

When wet etching is used for thinning, hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), surfactant-added buffered hydrofluoric acid (LAL) and the like can be used. The chemical solution used for etching can be appropriately selected depending on the material of the substrate. When CMP is used for thinning, cerium oxide (ceria) can be used as an abrasive. CMP using ceria can polish glass and silicon oxide at high speed. Ceria has not only a mechanical polishing action but also an action of chemically polishing silicon oxide by acting together with water, and a high polishing rate can be obtained.

FIG. 16 is a cross-sectional view showing a step of selectively removing a altered layer from the back surface side of the first substrate in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 16, similarly to the first etching, the altered layer 103 is selectively removed by the second etching from the side opposite to the multilayer wiring structure 199 of the first substrate 100, and penetrates the first substrate 100. A through hole 120 that exposes the first wiring layer 130 is formed. Wet etching can be used for the second etching. Here, the second etching may have the same etching conditions as the first etching, or may have different etching conditions from the first etching. When the second etching is processed under the same conditions as the first etching, the first etching and the second etching may be continuously processed. That is, the first etching and the second etching may be performed in the same step, and the through hole may be formed by thinning the first substrate 100 and selective etching of the altered layer 103 under one etching condition.

Then, the through electrode substrate 10 shown in FIG. 1 can be formed by forming the through electrode 110 and the second bump 115 connected to the first wiring layer 130 in the through hole 120 shown in FIG. Here, the through silicon via 110 and the second bump 115 may be formed in the same process or may be formed in different configurations. When the through silicon via 110 and the second bump 115 are formed in the same process, they may be formed by a plating method using the first wiring layer 130 as a seed layer, or the second surface of the first substrate 100 by a method such as a solder plating method. It may be formed from the 102 side.

[Material of each member of the through silicon via board]
The material of each member (each layer) included in the through silicon via substrate 10 shown in FIG. 1 will be described in detail.

A glass substrate can be used as the first substrate 100. In addition to the glass substrate, an insulating substrate such as a quartz substrate, a sapphire substrate, or a resin substrate, a silicon substrate, a silicon carbide substrate, a semiconductor substrate such as a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate can be used. .. Further, as the material used for the substrate, a material having a coefficient of thermal expansion in the range of 2 × 10 ^-6 [/ K] or more and 17 × 10 ^-6 [/ K] or less can be used. Further, these may be laminated. The thickness of the first substrate 100 before thinning is not particularly limited, but for example, a substrate having a thickness of 100 μm or more and 800 μm or less can be used. The thickness of the first substrate 100 is more preferably 200 μm or more and 400 μm or less. When the substrate becomes thinner than the lower limit of the thickness of the substrate, the deflection of the substrate increases. As a result, handling in the manufacturing process becomes difficult, and the substrate warps due to the internal stress of the thin film or the like formed on the substrate. Further, when the substrate becomes thicker than the upper limit of the thickness of the substrate, the step of forming the through hole becomes longer. As a result, the manufacturing process becomes longer and the manufacturing cost rises.

For the first wiring layer 130 and the first conductive layers 142, 152, 162, a conductive material having good adhesion to the underlying first substrate 100 or the insulating layer 139, 149, 159 can be used. For example, titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), nickel (Ni), chromium (Cr), aluminum (Al), these compounds, or alloys thereof can be used. can. In particular, when the second conductive layers 144, 154, and 164 formed on the first conductive layers 142, 152, 162 contain copper (Cu), the first conductive layers 142, 152, 162 diffuse Cu. A material to suppress can be used, and for example, titanium nitride (TiN), molybdenum nitride (MoN), tantalum nitride (TaN) and the like may be used. Here, the thicknesses of the first conductive layers 142, 152, and 162 are not particularly limited, but can be appropriately selected, for example, in the range of 50 nm or more and 400 nm or less.

As the second conductive layer 144, 154, 164, a conductive material having good adhesion to the first conductive layers 142, 152, 162 and having high electric conductivity can be used. For example, metals such as copper (Cu), gold (Au), silver (Ag), platinum (Pt), rhodium (Rh), tin (Sn), aluminum (Al), nickel (Ni), chromium (Cr) or It can be selected from alloys using these.

As the insulating layer 139, 149, 159, 169, an inorganic insulating layer, an organic insulating layer, or a laminated structure of an inorganic insulating layer and an organic insulating layer can be used.

Examples of the inorganic insulating layer include silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride carbide (SiCN), and carbon. Additive silicon oxide (SiOC) or the like can be used. Here, as the insulating layer 139, 149, 159, 169, the above-mentioned inorganic insulating layer may be used as a single layer or may be used in a laminated manner.

Examples of the organic insulating layer include polyimide, epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluororesin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, and BT. Resin, FR-4, FR-5, Polyacetal, Polybutylene terephthalate, Syndiotactic polystyrene, Polyphenylene sulfide, Polyether ether ketone, Polyether nitrile, Polycarbonate, Polyphenylene ether Polysulfone, Polyether sulfone, Polyarylate, Polyetherimide Etc. can be used. Further, an inorganic filler such as glass, talc, mica, silica, or alumina may be used in combination with the above resin. Here, as the resin used for the insulating layer 139, 149, 159, 169, a resin having a Young's modulus of 1 × 10 ⁹ [dyne / cm ² ] or less at room temperature may be used for the purpose of stress relaxation. ..

As the first bump 210 and the second bump 115, materials having high uniformity in height and shape and high conductivity can be used. For example, it can be selected from metals such as Au, Ag, Cu, Ni, and solder, or alloys using these.

As the adhesive layer 240, a material having sufficient adhesive strength with the chips 230, 232 and the second substrate 200 and having high thermal conductivity can be used.

As the second substrate 200, a material having high thermal conductivity can be used. For example, a material containing Cu can be used.

As described above, according to the method for manufacturing a through electrode substrate according to the first embodiment, the multilayer wiring structure 199 is formed by using the second substrate 200 which is a support substrate for an external device such as chips 230 and 232. Since 1 substrate 100 can be thinned, the step of attaching / peeling the support substrate for thinning can be omitted. Further, by forming the altered layer 103 in the region where the through hole 120 of the first substrate 100 is desired to be formed, forming the multilayer wiring structure 199, and then removing the altered layer 103, the multilayer wiring structure 199 is not processed and is flat. Can be formed on a flexible substrate. As a result, it is possible to provide a method for manufacturing a through silicon via substrate, which can reduce the number of steps, shorten the manufacturing period, and improve the yield.

Further, by using a substrate made of a material having high thermal conductivity such as a heat sink as the second substrate 200, the heat generated by driving the circuits of the chips 230 and 232 can be efficiently discharged to the outside. Further, by setting the etching conditions of the first etching and the etching conditions of the second etching to be the same etching conditions, it is possible to thin the first substrate 100 and form the through holes 120 in one step.

Further, by forming the spacer 220 in the second region 202, it is possible to firmly fix the first substrate and the second substrate on which the multilayer wiring structure is formed as compared with the structure without the spacer. Therefore, in the process of thinning the first substrate, the in-plane uniformity of the thinning can be improved. Further, by filling the space sealed by the first substrate 100, the second substrate 200, and the spacer 220 with an inert gas, or by putting the space in a vacuum state or a depressurized state, the first bump 210 and the chips 230, 232. Is less likely to come into contact with oxygen and moisture, so that the problem of high resistance due to oxidation of the conductive material can be suppressed.

<Modification 1 of Embodiment 1>
FIG. 17 is a cross-sectional view showing an outline of a through silicon via substrate according to a modified example of the embodiment of the present invention. The through silicon via 11 according to the first modification of the first embodiment shown in FIG. 17 is similar to the through silicon via 10 shown in FIG. 1, but the through silicon via 11 has a cross-sectional structure of a region in which the spacer 220 is arranged. , The via silicon via substrate 10 is different from the through silicon via substrate 10 in that it has the same cross-sectional structure as the region where the first bump 210 is formed in the region where the chips 230 and 232 are formed.

As shown in FIG. 17, the through silicon via substrate 11 has a third bump 222 formed between the multilayer wiring structure 199 and the spacer 220 in the same process as the first bump 210. Further, in the second region 202 where the third bump 222 is formed, the first conductive layer 224 formed in the same process as the first conductive layer 162 and the second conductive layer 224 formed in the same process as the second conductive layer 164. It has a conductive layer 226. Then, the third bump 222 has an opening provided in the insulating layer 169, similar to the structure of the region in which the second wiring layer 160 and the first bump 210 are arranged in the first region 201 in which the chips 230 and 232 are arranged. It is in contact with the second conductive layer 226 via the portion 227.

<Embodiment 2>
The structure of the through silicon via substrate and the method for manufacturing the through silicon via substrate according to the second embodiment of the present invention will be described in detail with reference to FIGS. 18 to 33. In the through silicon via substrate 20 according to the second embodiment, the same parts as those of the through silicon via substrate 10 shown in FIG. 1 or the parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

[Construction of through silicon via board]
The through electrode substrate 20 shown in FIG. 18 is similar to the through electrode substrate 10 shown in FIG. 1, but the through electrode substrate 20 is a conformal through hole formed in the through hole 120 provided in the first substrate 100. The first surface of the first substrate 100 is connected to the first electrode 332 formed on the first surface 101 of the first substrate 100 and the second electrode 334 formed on the second surface 102 by the electrode 330. The first film-like resin 310 is formed as an insulating layer on the 101, the second film-like resin 320 is formed as an insulating layer on the second surface 102, and the second surface 102 side of the first substrate 100. It differs from the through electrode substrate 10 in the connection structure between the formed second bump 350 and the through electrode 330.

Here, the connection structure between the second bump 350 formed on the second surface 102 side of the first substrate 100 and the through electrode 330 will be described in detail. The second film-like resin 320 formed on the second surface 102 side of the first substrate 100 has a second opening 327 that exposes the second electrode 334 and an opening 324 that is provided corresponding to the through hole 120. It is provided. That is, the through hole 120 is connected to the outside through the opening 324. Further, on the second surface 102 side of the first substrate 100, a wiring layer 340 including the first conductive layer 342 and the second conductive layer 344 connected to the second electrode 334 via the second opening 327 is formed. ing. A second bump 350 is formed on the lower surface of the wiring layer 340.

FIG. 18 illustrates a structure in which the second bump 350 is connected to the second electrode 334 via the wiring layer 340, but the structure is not limited to this. For example, the wiring layer 340 may not be arranged, the second bump 350 may be arranged in the second opening 327 of the second film-like resin 320, and the structure may be in contact with the second electrode 334. Further, if the second bump 350 and the through electrode 330 can be brought into contact with each other when the wiring layer 340 or the wiring layer 340 is not arranged, the second electrode 334 may not be provided.

[Manufacturing method of through silicon via board]
A method for manufacturing the through silicon via 20 according to the second embodiment of the present invention will be described with reference to FIGS. 19 to 33. In FIGS. 19 to 33, the same elements as those shown in FIG. 1 are designated by the same reference numerals. Since the manufacturing method of the through silicon via substrate 20 is similar to the manufacturing method of the through silicon via substrate 10 shown in FIG. 1, detailed description thereof will be omitted, and the points different from the manufacturing method of the through silicon via substrate 10 will be described in detail. do. Here, a manufacturing method when a glass substrate is used as the through silicon via substrate will be described.

FIG. 19 is a cross-sectional view showing a step of forming a bottomed hole in the first substrate in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 19, a bottomed hole 105 is formed on the first surface 101 side of the first substrate 100. The bottomed hole 105 is formed by forming a altered layer in a region where the bottomed hole 105 of the first substrate 100 is to be formed and selectively etching the altered layer, as in the steps of FIGS. 2 and 3. be able to.

Here, as a method of forming the bottomed hole 105, a altered layer is formed by irradiating a region of the first substrate 100 where the bottomed hole 105 is desired to be formed with a laser beam, and the bottomed hole is formed by wet etching with a chemical solution. The method of forming has been described, but the method is not limited to this method. For example, a bottomed hole or a through hole may be formed by irradiating the first substrate 100 with a high-power laser and melting the substrate. For example, a CO ₂ laser or the like can be used as a laser for processing a glass substrate.

FIG. 20 is a cross-sectional view showing a step of forming a first electrode inside a bottomed hole in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 20, a first electrode 332 and a through electrode 330 are formed in a part of the surface of the first substrate 100 on the first surface 101 side and inside the bottomed hole 105. The first electrode 332 and the through electrode 330 can be formed by a PVD method, a CVD method, or a plating method. Further, the first electrode 332 and the through electrode 330 may be formed of a single layer or may be formed of a laminated layer. Here, the first electrode 332 and the through electrode 330 are continuous layers formed by the same process, but for convenience of explanation, the conductive layer formed on the first surface 101 of the first substrate 100 is referred to as the first electrode 332. It is expressed only that the conductive layer formed inside the bottomed hole 105 is expressed as the through electrode 330, and the "first electrode 332" and the "through electrode 330" are clearly distinguished as different members. is not it. That is, the through electrode may be expressed as the first electrode.

FIG. 21 is a cross-sectional view showing a step of forming a first film-like resin covering a bottomed hole on a first substrate and on the first electrode in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. .. As shown in FIG. 21, a film-shaped first film-shaped resin 310 covering the bottomed hole 105 is attached onto the first substrate 100 and the first electrode 332. Here, the film-like resin is a film of 1 μm or more and 100 μm or less, and is a resin that has been in the form of a film before being formed on the substrate. The film-like resin can also be referred to as a sheet-like resin or a laminated resin. Since the film-like resin is in the form of a film even before it is formed on the substrate, the resin hardly falls into the bottomed hole 105 even if it is formed on the bottomed hole 105, and the end portion of the bottomed hole 105 is formed. To form a hollow structure.

FIG. 22 is a cross-sectional view showing a step of forming a first opening in which the first electrode is exposed in the first film-like resin in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 22, a first opening 317 that exposes the first electrode 332 is formed in the first film-shaped resin 310. The first opening 317 may be formed by a photolithography step and an etching step, or may be formed by sublimating the resin using an energy ray such as a laser.

FIG. 23 is a cross-sectional view showing a step of forming a first wiring layer connected to a first electrode via a first opening in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 23, a first wiring layer including a first conductive layer 132 and a second conductive layer 134 on a first film-like resin 310 and on a first electrode 332 exposed at the bottom of the first opening 317. Form 130. In other words, the first wiring layer 130 is connected to the first electrode 332 via the first opening 317.

FIG. 24 is a cross-sectional view showing a step of forming a multilayer wiring structure on a first wiring layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 24, by repeating the steps shown in FIGS. 5 to 10 with respect to the structure shown in FIG. 23, the wiring layer 150 (first conductive layer) is placed on the first wiring layer 130 via the insulating layer 139. The laminated structure of 152 and the second conductive layer 154) is formed, and the second wiring layer 160 (the laminated structure of the first conductive layer 162 and the second conductive layer 164) is formed on the wiring layer 150 via the insulating layer 159. .. Further, an insulating layer 169 having an opening 167 provided at a position corresponding to an external terminal of the chip 230 and 232 is formed on the second wiring layer 160. That is, on the first substrate 100, the first wiring layer 130 in contact with the first electrode 332 and the second wiring layer 160 electrically connected to the first wiring layer 130 via the plurality of insulating layers and the plurality of wiring layers. And to form a multi-layer wiring structure 199 having.

FIG. 25 is a cross-sectional view showing a step of attaching a second substrate to the back surface side of the chip in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 25, the first bump is in contact with the second wiring layer 160 through the opening 167 and is provided at a position corresponding to the external terminal of the chip 230 and 232 having an electronic circuit such as a logic circuit and a memory circuit. The 210 is formed, and the chips 230 and 232 are mounted on the multilayer wiring structure 199 via the first bump 210 in contact with the second wiring layer 160. Further, the second substrate 200 is attached to the opposite side of the chips 230 and 232 from the first bump 210 via the adhesive layer 240.

FIG. 26 is a cross-sectional view showing a step of thinning the first substrate from the back surface side in the method for manufacturing a through silicon via according to an embodiment of the present invention. As shown in FIG. 26, the first substrate 100 is thinned from the second surface 102 side opposite to the multilayer wiring structure 199 of the first substrate 100. Wet etching or CMP can be used as a method for thinning the first substrate 100. The first substrate 100 is thinned until a part of the through electrode 330 formed at the bottom of the bottom hole 105 is exposed by thinning the first substrate 100.

As described above, in the step of exposing a part of the through electrode 330 formed at the bottom of the bottom hole 105 by thinning the first substrate 100, the through electrode 330 has a function of a stopper for the thinning process. May be. For example, when thinning a plate using HF, a material that is not etched by HF or has an etching rate for HF lower than that of the first substrate 100 can be used as the through electrode 330, such as Ti, TiN, Mo, and MoN. Can be used.

FIG. 27 is a cross-sectional view showing a step of removing a first electrode to form a through hole in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 27, the portion of the through silicon via 330 shown in FIG. 26 that protrudes downward from the second surface 102 of the first substrate 100 is removed. Dry etching, wet etching, or CMP can be used as a step of removing a part of the through electrode 330. By this step, the through electrode 330 may be etched so as to be in a surface position with the second surface 102 of the first substrate 100, or may have a concave shape (a shape having an upward recess) with respect to the second surface 102. It may be a convex shape (a shape protruding downward) with respect to the second surface 102. By this step, a through hole is formed which penetrates the first surface 101 and the second surface 102 of the first substrate 100 and exposes the through electrode 330 (or the first electrode).

FIG. 28 is a cross-sectional view showing a step of forming a conductive layer connected to a first electrode in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 28, the conductive layer 339 connected to the through electrode 330 (or the first electrode) is formed from the second surface 102 side of the first substrate 100. In other words, a conductive layer 339 connected to the through electrode 330 (or the first electrode) is formed on the thinned side of the first substrate 100. The conductive layer 339 can be formed by a PVD method, a CVD method, or a plating method. Further, the conductive layer 339 may be formed by a single layer or may be formed by laminating.

FIG. 29 is a cross-sectional view showing a step of forming a second electrode connected to the first electrode in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 29, the conductive layer 339 of FIG. 29 is processed by a photolithography step and an etching step to form a second electrode 334. In other words, the second electrode 334 connected to the through electrode 330 (or the first electrode) is formed on the thinned side of the first substrate 100 by the steps shown in FIGS. 28 and 29. Here, the second electrode 334 is processed into a pattern that electrically separates each of the plurality of through electrodes 330.

FIG. 30 is a cross-sectional view showing a step of forming a second film-like resin covering the through holes on the first substrate and the second electrode in the method for manufacturing the through electrode substrate according to the embodiment of the present invention. As shown in FIG. 30, a film-like material covering the second electrode 334 and the through hole 120 on the second surface 102 side of the first substrate 100 on which the second electrode 334 is formed, that is, on the thinned side of the first substrate 100. The second film-like resin 320 is attached. Here, as the second film-like resin 320, the same one as that of the first film-like resin 310 can be used. Since the film-like resin is in the form of a film even before it is formed on the substrate, even if it is formed on the through hole 120, the resin hardly falls into the through hole 120 and covers the end portion of the through hole 120. Form a hollow structure.

FIG. 31 is a cross-sectional view showing a step of forming a second opening in which the second electrode is exposed in the second film-like resin in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 31, a second opening 327 that exposes the second electrode 334 is formed in the second film-shaped resin 320. The second opening 327 may be formed by a photolithography step and an etching step, or may be formed by sublimating the resin using an energy ray such as a laser.

FIG. 32 is a cross-sectional view showing a step of forming a wiring layer connected to a second electrode via a second opening in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 32, a wiring layer including a first conductive layer 342 and a second conductive layer 344 under the second film-like resin 320 and under the second electrode 334 exposed at the bottom of the second opening 327. Form 340. As shown in FIG. 18, the wiring layer 340 is provided at a position corresponding to the second bump 350 formed on the second surface 102 side of the first substrate 100. The pattern of the wiring layer 340 is determined according to the alignment accuracy when forming the second bump 350 and the diameter of the second bump 350.

FIG. 33 is a cross-sectional view showing a step of forming an opening reaching a through hole in the second film-like resin in the method for manufacturing a through electrode substrate according to an embodiment of the present invention. As shown in FIG. 33, an opening 324 that reaches the through hole 120 is provided at a position corresponding to the through hole 120 of the second film-shaped resin 320. In FIG. 33, a structure in which the diameter of the opening 324 is substantially the same as the diameter of the through hole 120 is illustrated, but the structure is not limited to this structure. For example, the diameter of the opening 324 may be larger than the diameter of the through hole 120, or conversely smaller. The opening 324 may be formed by a photolithography step and an etching step, or may be formed by sublimating the resin using an energy ray such as a laser.

By connecting the through hole 120 and the outside through the opening 324, for example, even when the gas desorbed from each member constituting the through electrode substrate reaches the inside of the through hole 120. , The gas is released to the outside through the opening 324. Therefore, it is possible to avoid the problem that the gas fills and the internal pressure inside the through hole 120 rises and explodes, which occurs when the through hole 120 is sealed with another member.

Then, by forming the second bump 350 on the wiring layer 340 (second conductive layer 344) shown in FIG. 33, the through silicon via substrate 20 shown in FIG. 18 can be formed. Here, the second bump 350 is connected to the second electrode 334 via the wiring layer 340 in the second opening 327 provided in the second film-like resin 320, and further connected to the first electrode via the through electrode 330. It is connected to 332. In other words, the second bump 350 is electrically connected to the first electrode 332 via the second opening 327. Here, the second bump 350 may be formed by a plating method using the wiring layer 340 as a seed layer, or may be formed from the second surface 102 side of the first substrate 100 by a method such as a solder plating method.

As described above, according to the method for manufacturing a through electrode substrate according to the second embodiment, the multilayer wiring structure 199 is formed by using the second substrate 200 which is a support substrate for an external device such as chips 230 and 232. Since 1 substrate 100 can be thinned, the step of attaching / peeling the support substrate for thinning can be omitted.

Further, by using a substrate made of a material having high thermal conductivity such as a heat sink as the second substrate 200, the heat generated by driving the circuits of the chips 230 and 232 can be efficiently discharged to the outside. Further, by attaching the first film-like resin 310 so as to cover the bottomed hole 105 formed in the first substrate 100, the step formed by the bottomed hole 105 can be alleviated. Similarly, by attaching the second film-like resin 320 so as to cover the through hole 120 formed in the first substrate 100, the step formed by the through hole 120 can be alleviated.

Further, by forming the spacer 220 in the second region 202, the first substrate and the second substrate on which the multilayer wiring structure is formed can be firmly fixed as compared with the structure without the spacer. Therefore, in the process of thinning the first substrate, the in-plane uniformity of the thinning can be improved. Further, by filling the space sealed by the first substrate 100, the second substrate 200, and the spacer 220 with an inert gas, or by putting the space in a vacuum state or a depressurized state, the first bump 210 and the chips 230, 232. Is less likely to come into contact with oxygen and moisture, so that the problem of high resistance due to oxidation of the conductive material can be suppressed. Further, by arranging the second electrode 334 connected to the through electrode 330, the second opening 327 of the second film-like resin 320 may be provided so as to expose the second electrode 334. Therefore, the second electrode may be provided. By adjusting the pattern of 334, the alignment accuracy of the second opening 327 can be loosened.

<Embodiment 3>
The structure of the through silicon via substrate and the method for manufacturing the through silicon via substrate according to the third embodiment of the present invention will be described in detail with reference to FIGS. 34 to 40. In the through silicon via substrate 30 according to the third embodiment, the same parts as those of the through silicon via substrate 10 shown in FIG. 1 or the parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

[Construction of through silicon via board]
The through electrode substrate 30 shown in FIG. 34 is similar to the through electrode substrate 10 shown in FIG. 1, but the through electrode substrate 30 is different from the through electrode substrate 10 in that the first substrate 100 is removed. ..

Here, in FIG. 34, an insulating layer 410 provided with an opening 417 that exposes the first wiring layer 130 is arranged under the first wiring layer 130 and the insulating layer 139, and the second bump 115 has an opening. It is connected to the first wiring layer 130 via the portion 417. FIG. 34 illustrates a structure in which the insulating layer 410 is arranged between the first wiring layer 130 and the insulating layer 139 and the second bump 115, but the structure is not limited to this. For example, the insulating layer 410 may not be arranged.

[Manufacturing method of through silicon via board]
A method for manufacturing the through silicon via 30 according to the third embodiment of the present invention will be described with reference to FIGS. 35 to 41. In FIGS. 35 to 41, the same elements as those shown in FIG. 1 are designated by the same reference numerals. Since the manufacturing method of the through silicon via substrate 30 is similar to the manufacturing method of the through silicon via substrate 10 shown in FIG. 1, detailed description thereof will be omitted, and the points different from the manufacturing method of the through silicon via substrate 10 will be described in detail. do. Here, a manufacturing method when a glass substrate is used as the through silicon via substrate will be described.

FIG. 35 is a cross-sectional view showing a step of forming a first wiring layer on a first substrate in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 35, the first substrate 100 is prepared, and the first wiring layer 130 is formed on the first surface 101 side of the first substrate 100.

FIG. 36 is a cross-sectional view showing a step of forming an insulating layer on the first wiring layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 36, the insulating layer 139 is formed on the first surface 101 of the first substrate 100 and on the first wiring layer 130. Here, the insulating layer 139 is formed on the entire surface of the substrate so as to cover the pattern end portion of the first wiring layer 130. Further, the insulating layer 139 is provided with an opening 137 that exposes a part of the first wiring layer 130. The insulating layer 139 can be formed by an inorganic insulating layer using a CVD method or an organic insulating layer using a coating method. Further, the insulating layer 139 may be formed by a single layer or may be formed by laminating.

FIG. 37 is a cross-sectional view showing a step of forming a multilayer wiring structure on a first wiring layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 37, by repeating the steps shown in FIGS. 5 to 10 with respect to the structure shown in FIG. 36, the wiring layer 140 (first conductive layer) is placed on the first wiring layer 130 via the insulating layer 139. 142 and the laminated structure of the second conductive layer 144) are formed, and the wiring layer 150 (the laminated structure of the first conductive layer 152 and the second conductive layer 154) is formed on the wiring layer 140 via the insulating layer 149, and the wiring is performed. A second wiring layer 160 (a laminated structure of the first conductive layer 162 and the second conductive layer 164) is formed on the layer 150 via the insulating layer 159. Further, an insulating layer 169 having an opening 167 provided at a position corresponding to an external terminal of the chip 230 and 232 is formed on the second wiring layer 160. That is, by the above steps, the first wiring layer 130 and the second wiring layer 160 electrically connected to the first wiring layer 130 via the plurality of insulating layers and the plurality of wiring layers are provided on the first substrate 100. , To form a multi-layer wiring structure 199 with.

FIG. 38 is a cross-sectional view showing a step of attaching a second substrate to the back surface side of the chip in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 38, the first bump is in contact with the second wiring layer 160 through the opening 167 and is provided at a position corresponding to the external terminal of the chip 230 and 232 having an electronic circuit such as a logic circuit and a memory circuit. The 210 is formed, and the chips 230 and 232 are mounted on the multilayer wiring structure 199 via the first bump 210 in contact with the second wiring layer 160. Further, the second substrate 200 is attached to the opposite side of the chips 230 and 232 from the first bump 210 via the adhesive layer 240.

FIG. 39 is a cross-sectional view showing a step of thinning the first substrate from the back surface side in the method for manufacturing a through silicon via according to an embodiment of the present invention. As shown in FIG. 39, the first substrate 100 is thinned from the second surface 102 side opposite to the multilayer wiring structure 199 of the first substrate 100, and the first wiring layer 130 and the insulating layer 139 are exposed. Here, FIG. 39 illustrates a manufacturing method in which the first substrate 100 is thinned and the first substrate 100 is completely removed, but the present invention is not limited to this manufacturing method. Here, in order to make the first substrate 100 thinner, at least the first wiring layer 130 may be exposed, and it is not necessary to remove all the first substrate 100.

FIG. 40 is a cross-sectional view showing a step of forming an insulating layer having an opening that exposes a first wiring layer in the method for manufacturing a through silicon via substrate according to an embodiment of the present invention. As shown in FIG. 40, the insulating layer 410 is formed under the exposed first wiring layer 130 and the insulating layer 139. As shown in FIG. 34, the insulating layer 410 is formed with an opening 417 at a position corresponding to the first wiring layer 130 and the second bump 115.

Then, by forming the second bump 115 in the opening 417 shown in FIG. 40, the through electrode substrate 30 shown in FIG. 34 can be formed. Here, the second bump 115 is connected to the first wiring layer 130 via the opening 417. Here, the second bump 115 may be formed by a plating method using the first wiring layer 130 as a seed layer, or may be formed in the opening 417 of the insulating layer 410 by a method such as a solder plating method.

As described above, according to the method for manufacturing the through electrode substrate 30 according to the third embodiment, the multilayer wiring structure 199 is formed by using the second substrate 200 which is a support substrate for an external device such as chips 230 and 232. Since the first substrate 100 can be made into a thin plate, the step of attaching / peeling the support substrate for making the thin plate can be omitted. Further, since the first wiring layer 130 and the insulating layer 139 are exposed after the multilayer wiring structure 199 is formed, the multilayer wiring structure 199 can be formed on the unprocessed flat first substrate 100. Therefore, it is not necessary to add an extra step such as flattening the step, and the through electrode substrate can be formed.

Further, by using a substrate made of a material having high thermal conductivity such as a heat sink as the second substrate 200, the heat generated by driving the circuits of the chips 230 and 232 can be efficiently discharged to the outside. Further, by forming the spacer 220 in the second region 202, the first substrate and the second substrate on which the multilayer wiring structure is formed can be firmly fixed as compared with the structure without the spacer. Therefore, in the process of thinning the first substrate, the in-plane uniformity of the thinning can be improved. Further, by filling the space sealed by the first substrate 100, the second substrate 200, and the spacer 220 with an inert gas, or by putting the space in a vacuum state or a depressurized state, the first bump 210 and the chips 230, 232. Is less likely to come into contact with oxygen and moisture, so that the problem of high resistance due to oxidation of the conductive material can be suppressed.

<Embodiment 4>
In the fourth embodiment, the semiconductor device manufactured by using the through silicon via substrate according to the first to third embodiments will be described.

FIG. 41 is a diagram showing a semiconductor device according to the fourth embodiment of the present invention. The semiconductor device 1000 is connected to an LSI substrate 1400 in which three through silicon via substrates 1310, 1320, and 1330 are laminated and, for example, a semiconductor element such as a DRAM is formed. The through silicon via substrate 1310 has connection terminals 1511 and 1512. These through electrode substrates 1310, 1320, 1330 may be through electrode substrates, each of which is formed of a substrate made of a different material. The connection terminal 1512 is connected to the connection terminal 1500 of the LSI board 1400 by a bump 1610. The connection terminal 1511 is connected to the connection terminal 1522 of the through silicon via board 1320 by a bump 1620. The connection terminals 1521 of the through silicon via 1320 and the connection terminals 1532 of the through silicon via 1330 are also connected by the bumps 1630. For the bumps 1610, 1620, 1630, for example, a metal such as indium, copper, or gold is used.

When the through silicon via substrates are laminated, the number of layers is not limited to three, and may be two layers or four or more layers. Further, in the connection between the through electrode substrate and another substrate, not only the one using bumps but also other bonding techniques such as eutectic bonding may be used. Further, a polyimide, an epoxy resin or the like may be applied and fired to bond the through silicon via substrate to another substrate.

FIG. 42 is a diagram showing another example of the semiconductor device according to the fourth embodiment of the present invention. In the semiconductor device 1000 shown in FIG. 42, semiconductor chips (LSI chips) 1410 and 1420 such as a MEMS device, a CPU, and a memory, and a through silicon via substrate 1300 are laminated and connected to the LSI substrate 1400.

A through silicon via substrate 1300 is arranged between the semiconductor chip 1410 and the semiconductor chip 1420, and is connected by bumps 1640 and 1650. A semiconductor chip 1410 is placed on the LSI substrate 1400, and the LSI substrate 1400 and the semiconductor chip 1420 are connected by a wire 1700. In this example, the through silicon via substrate 1300 is used as an interposer for stacking a plurality of semiconductor chips and mounting them three-dimensionally, and by stacking a plurality of semiconductor chips having different functions, a multifunctional semiconductor device is manufactured. can do. For example, by using the semiconductor chip 1410 as a 3-axis acceleration sensor and the semiconductor chip 1420 as a 2-axis magnetic sensor, it is possible to manufacture a semiconductor device in which a 5-axis motion sensor is realized by one module.

When the semiconductor chip is a sensor formed by a MEMS device or the like, the sensing result may be output by an analog signal. In this case, the low-pass filter, amplifier, and the like may also be formed on the semiconductor chip or the through silicon via substrate 1300.

FIG. 43 is a diagram showing another example of the semiconductor device according to the fourth embodiment of the present invention. The above two examples (FIGS. 41 and 42) were three-dimensional implementations, but in this example, they are applied to a combined implementation of two dimensions and three dimensions (sometimes referred to as 2.5 dimensions). .. In the example shown in FIG. 43, six through electrode substrates 1310, 1320, 1330, 1340, 1350, and 1360 are laminated and connected to the LSI substrate 1400. However, not only are all through silicon via substrates arranged in a laminated manner, but they are also arranged side by side in the in-plane direction of the substrate. These through silicon via substrates may be through silicon via substrates, each of which is formed of a substrate made of a different material.

In the example of FIG. 43, the through electrode substrates 1310 and 1350 are connected on the LSI substrate 1400, the through electrode substrates 1320 and 1340 are connected on the through electrode substrate 1310, and the through electrode substrate 1330 is connected on the through electrode substrate 1320. , The through silicon via 1360 is connected on the through silicon via 1350. As in the example shown in FIG. 42, even if the through silicon via substrate 1300 is used as an interposer for connecting a plurality of semiconductor chips, the two-dimensional and three-dimensional mounting can be performed in combination. For example, the through silicon via substrates 1330, 1340, 1360 and the like may be replaced with semiconductor chips.

The semiconductor device 1000 manufactured as described above includes various devices such as mobile terminals (mobile phones, smartphones, notebook personal computers, etc.), information processing devices (desktop personal computers, servers, car navigation systems, etc.), home appliances, and the like. It is installed in electrical equipment.

The present invention is not limited to the above embodiment, and can be appropriately modified without departing from the spirit.

10, 11, 20, 30: Through electrode substrate 100: First substrate 101: First surface 102: Second surface 103: Altered layer 105: Bottom hole 110: Through electrode 115, 350: Second bump 120: Through hole 130: First wiring layer 132, 142, 152, 162, 224, 342: First conductive layer 134, 144, 154, 164, 226, 344: Second conductive layer 137, 147, 157, 167, 227, 324, 417: Opening 139: 149, 159, 169, 410: Insulation layer 140, 150, 340: Wiring layer 160: Second wiring layer 199: Multilayer wiring structure 200: Second substrate 201: First region 202: Second Region 210: First bump 220: Spacer 222: Third bump 339: Conductive layer 230, 232: Chip 240: Adhesive layer 300: Light source 301: Laser light 310: First film-like resin 317: First opening 320: First 2 film-like resin 325: seed layer 326: plating layer 327: second opening 329: resist pattern 330: through electrode 332: first electrode 334: second electrode 1000: semiconductor device 1300, 1310, 1320, 1330, 1340, 1350, 1360: Through electrode substrate 1400: LSI substrate 1410, 1420: Semiconductor chip 1500, 1511, 1512, 1521, 1522, 1532: Connection terminal 1610, 1620, 1630, 1640, 1650: Bump 1700: Wire

Claims (4)

A first substrate having a first surface and a second surface opposite to the first surface and having a through hole from the first surface to the second surface.
Through silicon vias provided in the through holes and
A multilayer wiring structure provided on the first substrate, the first wiring layer provided on the first substrate, and the second wiring layer connected to the first wiring layer via an insulating layer. With a multi-layer wiring structure with
A chip connected to the second wiring layer and having an electronic circuit,
A second substrate arranged on the side of the chip opposite to the multilayer wiring structure side,
A spacer provided continuously so as to surround the outer periphery of the region in which the chip is arranged, and provided between the multilayer wiring structure and the second substrate,
Have,
The chip and the spacer are adhered to the second substrate via an adhesive layer.
The adhesive layer is continuous from the region where the chip is provided to the region where the spacer is provided.
The spacer is a through silicon via substrate provided on the outer peripheral side of the first wiring layer and the second wiring layer in a plan view and does not overlap with the conductive layer . The through silicon via according to claim 1, wherein the space sealed by the multilayer wiring structure, the second substrate, and the spacer is filled with an inert gas. The through silicon via according to claim 1, wherein the space sealed by the multilayer wiring structure, the second substrate, and the spacer is in a reduced pressure state. It further has a third conductive member provided on the second surface side of the first substrate and connected to the first wiring layer.
The multilayer wiring structure is provided on the first surface side of the first substrate.
The through silicon via according to any one of claims 1 to 3, wherein the region provided with the third conductive member does not overlap with the region provided with the spacer in a plan view.

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