JPH11204940A - Laminated board, bga board and manufacture of laminated board - Google Patents

Laminated board, bga board and manufacture of laminated board

Info

Publication number
JPH11204940A
JPH11204940A JP10006650A JP665098A JPH11204940A JP H11204940 A JPH11204940 A JP H11204940A JP 10006650 A JP10006650 A JP 10006650A JP 665098 A JP665098 A JP 665098A JP H11204940 A JPH11204940 A JP H11204940A
Authority
JP
Japan
Prior art keywords
substrate
laminated
insulating resin
board
bga
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10006650A
Other languages
Japanese (ja)
Inventor
Kazunori Akaho
和則 赤穂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal SMI Electronics Device Inc
Original Assignee
Sumitomo Metal SMI Electronics Device Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal SMI Electronics Device Inc filed Critical Sumitomo Metal SMI Electronics Device Inc
Priority to JP10006650A priority Critical patent/JPH11204940A/en
Publication of JPH11204940A publication Critical patent/JPH11204940A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To realize linear formation and a small diameter for via conductors. SOLUTION: A copper foil is bonded to one side of a thermosetting insulating resin sheet 27 by hot pressing, and the copper foil is photo-etched to linearly form a pattern of a plurality of via conductors 28. After this, multiple insulating resin sheets 27 are stacked and integrated by vacuum thermocompression. After the laminate of the insulating resin sheets 27 is cut to board sizes, the top and bottom cut surfaces or both sides of a board are polished, thereby forming a laminated board 26. The bonded surface between the individual insulating resin sheets 27 in this laminated board 26 is perpendicular to the board surface. After a core sheet 22 is bonded to the bottom of the laminated board 26, solder resist patterns 29 and 30 are respectively formed on the top of the laminated board 26 and the bottom of the core sheet 22. Then, a solder ball is bonded to the bottom of the core sheet 22, thereby forming a BGA(Ball Grid Array) board 21.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ビア導体の形成方
法を改良した積層基板、BGA基板及び積層基板の製造
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated substrate, a BGA substrate, and a method for manufacturing a laminated substrate, in which a method for forming a via conductor is improved.

【0002】[0002]

【従来の技術】近年のICチップの高性能化・小型化に
伴い、ICチップを搭載する基板の配線密度の高密度
化、多ピン化が重要な技術的課題となっている。現在、
実用化されている高密度実装基板の一例としてビルドア
ップ多層基板がある。このものは、図4に示すように、
コア基板となるガラスエポキシ基板11の両面又は片面
にエポキシ系の感光性絶縁樹脂層12を形成し、この感
光性絶縁樹脂層12にフォトエッチング法でビアホール
13を形成し、その上から、銅めっきで内層導体パター
ン14やビア導体15を形成し、以後、同様の工程を順
次繰り返して多層化するものである。
2. Description of the Related Art With the recent increase in performance and miniaturization of IC chips, increasing the wiring density and increasing the number of pins of a substrate on which the IC chip is mounted have become important technical issues. Current,
An example of a high-density mounting board that has been put into practical use is a build-up multilayer board. This is, as shown in FIG.
An epoxy-based photosensitive insulating resin layer 12 is formed on both surfaces or one surface of a glass epoxy substrate 11 serving as a core substrate, and a via hole 13 is formed in the photosensitive insulating resin layer 12 by a photo-etching method. Then, the inner conductor pattern 14 and the via conductor 15 are formed, and thereafter, the same steps are sequentially repeated to form a multilayer.

【0003】[0003]

【発明が解決しようとする課題】上記ビルドアップ多層
基板では、ビア導体15を銅めっきで形成するため、ビ
ア導体15が中空になっている。このため、層間でビア
導体15を一直線に接続することは不可能で、1層毎に
配線パターンを引き回してビア導体15の位置を横にず
らす必要があり、しかも、ビア導体15(ビアホール1
3)の径の微小化もめっき液を行き渡らせる必要性から
限界があった。
In the above build-up multilayer substrate, the via conductor 15 is hollow because the via conductor 15 is formed by copper plating. For this reason, it is impossible to connect the via conductor 15 in a straight line between the layers, and it is necessary to route the wiring pattern for each layer to shift the position of the via conductor 15 to the side.
The miniaturization of the diameter of 3) also has a limit due to the necessity of spreading the plating solution.

【0004】本発明はこのような事情を考慮してなされ
たものであり、従ってその目的は、ビア導体の一直線化
及び微小径化が可能で、高密度化、多ピン化に対応でき
る積層基板、BGA基板及び積層基板の製造方法を提供
することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and accordingly, it is an object of the present invention to provide a laminated substrate which is capable of linearizing and miniaturizing a via conductor, and which can cope with high density and multi-pin. , A BGA substrate and a method of manufacturing a laminated substrate.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、複数枚の絶縁樹脂を積層して成る絶縁樹
脂において、基板面に対して各絶縁樹脂間の接合面が直
角となるように各絶縁樹脂を積層し、各絶縁樹脂の片面
又は両面に形成された配線パターンでビア導体を形成し
たものである(請求項1)。このように、基板面に対し
て各絶縁樹脂間の接合面が直角となるように積層するこ
とで、各絶縁樹脂に形成した配線パターンでビア導体を
形成することが可能となり、従来のビアホールによるビ
ア導体形成方法とは異なり、ビア導体の一直線化及び微
小径化が可能となる。
In order to achieve the above-mentioned object, the present invention relates to an insulating resin comprising a plurality of insulating resins laminated, wherein a bonding surface between the insulating resins is perpendicular to a substrate surface. Insulating resin is laminated so as to form a via conductor with a wiring pattern formed on one or both sides of each insulating resin (claim 1). In this way, by laminating such that the bonding surface between the insulating resins is perpendicular to the substrate surface, it becomes possible to form a via conductor with the wiring pattern formed on each insulating resin, and a conventional via hole is used. Unlike the via conductor forming method, it is possible to make the via conductor straight and small in diameter.

【0006】この場合、請求項2のように、本発明の積
層基板の下面にコア基板を接合すると共に、このコア基
板の下面に半田ボールを列設し、この半田ボールと積層
基板側のビア導体とをコア基板に形成したスルーホール
を通して導通させたBGA(Ball Grid Array )基板を
構成しても良い。このようにすれば、絶縁樹脂の積層厚
みのばらつきがあったとしても、その影響を受けずに、
半田ボールの位置精度をコア基板によって正確にするこ
とができる。
In this case, a core substrate is joined to the lower surface of the laminated substrate according to the present invention, and solder balls are arranged in line on the lower surface of the core substrate. A BGA (Ball Grid Array) substrate may be formed in which conductors are conducted through through holes formed in the core substrate. In this way, even if the thickness of the insulating resin varies,
The position accuracy of the solder ball can be made accurate by the core substrate.

【0007】また、本発明の積層基板を製造する場合に
は、請求項3のように、複数枚の絶縁樹脂の片面又は両
面にビア導体用の配線パターンを形成した後、これら複
数枚の絶縁樹脂を積層し、これを基板サイズに切断し
て、その切断面を研磨して積層基板を形成すると良い。
このようにすれば、各絶縁樹脂間に積層ずれがあったと
しても、積層基板の基板面(切断面)を確実に平坦にす
ることができる。また、1つの絶縁樹脂積層体から多数
の積層基板を切り取るようにすれば、切断という極めて
容易な作業で積層基板を量産することが可能となる。
In the case of manufacturing the laminated substrate of the present invention, after forming a wiring pattern for a via conductor on one or both surfaces of a plurality of insulating resins, the plurality of insulating resins are formed. It is preferable to laminate a resin, cut the resin into a substrate size, and polish the cut surface to form a laminated substrate.
In this way, even if there is a lamination shift between the insulating resins, the substrate surface (cut surface) of the laminated substrate can be reliably flattened. Further, if a large number of laminated substrates are cut from one insulating resin laminated body, it becomes possible to mass-produce the laminated substrates by an extremely easy operation of cutting.

【0008】[0008]

【発明の実施の形態】以下、本発明の一実施形態を図1
乃至図3に基づいて説明する。まず、図1及び図2に基
づいてBGA基板21の構造を説明する。コア基板22
は、例えばガラスエポキシ基板、BT(ビスマレイミド
・トリアジン)エポキシ基板等により形成された単層又
は多層基板であり、その所定位置には、上下方向に貫通
するスルーホール23が形成され、更に、無電解めっ
き、電解めっき等でスルーホール導体25や導体パター
ン24が形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIG. First, the structure of the BGA substrate 21 will be described with reference to FIGS. Core substrate 22
Is a single-layer or multi-layer substrate formed of, for example, a glass epoxy substrate, a BT (bismaleimide triazine) epoxy substrate, or the like, and a through hole 23 penetrating vertically is formed at a predetermined position thereof. The through-hole conductor 25 and the conductor pattern 24 are formed by electrolytic plating, electrolytic plating, or the like.

【0009】このコア基板22の上面には、積層基板2
6が接着剤、導電性ペースト等により接合されている。
この積層基板26は、プリプレグ等により形成された複
数枚の熱硬化性の絶縁樹脂シート27を熱圧着して積層
したものであり、基板面に対して各絶縁樹脂シート27
間の接合面が直角となっている。各絶縁樹脂シート27
の片面には、複数本のビア導体28のパターンがプリン
ト配線技術により一直線状に形成されている。積層基板
26の上面及びコア基板22の下面には、それぞれソル
ダーレジストパターン29,30が形成されている。そ
して、コア基板22の下面には、多数の半田ボール(図
示せず)が接合され、各半田ボールがコア基板22のス
ルーホール導体25を介して積層基板26側のビア導体
28と電気的に接続されている。
On the upper surface of the core substrate 22, the laminated substrate 2
6 are joined by an adhesive, a conductive paste or the like.
The laminated substrate 26 is formed by laminating a plurality of thermosetting insulating resin sheets 27 formed by prepreg or the like by thermocompression bonding.
The joining surface between them is a right angle. Each insulating resin sheet 27
On one side, a pattern of a plurality of via conductors 28 is formed in a straight line by a printed wiring technique. Solder resist patterns 29 and 30 are formed on the upper surface of the laminated substrate 26 and the lower surface of the core substrate 22, respectively. A large number of solder balls (not shown) are joined to the lower surface of the core substrate 22, and each solder ball is electrically connected to the via conductor 28 on the laminated substrate 26 via the through-hole conductor 25 of the core substrate 22. It is connected.

【0010】以上のように構成したBGA基板21を製
造する手順を説明する。まず、熱硬化性の絶縁樹脂シー
ト27(プリプレグ)の片面に銅箔を熱プレスして接合
する。この熱プレスは、絶縁樹脂シート27の硬化を途
中までで抑えるように、例えば130℃、1時間の条件
で行う。本発明者の実験結果(図3参照)によれば、1
30℃で熱プレスを行えば、必要な銅箔ピール強度(銅
箔と絶縁樹脂シート27との接合強度)を十分に確保で
きることが確認された。
A procedure for manufacturing the BGA substrate 21 configured as described above will be described. First, a copper foil is hot-pressed and joined to one surface of a thermosetting insulating resin sheet 27 (prepreg). This hot pressing is performed, for example, at 130 ° C. for one hour so that the curing of the insulating resin sheet 27 is suppressed halfway. According to the experimental results of the inventor (see FIG. 3), 1
It has been confirmed that the necessary copper foil peel strength (the bonding strength between the copper foil and the insulating resin sheet 27) can be sufficiently ensured by hot pressing at 30 ° C.

【0011】熱プレス後、銅箔の表面全体に感光性レジ
ストをスピンコーターで塗布し、例えば100℃で7分
間、大気乾燥(プリベーク)する。この後、感光性レジ
ストのうちのビア導体パターン形成部分のみを露光(3
00mj)し、これをアルカリ現像液に例えば1分間浸
漬して現像した後、例えば120℃で7分間、ポストベ
ークする。この後、銅箔のうちの感光性レジストから露
出する部分(つまりビア導体パターン以外の部分)をア
ルカリエッチング液でエッチングして取り除いた後、ア
セトンで感光性レジストを剥離する。これにより、絶縁
樹脂シート27に複数本のビア導体28のパターンを一
直線状に形成する。
After hot pressing, a photosensitive resist is applied to the entire surface of the copper foil with a spin coater, and dried (prebaked) at, for example, 100 ° C. for 7 minutes. Then, only the via conductor pattern forming portion of the photosensitive resist is exposed (3
00mj), immersed in an alkali developing solution for, for example, 1 minute, and developed, and then post-baked at, for example, 120 ° C. for 7 minutes. Thereafter, a portion of the copper foil exposed from the photosensitive resist (that is, a portion other than the via conductor pattern) is removed by etching with an alkaline etchant, and then the photosensitive resist is peeled off with acetone. Thereby, the pattern of the plurality of via conductors 28 is formed in the insulating resin sheet 27 in a straight line.

【0012】次の積層工程で、ビア導体28付きの絶縁
樹脂シート27を複数枚重ね合わせて、例えば150℃
で8時間、真空熱プレスして、複数枚の絶縁樹脂シート
27を硬化させながら熱圧着して一体化する。
In the next laminating step, a plurality of insulating resin sheets 27 with via conductors 28 are superposed,
For 8 hours under vacuum, and thermocompression-bonding and unifying the plurality of insulating resin sheets 27 while curing them.

【0013】この後、絶縁樹脂シート27の積層体を基
板サイズにダイシングにより切断した後、上下の切断
面、つまり基板両面を研磨して積層基板26を形成す
る。尚、絶縁樹脂シート27の積層体から切断する積層
基板26の数は1個でも良いが、複数個でも良い。同じ
絶縁樹脂シート27の積層体から多数の積層基板26を
切り取るようにすれば、切断という極めて容易な作業で
積層基板26を量産することが可能となる。
Thereafter, the laminated body of the insulating resin sheet 27 is cut into a substrate size by dicing, and the upper and lower cut surfaces, that is, both surfaces of the substrate are polished to form a laminated substrate 26. Note that the number of the laminated substrates 26 cut from the laminated body of the insulating resin sheets 27 may be one, but may be plural. If a large number of laminated substrates 26 are cut out from the same laminated body of the insulating resin sheets 27, the laminated substrates 26 can be mass-produced by an extremely easy operation of cutting.

【0014】一方、コア基板22には、予めスルーホー
ル23を形成して、無電解めっき、電解めっき等でスル
ーホール導体25や導体パターン24を形成しておく。
そして、このコア基板22の上面に積層基板26を接着
剤、導電性ペースト等により接合した後、積層基板26
の上面及びコア基板22の下面に、それぞれソルダーレ
ジストパターン29,30を形成する。この後、コア基
板22の下面に半田ボールを接合して、BGA基板21
を形成する。
On the other hand, a through hole 23 is formed in the core substrate 22 in advance, and a through hole conductor 25 and a conductor pattern 24 are formed by electroless plating, electrolytic plating, or the like.
Then, after bonding the laminated substrate 26 to the upper surface of the core substrate 22 with an adhesive, a conductive paste, or the like, the laminated substrate 26
Are formed on the lower surface of the core substrate 22 and the upper surface of the core substrate 22, respectively. Thereafter, solder balls are bonded to the lower surface of the core substrate 22 to form the BGA substrate 21.
To form

【0015】尚、コア基板22のスルーホール23の形
成は、コア基板22を積層基板26と接合した後に行う
ようにしても良い。この場合には、まず、コア基板22
の上面に積層基板26を接着剤により接合した後、コア
基板22側から例えば炭酸ガスレーザでスルーホール2
3を形成する。この後、無電解めっきと電解めっきによ
りスルーホール導体25を形成して、このスルーホール
導体25と積層基板26側のビア導体28とを導通させ
る。この際、スルーホール23のめっきと同時に、コア
基板22の下面全体にめっき被膜を形成する。その後、
このめっき被膜をフォトエッチングして導体パターンを
形成する。
The formation of the through holes 23 in the core substrate 22 may be performed after the core substrate 22 is joined to the laminated substrate 26. In this case, first, the core substrate 22
After the laminated substrate 26 is bonded to the upper surface of the through hole 2 with an adhesive, the through-hole 2 is
Form 3 Thereafter, the through-hole conductor 25 is formed by electroless plating and electrolytic plating, and the through-hole conductor 25 and the via conductor 28 on the side of the laminated substrate 26 are conducted. At this time, a plating film is formed on the entire lower surface of the core substrate 22 simultaneously with the plating of the through holes 23. afterwards,
The plating film is photo-etched to form a conductor pattern.

【0016】この後、積層基板26の上面及びコア基板
22の下面に、それぞれ感光性のソルダーレジストを印
刷により例えば20μmの厚みで塗布し、露光(300
mj)、現像(炭酸ソーダ1%)した後、1000mj
のUVキュアーとポストベーク(150℃、1時間)を
行う。この後、無電解Niめっきと無電解Auめっきを
施してパッドを形成した後、コア基板22の下面のパッ
ドに半田ボールを接合してBGA基板21を形成する。
Thereafter, a photosensitive solder resist is applied to the upper surface of the laminated substrate 26 and the lower surface of the core substrate 22 by printing, for example, to a thickness of, for example, 20 μm.
mj) and after development (sodium carbonate 1%), 1000 mj
UV curing and post baking (150 ° C., 1 hour). After that, pads are formed by performing electroless Ni plating and electroless Au plating, and then solder balls are bonded to the pads on the lower surface of the core substrate 22 to form the BGA substrate 21.

【0017】以上説明した実施形態によれば、基板面に
対して各絶縁樹脂シート27間の接合面が直角となるよ
うに積層して積層基板26を形成したので、絶縁樹脂シ
ート27に形成した配線パターンでビア導体28を形成
することが可能となり、従来のビアホールによるビア導
体形成方法とは異なり、ビア導体28の一直線化及び微
小径化が可能となり、高密度化、多ピン化に対応でき
る。
According to the embodiment described above, since the laminated substrate 26 is formed by laminating the insulating resin sheets 27 so that the joining surface between the insulating resin sheets 27 is perpendicular to the substrate surface, the laminated resin substrate 27 is formed on the insulating resin sheet 27. The via conductor 28 can be formed by a wiring pattern, and unlike the conventional via conductor forming method using via holes, the via conductor 28 can be straightened and reduced in diameter, and can be adapted to high density and multi-pin. .

【0018】しかも、積層基板26の下面にコア基板2
2を接合してBGA基板21を形成したので、絶縁樹脂
シート27の積層厚みのばらつきがあったとしても、そ
の影響を受けずに、コア基板22下面の半田ボールの位
置精度を正確にすることができ、品質向上に寄与でき
る。但し、絶縁樹脂シート27の積層厚みのばらつきが
半田ボールの位置精度の許容範囲である場合には、積層
基板26の下面に直接、半田ボールを接合してBGA基
板を構成するようにしても良い。
Further, the core substrate 2 is provided on the lower surface of the laminated substrate 26.
Since the BGA substrate 21 is formed by bonding the BGAs 2, even if the thickness of the insulating resin sheet 27 varies, the positional accuracy of the solder balls on the lower surface of the core substrate 22 can be made accurate without being affected by the variation. And contribute to quality improvement. However, when the variation in the lamination thickness of the insulating resin sheet 27 is within the allowable range of the positional accuracy of the solder balls, the solder balls may be directly bonded to the lower surface of the lamination substrate 26 to form a BGA substrate. .

【0019】尚、上記実施形態では、複数枚の絶縁樹脂
シート27を積層して積層基板26を形成したが、絶縁
樹脂層を1層ずつ形成してビルドアップするようにして
も良い。
In the above embodiment, the laminated substrate 26 is formed by laminating a plurality of insulating resin sheets 27. However, the insulating resin layers may be formed one by one to build up.

【0020】また、上記実施形態では、全てのビア導体
28を一直線状に形成したが、半田ボールのピッチ等に
応じてビア導体28の一部分を屈曲させるようにしても
良い。また、ビア導体28のパターニング方法も上記実
施形態に限定されるものではなく、公知の種々のプリン
ト配線技術を用いてビア導体をパターニングすることが
可能である。また、上記実施形態では、絶縁樹脂シート
27の片面にビア導体28をパターニングしたが、絶縁
樹脂シート27の両面にビア導体28をパターニングす
るようにしても良い。
In the above embodiment, all the via conductors 28 are formed in a straight line. However, a part of the via conductor 28 may be bent in accordance with the pitch of the solder balls. Also, the patterning method of the via conductor 28 is not limited to the above-described embodiment, and the via conductor can be patterned using various known printed wiring techniques. In the above embodiment, the via conductor 28 is patterned on one surface of the insulating resin sheet 27, but the via conductor 28 may be patterned on both surfaces of the insulating resin sheet 27.

【0021】その他、本発明は、コア基板22の両面に
積層基板26を接合したり、積層基板26をBGA基板
以外の用途に用いても良い等、種々変更して実施でき
る。
In addition, the present invention can be implemented with various modifications, such as bonding the laminated substrate 26 to both surfaces of the core substrate 22 and using the laminated substrate 26 for applications other than the BGA substrate.

【0022】[0022]

【発明の効果】以上の説明から明らかなように、本発明
の積層基板は、基板面に対して各絶縁樹脂間の接合面が
直角となるように各絶縁樹脂を積層し、各絶縁樹脂に形
成した配線パターンでビア導体を形成したので、ビア導
体を一直線化及び微小径化することができ、高密度化、
多ピン化に対応できる(請求項1)。
As is apparent from the above description, the laminated substrate of the present invention is formed by laminating each insulating resin such that the bonding surface between the insulating resins is perpendicular to the substrate surface, and Since the via conductor is formed with the formed wiring pattern, the via conductor can be straightened and the diameter can be reduced.
The number of pins can be increased (claim 1).

【0023】また、本発明のBGA基板は、上記構成の
積層基板の下面にコア基板を接合して構成したので、絶
縁樹脂シートの積層厚みのばらつきの影響を受けずに、
半田ボールの位置精度を向上することができる(請求項
2)。
Further, since the BGA substrate of the present invention is formed by bonding the core substrate to the lower surface of the laminated substrate having the above structure, the BGA substrate is not affected by the variation of the laminated thickness of the insulating resin sheet.
The position accuracy of the solder ball can be improved (claim 2).

【0024】また、本発明の積層基板の製造方法では、
絶縁樹脂の積層体を基板サイズに切断して、その切断面
を研磨して積層基板を形成するようにしたので、基板面
の平坦化と量産性向上とを実現することができる(請求
項3)。
In the method for manufacturing a laminated substrate according to the present invention,
Since the laminated body of the insulating resin is cut into a substrate size and the cut surface is polished to form a laminated substrate, it is possible to realize flattening of the substrate surface and improvement of mass productivity. ).

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態におけるBGA基板の構造
を模式的に示す断面図
FIG. 1 is a sectional view schematically showing a structure of a BGA substrate according to an embodiment of the present invention.

【図2】BGA基板の構造を模式的に示す部分破断斜視
FIG. 2 is a partially cutaway perspective view schematically showing the structure of a BGA substrate.

【図3】銅箔を絶縁樹脂シートに熱プレスする際の温度
とピール強度との関係を測定した実験結果を示す図
FIG. 3 is a view showing an experimental result of measuring a relationship between a temperature and a peel strength when hot pressing a copper foil on an insulating resin sheet.

【図4】従来のビルドアップ多層基板の構造を模式的に
示す断面図
FIG. 4 is a cross-sectional view schematically showing the structure of a conventional build-up multilayer substrate.

【符号の説明】[Explanation of symbols]

21…BGA基板、22…コア基板、23…スルーホー
ル、24…導体パターン、25…スルーホール導体、2
6…積層基板、27…絶縁樹脂シート、28…ビア導
体、29,30…ソルダーレジストパターン。
21 BGA board, 22 core board, 23 through-hole, 24 conductor pattern, 25 through-hole conductor, 2
6: laminated substrate, 27: insulating resin sheet, 28: via conductor, 29, 30: solder resist pattern.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H01L 23/12 L ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 23/12 L

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数枚の絶縁樹脂を積層して成る積層基
板において、 基板面に対して各絶縁樹脂間の接合面が直角となるよう
に各絶縁樹脂を積層し、各絶縁樹脂の片面又は両面に形
成された配線パターンでビア導体を形成したことを特徴
とする積層基板。
1. A laminated board comprising a plurality of insulating resins laminated, wherein each insulating resin is laminated such that a bonding surface between the insulating resins is perpendicular to a substrate surface, and one side of each insulating resin or A laminated substrate having via conductors formed by wiring patterns formed on both surfaces.
【請求項2】 請求項1に記載の積層基板の下面にコア
基板を接合すると共に、このコア基板の下面に半田ボー
ルを列設し、この半田ボールと前記積層基板側のビア導
体とを前記コア基板に形成したスルーホールを通して導
通させたことを特徴とするBGA基板。
2. A core substrate is joined to the lower surface of the laminated substrate according to claim 1, and solder balls are arranged in line on the lower surface of the core substrate, and the solder balls and via conductors on the laminated substrate side are connected to each other. A BGA substrate, wherein conduction is made through through holes formed in a core substrate.
【請求項3】 請求項1に記載の積層基板を製造する方
法において、 複数枚の絶縁樹脂の片面又は両面にビア導体用の配線パ
ターンを形成した後、これら複数枚の絶縁樹脂を積層
し、これを基板サイズに切断して、その切断面を研磨し
て積層基板を形成することを特徴とする積層基板の製造
方法。
3. The method of manufacturing a laminated substrate according to claim 1, wherein after forming a wiring pattern for a via conductor on one or both surfaces of the plurality of insulating resins, the plurality of insulating resins are laminated. A method of manufacturing a laminated substrate, comprising cutting the substrate to a substrate size and polishing the cut surface to form a laminated substrate.
JP10006650A 1998-01-16 1998-01-16 Laminated board, bga board and manufacture of laminated board Pending JPH11204940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10006650A JPH11204940A (en) 1998-01-16 1998-01-16 Laminated board, bga board and manufacture of laminated board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10006650A JPH11204940A (en) 1998-01-16 1998-01-16 Laminated board, bga board and manufacture of laminated board

Publications (1)

Publication Number Publication Date
JPH11204940A true JPH11204940A (en) 1999-07-30

Family

ID=11644265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10006650A Pending JPH11204940A (en) 1998-01-16 1998-01-16 Laminated board, bga board and manufacture of laminated board

Country Status (1)

Country Link
JP (1) JPH11204940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022050595A (en) * 2020-02-03 2022-03-30 大日本印刷株式会社 Through electrode substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022050595A (en) * 2020-02-03 2022-03-30 大日本印刷株式会社 Through electrode substrate

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