KR20160103270A - Printed circuit board and method of manufacturing the same - Google Patents

Abstract

A printed circuit board of the present invention comprises: a circuit layer; and a build-up insulating layer formed by sequentially including first, second, and third insulating layers between circuit layers. Provided is the printed circuit board to reduce warpage of a substrate by configuring a build-up insulator with a composite insulating layer having a low heat expansion rate.

Description

Technical Field [0001] The present invention relates to a printed circuit board and a method of manufacturing the same,

The present invention relates to a printed circuit board and a manufacturing method thereof.

Generally, a printed circuit board is formed by wiring a copper foil on one side or both sides of a board made of various thermosetting synthetic resins, and then ICs or electronic parts are arranged and fixed on the board, and electrical wiring between them is implemented and coated with an insulator. In particular, a variety of techniques are required for the implementation of printed circuit boards in accordance with the tendency of the market to demand reduction of profiles and various functions in semiconductor packages.

Currently, thin circuit boards, such as printed circuit boards (PCBs), are being fabricated in such a way that various build-up insulation layers are stacked and pressed in order for thinning and high integration. As a result, warpage is becoming a very important packaging feature. As the number of solder bumps used for connection with semiconductors increases, pitches become smaller, and fewer solders are used to join the semiconductor devices, If the characteristics are not correct, the solder may not be connected or cracks may occur. Warpage of a multilayer substrate is generally caused by shrinkage of an insulating material and asymmetry of a buildup layer in the case of forming a buildup layer on the upper and lower surfaces of the core. As the thickness becomes smaller, it becomes difficult to suppress warpage of the upper and lower buildup layers.

US Published Patent US 2012-0037411A

One aspect (or perspective) is to provide a printed circuit board that can reduce the warpage of the substrate by constructing the build-up insulating material as a composite insulating layer having a low thermal expansion coefficient.

Another aspect of the present invention is to provide a method of manufacturing a printed circuit board which can reduce the warpage of a substrate by forming a composite insulating layer having a low thermal expansion coefficient.

A printed circuit board according to an exemplary embodiment includes a build-up insulation layer formed between a circuit layer and a circuit layer sequentially including a first insulation layer, a second insulation layer, and a third insulation layer.

According to another aspect of the present invention, there is provided a method of manufacturing a printed circuit board, comprising: preparing a core substrate; Forming a build-up insulation layer formed by sequentially laminating a first insulation material layer, a second insulation material layer and a third insulation material layer on both sides of the core substrate; And forming a build-up circuit layer on the build-up insulating layer.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

1 is a cross-sectional view of a printed circuit board according to a first embodiment of the present invention.
2 is a cross-sectional view of a printed circuit board according to a second embodiment of the present invention.
3 is a cross-sectional view of a printed circuit board according to a third embodiment of the present invention.
4 is a cross-sectional view of a printed circuit board according to a fourth embodiment of the present invention.
5 is a cross-sectional view of a printed circuit board according to a fifth embodiment of the present invention.
6 is a process flow chart for a method of manufacturing a printed circuit board of the present invention.
7A to 7D are process diagrams for a method of manufacturing a printed circuit board according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The objectives, specific advantages and novel features of the invention will become more apparent from the following detailed description and examples taken in conjunction with the accompanying drawings. It should be noted that, in the present specification, the reference numerals are added to the constituent elements of the drawings, and the same constituent elements have the same numerical numbers as much as possible even if they are displayed on different drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In this specification, the terms first, second, etc. are used to distinguish one element from another, and the element is not limited by the terms. In the accompanying drawings, some of the elements are exaggerated, omitted or schematically shown, and the size of each element does not entirely reflect the actual size.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Printed circuit board

First, a printed circuit board according to an embodiment of the present invention will be specifically described with reference to the drawings. Here, reference numerals not shown in the drawings to be referred to may be reference numerals in other drawings showing the same configuration.

1 is a cross-sectional view of a printed circuit board according to a first embodiment of the present invention.

A first circuit layer 120 formed on both sides of the core substrate 110; A build-up insulation layer 130 comprising a first insulation layer 131, a second insulation layer 132 and a third insulation layer 133 sequentially formed on the first circuit layer 120; A second circuit layer (build-up circuit layer) 140 formed on the build-up insulation layer 130; A solder resist layer 150 formed on the second circuit layer 140 and having an opening to expose a predetermined pattern of the second circuit layer 140 and a post 160 formed of a metal material on the opening of the solder resist layer ).

The first circuit layer 120 forms a circuit pattern on both sides of the core substrate 110. The circuit layer formed on one surface of the substrate and the circuit layer formed on the other surface are electrically connected to each other through the through vias Vt passing through the substrate. . Here, the core substrate 110 is made of a resin containing an inorganic filler, a glass fiber, or a combination thereof.

The build-up insulation layer 130 includes a first insulation layer 131 formed of a semi-cured insulation material, a second insulation layer 132 formed of a fully cured insulation material, and a third insulation layer 132 having an epoxy (133).

More specifically, in order to reduce hardening shrinkage during the build-up of the build-up insulating material of the build-up insulating layer 130, the middle portion is formed of a second insulation layer of a fully cured C-Stage, Layer of the B-stage so as to be adhered thereto while impregnating the circuit pattern of the B-stage, and a third insulating layer of Resin capable of securing the plating adhesion force to form the upper circuit pattern.

For example, B-Stage Resin acrylate, BT Resin, or the like may be used as the insulating material of the first insulating layer 131, but the present invention is not limited thereto. The first insulating layer 131 may be formed on the first circuit layer 120.

The second insulation layer 132 may be formed of resin such as Resin, glass fabric and inorganic filler including a filler of C-Stage film. , A polyimide film, and the like, but not limited thereto.

The third insulating layer 133 is formed by thinly coating a resin such as an epoxy resin, which improves adhesion with the circuit pattern seeding plating to be formed on the upper portion do.

On the other hand, the build-up insulation layer 130 composed of the first insulation layer 131, the second insulation layer 132 and the third insulation layer 133 is provided as a build-up insulation film in the form of a completed dry film, The first insulating layer 131 and the second insulating layer 132 may be formed of a separate insulating film and may be first laminated on the substrate and then the third insulating layer 133 may be separately coated thereafter You may.

The C-Stage of the second insulation layer 132 is formed of a material having a low thermal expansion coefficient, although the build-up insulation layer 130 basically has a low thermal expansion coefficient characteristic in each layer . The third insulating layer 133 may be formed to have a lower thickness than the second insulating layer.

Thus, the build-up insulation layer 130 includes a first insulation layer 131 formed of a semi-cured insulation material, a second insulation layer 132 formed of a completely cured insulation material, and a third insulation layer 132 having an epoxy (133), the curing shrinkage of the build-up insulating material can be reduced to reduce the warpage phenomenon.

The second circuit layer 140 is formed on the build-up insulating layer 130, and is formed through a process of applying a dry film and patterning an opening for forming a circuit, A via is formed for electrical connection.

The solder resist layer 150 is a heat resistant coating material and protects the external circuit layer from being coated with solder during soldering. Further, in order to electrically connect to the external circuit, it is preferable to expose the connection pad by processing the opening in the solder resist layer 150.

The bumps are bonded to the upper chip or the bonding region of the substrate in a state where the bumps made of a conductive material are integrally formed. That is, by adhering the counterpart to the conductive solder of the bump by using the thermal compression type bonding method of bonding the bonding area of the counterpart such as the upper chip or the substrate and the conductive solder of each bump at a predetermined temperature, Stacking is performed between the semiconductor chips, or the semiconductor chip is conductively connected to the substrate.

FIG. 2 is a cross-sectional view of a printed circuit board according to a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of a printed circuit board according to a third embodiment of the present invention.

As shown in FIG. 2, the printed circuit board of the present invention includes a first circuit layer 220 formed on both sides of a substrate 210; A first build-up insulation layer 230 comprising a first insulation layer 231, a second insulation layer 232 and a third insulation layer 233 sequentially formed on the first circuit layer 220; A second circuit layer 240 formed on the first build-up dielectric layer 230; A second build-up insulation layer (250) formed on the second circuit layer (240); A third circuit layer 260 formed on the second build-up insulation layer 250; A solder resist layer 270 formed on the third circuit layer 260 and having an opening to expose a predetermined pattern of the third circuit layer 240 and a solder resist layer 270 formed on the opening of the solder resist layer 270 And a post 280.

Here, the above-described first embodiment will be referred to, and thus redundant explanations can be omitted.

The printed circuit board of the second embodiment shows a structure in which the build-up insulating layer and the circuit layer are repeatedly laminated on both sides of the substrate at least twice. Here, the build-up insulating layer may be formed by laminating an insulating material including first, second and third insulating layers, forming a via hole by using a YAG laser or a CO2 laser, and then forming a via hole by using a semi- (Modified Semi-Additive Process) or the like to form a circuit layer including a via.

3, the printed circuit board of the third embodiment includes a first circuit layer 320 formed on both sides of the substrate 310; A first buildup insulation layer 330 comprising a first insulation layer 331, a second insulation layer 332 and a third insulation layer 333 sequentially formed on the first circuit layer 320; A second circuit layer (340) formed on the first build-up insulation layer (330); A second build-up insulation layer 350a formed on the second circuit layer 340 on one side of the substrate 310; A third circuit layer 360 formed on the second build-up insulation layer 350a; The third circuit layer 360 is formed on the first circuit layer 330b formed on the other surface of the substrate 310 while the third circuit layer 360 is formed with a solder resist layer 370 And a post 380 formed of a metal material at an opening of the solder resist layer 370. [

Here, the printed circuit board of the third embodiment shows a structure in which the build-up insulation layer and the circuit layer are repeatedly laminated at least twice on one surface of the substrate. Here, the build-up insulating layer may be formed by laminating an insulating material including first, second and third insulating layers, forming a via hole by using a YAG laser or a CO2 laser, and then forming a via hole by using a semi- (Modified Semi-Additive Process) or the like to form a circuit layer including a via.

4 is a cross-sectional view of a printed circuit board according to a fourth embodiment of the present invention, and FIG. 5 is a cross-sectional view of a printed circuit board according to a fifth embodiment of the present invention.

As shown in Fig. 4, the printed circuit board of the fourth embodiment includes: a first circuit layer 420 formed on both sides of the substrate 410; A build-up insulation layer 430 including a first insulation layer 431, a second insulation layer 432 and a third insulation layer 433 sequentially formed on the first circuit layer 420; A second circuit layer 440 formed on the build-up insulation layer 430; A single insulating layer 450 formed on the second circuit layer 450; A third circuit layer 460 formed on the single insulation layer 450; A solder resist layer 470 formed on the third circuit layer 460 and having an opening to expose a predetermined pattern of the third circuit layer 460 and a solder resist layer 470 formed on the opening of the solder resist layer 470 And a post 480.

Here, the above-described first embodiment will be referred to, and thus redundant explanations can be omitted.

The printed circuit board of the fourth embodiment has a structure in which a single insulating layer is further formed on a build-up insulating layer that is stacked on the outermost side of the substrate 410. In the case of forming microcircuits or fine vias in the outer layer, .

As shown in Fig. 5, the printed circuit board of the fifth embodiment includes: a first circuit layer 520 formed on both sides of a substrate 510; A single insulating layer 530 formed on the first circuit layer 520; A second circuit layer 540 formed on the single insulating layer 530; A build-up insulation layer 550 comprising a first insulation layer 551, a second insulation layer 552 and a third insulation layer 553 sequentially formed on the second circuit layer 540; A third circuit layer 560 formed on the build-up insulation layer 550; A solder resist layer 570 formed on the third circuit layer 560 and having an opening to expose a predetermined pattern of the third circuit layer 560 and a solder resist layer 570 formed on the opening of the solder resist layer 570 And a post 580.

Here, the above-described first embodiment will be referred to, and thus redundant explanations can be omitted.

The printed circuit board of the fifth embodiment has a structure in which a single insulating layer 530 is further formed on the first circuit layer 520 of the substrate 510. A cavity is formed in the core of the substrate, It is formed to secure the fluidity of the insulating material.

Manufacturing method of printed circuit board

FIG. 6 is a process flow chart for a method of manufacturing a printed circuit board of the present invention, and FIGS. 7A to 7D are process drawings of a printed circuit board according to an embodiment of the present invention.

First, as shown in FIG. 6, a method of manufacturing a printed circuit board includes forming a first circuit layer on both sides of a substrate (S601); (S602) forming a build-up insulation layer formed by sequentially laminating a first insulation material layer, a second insulation material layer and a third insulation material layer on both sides of the first circuit layer, respectively; Forming a second circuit layer on the build-up insulating layer (S603); And forming a solder resist layer on the second circuit layer (S604).

First, as shown in FIG. 7A, after vias penetrating in the thickness direction of the core substrate are formed by drilling, a dry film is applied to both surfaces of the substrate 110 to pattern the opening for circuit formation, (120). Here, the core substrate 110 is made of a resin containing an inorganic filler, a glass fiber, or a combination thereof. The dry film serves as a plating resist for forming the first circuit layer 120, and is applied using lamination. Here, the step of patterning the opening for forming a circuit on the dry film will be described in detail. First, the dry film is brought into close contact with the ArtWic film, and then an exposure process is performed in which ultraviolet rays are irradiated to selectively cure the dry film. Thereafter, the opening for circuit formation can be patterned by performing a developing step of dissolving and removing the uncured dry film by using sodium carbonate, potassium carbonate or the like. Then, the first circuit layer 120 is formed in the opening for circuit formation. The circuit layer 120 is preferably formed using copper through an electrolytic plating process. Here, when the formation of the circuit layer is completed, the dry film is removed. It is preferable to remove the dry film using a peeling solution such as NaOH or KOH.

Next, as shown in FIG. 7B, build-up insulation layers 130a and 130b are formed on both sides of the substrate 110 on which the first circuit layer 120 is formed.

More specifically, the build-up insulation layer 130 includes a first insulation layer 131 formed of a semi-cured insulation material, a second insulation layer 132 formed of a completely cured insulation material, and an epoxy The third insulating layer 133 is formed.

In order to reduce curing shrinkage during the build-up of the build-up insulating material of the build-up insulating layer 130, the intermediate portion is formed of a second insulation layer of a fully cured C-Stage, It is preferable that the third insulating layer is made of a first insulating layer of B-Stage to be adhered while being impregnated and a third insulating layer of resin which can secure a plating adhesion force to form an upper circuit pattern.

For example, B-Stage Resin acrylate, BT Resin, or the like may be used as the insulating material of the first insulating layer 131, but the present invention is not limited thereto. The first insulating layer 131 may be formed on the first circuit layer 120.

The second insulation layer 132 may be formed of resin such as Resin, glass fabric and inorganic filler including a filler of C-Stage film. , A polyimide film, and the like, but not limited thereto.

The third insulating layer 133 is formed by thinly coating a resin such as an epoxy resin, which improves adhesion with the circuit pattern seeding plating to be formed on the upper portion do.

On the other hand, the build-up insulation layer 130 composed of the first insulation layer 131, the second insulation layer 132 and the third insulation layer 133 is provided as a build-up insulation film in the form of a completed dry film, The first insulating layer 131 and the second insulating layer 132 may be formed of a separate insulating film and may be first laminated on the substrate and then the third insulating layer 133 may be separately coated thereafter You may.

The C-Stage of the second insulation layer 132 is formed of a material having a low thermal expansion coefficient, although the build-up insulation layer 130 basically has a low thermal expansion coefficient characteristic in each layer . The third insulating layer 133 may be formed to have a lower thickness than the second insulating layer.

Next, as shown in FIG. 7C, the second circuit layer 140 is formed on the build-up insulating layer 130 by patterning to expose vias and openings, and filling the via holes with a metal material . Here, an outer layer circuit layer including vias can be formed by performing a Semi-Additive Process (SAP) or a Modified Semi-Additive Process (MSAP). In addition, the process described above is not particularly limited, and a conventional circuit forming method including a subtractive, SAP and MASP known in the art is used.

7D, a solder resist layer 150 and a post 160 having openings on the build-up insulating layer 130 are formed. More preferably, the opening of the solder resist layer 160 includes a step of exposing and developing the mask by patterning the mask.

The solder resist layer 150 is a heat resistant coating material and protects the external circuit layer from being coated with solder during soldering. Further, in order to electrically connect to the external circuit, it is preferable to process the openings in the solder resist layer 150 to expose the pads.

The bumps are bonded to the upper chip or the bonding region of the substrate in a state where the bumps made of a conductive material are integrally formed. That is, by adhering the counterpart to the conductive solder of the bump by using the thermal compression type bonding method of bonding the bonding area of the counterpart such as the upper chip or the substrate and the conductive solder of each bump at a predetermined temperature, Stacking is performed between the semiconductor chips, or the semiconductor chip is conductively connected to the substrate.

On the other hand, in the method of forming the printed circuit board as shown in FIGS. 2 and 3, the circuit layer and the build-up insulating layer may be repeatedly formed on one or both surfaces of the substrate on which the build- have.

4 and 5, a single insulating layer is formed on a build-up insulating layer between the first circuit layer formed on the substrate and the build-up insulating layer or the outermost layer can do.

Here, a structure in which a single insulating layer is further formed on the build-up insulating layer that is laminated on the outermost layer of the substrate can ensure fluidity in the case of forming a microcircuit or fine via in the outer layer, It is possible to secure the fluidity of the insulating material when a cavity is formed in the core of the substrate and an electric element is embedded in the cavity.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the same is by way of illustration and example only and is not to be construed as limiting the present invention. It is obvious that the modification or improvement is possible.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

110, 210, 310, 410, 510 --- Core substrate
120, 220, 320, 420, 520 --- first circuit layer
130, 230, 330, 430, 530 --- Build-up insulation layer
131, 231, 251, 331, 351, 431, 551,
132, 232, 252, 332, 352, 432, 552 --- Second insulating layer
133, 233, 253, 333, 353, 433, 553 --- Third insulating layer
140, 240, 340, 440, 540 --- Second circuit layer
150, 270, 370, 470, 570 --- Solder resist layer
160, 280, 380, 480, 580 --- Post

Claims (28)

And a build-up insulation layer formed between the circuit layer and the circuit layer, the build-up insulation layer including a first insulation layer, a second insulation layer and a third insulation layer sequentially.
The method according to claim 1,
Wherein the second insulating layer is formed of a hardening insulating material having a thermal expansion coefficient lower than that of the insulating material of the first insulating layer and the third insulating layer.
The method according to claim 1,
Wherein the third insulating layer is formed of an insulating material having a thickness lower than that of the second insulating layer.
The method according to claim 1,
Wherein the third insulating layer is formed of an insulating material including an epoxy having adhesion.
The method according to claim 1,
Wherein the first insulation layer, the second insulation layer, and the third insulation layer are provided in the form of a build-up insulation film.
The method according to claim 1,
A core substrate made of a resin containing an inorganic filler, a glass fiber, or a combination thereof.
A core substrate; And
A build-up layer including a build-up circuit layer and a build-up insulation layer formed on the core substrate; / RTI >
Wherein the build-up insulation layer comprises a first insulation layer, a second insulation layer and a third insulation layer, respectively.
The method of claim 7,
Wherein the second insulating layer is formed of a hardening insulating material having a thermal expansion coefficient lower than that of the insulating material of the first insulating layer and the third insulating layer.
The method of claim 7,
Wherein the third insulating layer is formed of an insulating material having a thickness lower than that of the second insulating layer.
The method of claim 7,
Wherein the third insulating layer is formed of an insulating material including an epoxy having adhesion.
The method of claim 7,
And a solder resist layer formed on the build-up circuit layer and having an opening to expose a connection pad of the build-up circuit layer.
The method of claim 11,
And a post formed on the exposed connection pad.
The method of claim 7,
And a single insulation layer between the core substrate and the build-up insulation layer.
The method of claim 7,
Wherein the build-up insulating layer is repeatedly laminated on at least one surface or both surfaces of the core substrate.
15. The method of claim 14,
And a single insulating layer on the build-up circuit layer.
The method of claim 7,
Wherein the core substrate comprises an inorganic filler, a glass fiber, or a resin containing a combination thereof.
Preparing a core substrate;
Forming a build-up insulation layer formed by sequentially laminating a first insulation material layer, a second insulation material layer and a third insulation material layer on both sides of the core substrate; And
And forming a build-up circuit layer on the build-up insulating layer.
18. The method of claim 17,
Wherein the first insulating material layer is formed by coating a semi-cured insulating material on the build-up circuit layer.
19. The method of claim 18,
Wherein the semi-cured insulating material uses either acrylate or BT resin.
18. The method of claim 17,
Wherein the second insulating material layer is formed of a fully cured insulating material.
The method of claim 20,
Wherein the fully cured insulating material comprises any one of a resin including inorganic filler, a resin including glass fiber and inorganic filler, and a polyimide film.
18. The method of claim 17,
Wherein the third insulating material layer is formed by coating a resin including epoxy.
18. The method of claim 17,
Wherein the build-up circuit layer comprises vias through the thickness of the core substrate.
18. The method of claim 17,
And forming a solder resist layer on the build-up circuit layer.
26. The method of claim 24,
Wherein the solder resist layer is formed with openings such that connection pads of the build-up circuit layer are exposed.
26. The method of claim 25,
And a post formed on the exposed connection pad.
18. The method of claim 17,
Further comprising laminating the build-up circuit layer and the build-up insulation layer on one or both surfaces of the core substrate on which the build-up insulation layer is formed by repeating at least two or more times.
The method of claim 17,
Further comprising forming a single insulating layer on a build-up insulating layer between the build-up circuit layer formed on the core substrate and the build-up insulating layer or on the outermost layer.

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