JP4589519B2 - Manufacturing method of semiconductor circuit components - Google Patents

Manufacturing method of semiconductor circuit components Download PDF

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Publication number
JP4589519B2
JP4589519B2 JP2000342404A JP2000342404A JP4589519B2 JP 4589519 B2 JP4589519 B2 JP 4589519B2 JP 2000342404 A JP2000342404 A JP 2000342404A JP 2000342404 A JP2000342404 A JP 2000342404A JP 4589519 B2 JP4589519 B2 JP 4589519B2
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insulating resin
metal plate
semiconductor circuit
manufacturing
circuit component
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JP2002151622A (en
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明弘 浜野
広一 本多
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Description

【０００１】
【発明の属する技術分野】
本発明は、金属板上にビルドアップ形成した絶縁樹脂体に半導体素子を実装し、封止樹脂で樹脂封止した後、金属板をエッチングで除去して形成する半導体回路部品の製造方法に関する。
【０００２】
【従来の技術】
近年、半導体素子を実装して形成される半導体回路部品には、半導体素子の高集積化に伴ない半導体素子を搭載する回路基板の配線が高密度化しており、その対応の一例として、ビルドアップ法による多層配線基板が使用されている。このビルドアップ多層配線基板の代表的な製造方法は、先ず、ガラスエポキシ等からなるコア基板にスルーホール用の孔を穿設し、Ｐｄ等の触媒を付与し、全面に無電解銅めっきを施し、この上にフォトリソグラフィ法でドライフィルムレジストによる開口部を形成し、無電解銅めっき層に電流を通して開口部に電解銅めっき層を形成する。その後、ドライフィルムを除去し、露出した無電解銅めっき層をエッチングで除去し、無電解銅めっきと電解銅めっきからなる下層側の配線パターン層を形成する。そして、この配線パターン層上にスクリーン印刷やロールコーター等により感光性絶縁樹脂を塗布し、乾燥した後、感光性絶縁樹脂層上にビア形成用のパターンマスクを密着させ、紫外線で露光し、現像することでビアを有する感光性絶縁樹脂層を形成する。次に、この感光性絶縁樹脂層を硬化させて、下層側の絶縁樹脂層とし、このビアを伴う下層側の絶縁樹脂表面をクロム酸、過マンガン酸等の絶縁樹脂粗化液により粗化し、Ｐｄ等の触媒を付与した後、全面に無電解銅めっきを行った後、ドライフィルムを貼付し、パターンマスクを密着させ、紫外線で露光し、現像することで配線パターン導体やビア導体となる開口部を形成する。次いで、この開口部に電解銅めっきを形成し、ドライフィルムを剥離後、銅めっき表面をエッチングで、銅めっき層の薄い無電解銅めっき部分を剥離除去し、電解銅めっきで銅めっき層が厚くなった部分の配線パターン導体やビア導体を残すことで上層側の配線パターン層を形成する。以後、同様の工程を順次繰り返して多層化するものである。このようにして形成されたビルドアップ多層配線基板に半導体素子を実装し、封止樹脂で樹脂封止をし、外部端子としての半田ボールを形成して、半導体回路部品としている。
【０００３】
【発明が解決しようとする課題】
しかしながら、前述したような従来の半導体回路部品及びその製造方法には、次のような問題がある。
（１）ビルドアップ多層配線基板を形成するには、多数のスルーホールを形成したコア基板を使用するが、このコア基板はビルドアップ多層配線基板の製造コストに占める割合が高い。
（２）一方、市場の要求は低価格の商品にあり、半導体回路部品への更なるコストダウンの要求が高い。しかしながら、現行のコア基板を使用したビルドアップ多層配線基板ではコストダウンの要素が殆どない。
（３）また、近年、半導体素子のクロック周波数の高周波化が急速に進んでおり、この半導体素子を実装する基板にはインダクタンスを低減できる回路設計が求められている。現行のビルドアップ多層配線基板では、コア基板のスルーホール部のインダクタンスがその割合の殆どを占め、コア基板を使用する上ではインダクタンスの低減が期待できない。
（４）さらに、将来、クロック周波数が１ＧＨｚを超えると、現行のコア基板を使用してのビルドアップ多層配線基板では対応が困難と予想されている。
本発明は、かかる事情に鑑みてなされたものであって、コア基板を使用しないで、ビルドアップ回路形成がなされた絶縁樹脂体に半導体素子を実装し、安価で高周波特性に優れた半導体回路部品及びその製造方法を提供することを目的とする。
【０００４】
【課題を解決するための手段】
前記目的に沿う本発明に係る半導体回路部品は、下面に入出力端子を有し、配線パターン及びビア導体で回路が形成された絶縁樹脂体と半導体素子を接続し、封止樹脂で樹脂封止している半導体回路部品において、金属板上に形成された絶縁樹脂体に、半導体素子が実装され、樹脂封止された後に、金属板をエッチングで除去して形成されている。コア基板を必要としないことから製造コストを低く抑えられ、また、スルーホール部が存在しないので、インダクタンス低減の問題も起こらない。さらに、将来のクロック周波数が１ＧＨｚを超えた場合についても対応可能である。
ここで、半導体素子を絶縁樹脂体上面のフリップチップボンディング用のパッドに実装してもよい。これにより、実装面積を小さくすることができ、高密度で小型の半導体回路部品を提供できる。
また、半導体素子を予め電気特性が終了した良品回路の絶縁樹脂体上に実装することができる。これにより、断線やショートのある絶縁樹脂体への実装を避け、高価な半導体素子を無駄にすることがない。
【０００５】
前記目的に沿う本発明に係る半導体回路部品の製造方法は、金属板の片面に配線パターン及びビア導体からなる回路を備えた絶縁樹脂体を形成する工程と、回路の入出力端子部を露出するように、金属板にエッチングで孔を穿設し、孔に電気検査用のプローブを挿入し、電気検査する工程と、電気検査で良品とされた絶縁樹脂体に半導体素子を実装し、半導体素子を封止樹脂で封止する工程と、金属板の全てをエッチングで除去する工程とを含み、金属板に絶縁樹脂体を形成する工程の前において、金属板の片面のうち入出力端子部と対向する部分にＡｕめっきを施す。これにより、コア基板を必要としないので、比較的安価であり、インダクタンス低減の問題が起こらず、クロック周波数が１ＧＨｚを超える場合についても対応できる。さらに、半導体素子を実装する前に回路の電気検査を行うことで、良品回路をもつ絶縁樹脂体のみに半導体素子を実装できる。
ここで、複数層からなる絶縁樹脂層で絶縁樹脂体を形成してもよい。これにより、配線密度の高い多端子の半導体回路部品を製造することができる。
さらに、１枚の前記金属板に複数個の前記絶縁樹脂体を形成し、個片化切断することもできる。これにより、効率よく半導体回路部品を製造できる。また、個片化した後に、入出力端子に外部端子として半田ボールを形成することにより、ＢＧＡ（Ball Grid Array ）タイプの半導体回路部品を容易に形成することができる。
【０００６】
【発明の実施の形態】
続いて、添付した図面を参照しつつ、本発明を具体化した実施の形態について説明し、本発明の理解に供する。
ここに、図１は本発明の一実施の形態に係る半導体回路部品の部分拡大断面図、図２は本発明の一実施の形態に係る半導体回路部品の製造方法を説明するための部分拡大断面図である。
【０００７】
まず、図１を参照して、本発明の一実施の形態に係る半導体回路部品１０の構造を説明する。ビルドアップ層を形成するための土台となる金属板１１は、例えば、銅、銅合金、４２アロイ、ＳＵＳ３０４、ＳＵＳ４３０等が用いられ、樹脂との密着性を増すために、表面粗化が施されている。この金属板１１上に、ソルダーレジスト１２が形成されており、その開口部に金属被膜で形成された、入出力端子１３が形成されている。ソルダーレジスト１２上には、無電解銅めっき及び電解銅めっきにより配線パターン１３ａが形成されている。さらに、ソルダーレジスト１２上には、第１の絶縁樹脂層１４が形成され、この第１の絶縁樹脂層１４の所定位置には、フォトリソグラフィ法等でビアホール１５が形成されている。この第１の絶縁樹脂層１４の表面とビアホール１５とには、無電解銅めっき及び電解銅めっきにより、第１の配線パターン１６とビア導体１７が形成（回路の形成）され、入出力端子１３と、ソルダーレジスト１２上の配線パターン１３ａを通して、第１の絶縁樹脂層１４上の第１の配線パターン１６とが、ビア導体１７を介して電気的に接続されている。さらに、第１の配線パターン１６上に、第２の絶縁樹脂層１８が積層され、この第２の絶縁樹脂層１８の所定位置にフォトリソグラフィ法等でビアホール１５ａが形成され、第２の配線パターン１９とビア導体１７ａが形成されている。第１及び第２の絶縁樹脂層１４、１８によって絶縁樹脂体を形成している。さらに多層にする場合には上記方法を繰り返すことで形成される。
【０００８】
最上層の絶縁樹脂層（図１では第２の絶縁樹脂層１８）のビアホール１５ａ上に、接続部材２０を介して半導体素子２１が実装されている。さらに、半導体素子２１が封止樹脂２２によって樹脂封止されている。封止樹脂２２が形成された後、金属板１１をエッチングで除去して、下面に入出力端子１３を有する半導体回路部品１０が形成されている。なお、図１には、絶縁樹脂体は２層分の絶縁樹脂層（ソルダーレジスト層を入れたら３層分）のみが図示されているが、絶縁樹脂層の積層数は１層又は３層以上であってもよい。
【０００９】
次に、図１、図２を参照して、本発明の一実施の形態に係る半導体回路部品の製造方法について説明する。
（１）金属板１１の片面に回路を備えた絶縁樹脂体を形成する工程
金属板の片面にビルドアップ法により回路を形成するので、金属板は反りやすい。そこで、この金属板の選択として、反りを最小限に抑制するために、絶縁樹脂材料との熱膨張率差が小さく、且つ反りに対してある程度の機械強度を持つ材質が要求される。また、量産に適用できる安価である材質も要求される。その結果、銅、銅合金、４２アロイ、ＳＵＳ３０４、ＳＵＳ４３０等が揚げられるが、好ましい形態としては銅又は銅合金が選択される。板厚みは０．１〜０．５ｍｍ程度のものを使用する。ビルドアップに使用する材料は、既存のいずれの材料であっても適用可能である。また、プロセスについても既存のビア形成であるフォトビア方式、レーザービア方式等があり、回路形成方法としては、サブトラクティブ法、セミアディティブ法、フルアディティブ法等があり、特に限定するものではない。
【００１０】
ここでは、板厚み０．３ｍｍ程度のタフピッチ銅からなる金属板１１を使用して、セミアディティブ法によるビルドアップの製造方法で説明する。先ず、金属板１１と樹脂との密着性を高めるために、金属板１１の表面にジェットスクラブ処理等を施して表面粗化をする。金属板１１の裏面は、各種めっきやエッチングの処理から保護するために、耐薬品性に優れたカバーフィルムを形成する。この金属板１１の表面に、感光性のソルダーレジスト１２を約２０μｍ程度全面印刷し、フォトリソグラフィ法により、パターンマスクを載置し、例えば、６００ｍＪ／ｃｍ2 の紫外線で露光し、現像処理を行い、さらに、紫外線キュア、熱キュアを行い、硬化させて、入出力端子１３になる開口部を形成する。この開口部の金属板１１の表面には、金属被膜、例えば、Ａｕめっき、Ｎｉめっきを施す。なお、金属被膜として、Ａｕめっき及びＮｉめっきを施す場合は、後述する金属板１１を除去するときにＡｕめっき面がめっきレジストとなるようにＡｕめっきを先に行い、Ｎｉめっきを後に行う必要がある。Ａｕめっき、Ｎｉめっきは電解めっき、無電解めっき何れでもよく、めっき厚はＡｕめっきがＭａｘ０．１μｍ程度であり、ＮｉめっきがＭａｘ５μｍ程度である。
【００１１】
次いで、ソルダーレジスト１２の表面に配線パターン１３ａを形成する。これには、先ず、ソルダーレジスト１２と銅めっきとの密着性を高めるために、ソルダーレジスト１２の表面をクロム酸、過マンガン酸カリウム等により表面粗化をする。次いで、Ｐｄ等の触媒を付与した後、無電解銅めっきを施し、その上に感光性のドライフィルムレジストをラミネートし、パターンマスクを密着させ露光し、現像し、ドライフィルムレジストによる開口部を形成する。その後、無電解銅めっき層を通して電流を流し、開口部に電解銅めっき層を形成する。次に、ドライフィルムレジストを除去し、エッチングすることで、無電解銅めっき層のみの銅厚みの薄い部分をエッチング除去し、無電解銅めっきと電解銅めっきから成る配線パターン１３ａを形成する。
【００１２】
次に、樹脂との密着性を高めるために、銅の配線パターン１３ａの表面をＣＺ処理等で表面粗化した後、ソルダーレジスト１２上に感光性絶縁樹脂をスクリーン印刷やロールコーター等により塗布し、乾燥した後、パターンマスクを密着させ、紫外線で露光し、現像することでビアホール１５を開口させ、次いで、紫外線キュア、熱キュアを行い、硬化させて、第１の絶縁樹脂層１４を形成する。この第１の絶縁樹脂層１４上に、第１の配線パターン１６及びビア導体１７からなる回路を形成する方法は、上記ソルダーレジスト１２上に、配線パターン１３ａ、及び入出力端子１３部を形成した方法と同様の方法を採用する。
更に、上記方法を繰り返して行って、第２の絶縁樹脂層１８、ビアホール１５ａ、第２の配線パターン１９、ビア導体１７ａを形成する。
半導体素子が実装される第２の絶縁樹脂層１８上の第２の配線パターン１９及びビア導体１７ａの回路を形成した後、ソルダーレジストや金属被膜、例えば、Ｎｉめっき、Ａｕめっき等を施す。
上記工程により、金属板１１上に、半導体素子実装用の絶縁樹脂体が形成される。
【００１３】
（２）電気検査工程
通常、半導体素子実装用パッケージは、半導体素子２１を実装する前にパッケージとしての回路の断線、ショートの電気検査を実施する。これは、高価な半導体素子を半導体素子実装用パッケージに実装した後に、半導体素子実装用パッケージの電気的不具合により機能できないことを防止するためである。しかしながら、本発明の実施の形態では、金属板１１の上に半導体素子実装用の絶縁樹脂体を形成し、この状態で半導体素子２１を実装するので、金属板１１によって全ての端子がショートの状態にある。そこで、この電気検査を可能にする方法が、この工程である。
先ず、金属板１１の裏面に形成されているカバーフィルムを剥離し、感光性のドライフィルムを貼付し、パターンマスクを載置し、紫外線露光、現像を行って、入出力端子１３の部分を露出させるに足る大きさの開口部を形成する。次いで、ドライフィルムをエッチングレジストとして、ドライフィルムの開口部の金属板１１を通常のエッチング液、例えば、ＦｅＣｌ3 等のエッチング液を使用してエッチングをし、除去する。電気検査は金属板１１の開口された孔２３にプローブ２４を挿入し、入出力端子１３側と半導体素子の接続端子間を検査することができる断線、ショート検査機で検査する。検査結果での良品とされた絶縁樹脂体のみが半導体素子実装用に供される。
なお、多数の絶縁樹脂体を１枚の大型パネルで製作される場合には、この電気検査の結果をパネル上の個々の絶縁樹脂体に反映させる手段、例えば、不良絶縁樹脂体にマーキングを施す等の処置をすることが好ましい。
【００１４】
（３）半導体素子実装、樹脂封止工程
電気検査で良品となった絶縁樹脂体上に接続部材２０を介して半導体素子２１を載置し、赤外線リフロー炉やオーブン等で加熱し、接続する。接続方法はフリップチップボンディング方式が好ましい形態である。接続部材２０は通常半田バンプや、ワイヤボンディングを利用したＡｕボールバンプや、あるいは、Ａｕめっきバンプ等が絶縁樹脂体側のビアホール部及び／又は、半導体素子２１の接続パッドに形成される。
半導体素子２１が絶縁樹脂体に実装された後、半導体素子２１を封止樹脂２２で樹脂封止する。その方法は特に限定されるものではなく、通常のポッティング方式やトランスファーモールド方式等で行われる。
【００１５】
（４）金属板除去工程
金属板１１の全てを通常のエッチング液、例えば、ＦｅＣｌ3 等のエッチング液を使用してエッチングし、除去することで、半導体回路部品１０となる。
多数個の絶縁樹脂体を１枚の大型パネルで製作する場合には、ダイシングソー等で個片化切断して個々の半導体回路部品１０とする。
【００１６】
（５）外部端子形成工程
個片化された半導体回路部品１０の入出力端子１３に外部端子としての半田ボール２５を形成する。この半田ボール２５は、フラックスを使用した半田ボール転写方式により、半田ボールを所定の位置に配置させ、赤外線リフロー炉やオーブン等による加熱処理によって形成される。
【００１７】
【発明の効果】
請求項１〜３記載の半導体回路部品においては、絶縁樹脂体は金属板上に形成され、半導体素子が実装され、樹脂封止（気密封止）された後に、金属板をエッチングで除去して形成されているので、半導体回路部品にコア基板がつかわれていない。従って、製造コストを低く抑えられることができる。また、コア基板を使用していないのでスルーホールが存在せず、インダクタンス低減の問題は起こらない。さらに、将来のクロック周波数が１ＧＨｚを超えても対応可能となる。
特に、請求項２記載の半導体回路部品においては、半導体素子は絶縁樹脂体上面のフリップチップボンディング用のパッドに実装されるので、僅かな実装面積ですみ、高密度で小型の半導体回路部品を提供できる。
請求項３記載の半導体回路部品においては、半導体素子は予め電気特性が終了した良品回路の絶縁樹脂体上に実装されているので、不良の絶縁樹脂体には実装されることがなく、高価な半導体素子を無駄にすることがない。
【００１８】
請求項４〜６記載の半導体回路部品の製造方法は、金属板の片面に絶縁樹脂と配線パターン及びビア導体からなる回路を備えた絶縁樹脂体を形成する工程と、回路の入出力端子部を露出するように、金属板にエッチングで孔を穿設し、孔に電気検査用のプローブを挿入し、電気検査する工程と、電気検査で良品の絶縁樹脂体に半導体素子を実装し、半導体素子を封止樹脂で封止する工程と、金属板の全てをエッチングで除去する工程とを含むので、コア基板を必要とせず、比較的安価に製造でき、インダクタンス低減の問題が起こらず、クロック周波数１ＧＨｚについても対応でき、さらに、半導体素子を実装する前に回路の電気検査を行うことで、良品回路の絶縁樹脂体のみに半導体素子を実装できる。
特に、請求項５記載の半導体回路部品の製造方法においては、複数層からなる絶縁樹脂層で絶縁樹脂体を形成するので、配線密度の高い多端子の半導体回路部品の製造ができる。
請求項６記載の半導体回路部品の製造方法においては、１枚の金属板に複数個の絶縁樹脂体を形成し、個片化切断するので、効率よく形成できる。
【図面の簡単な説明】
【図１】 本発明の一実施の形態に係る半導体回路部品の部分拡大断面図である。
【図２】 本発明の一実施の形態に係る半導体回路部品の製造方法を説明するための部分拡大断面図である。
【符号の説明】
１０：半導体回路部品、１１：金属板、１２：ソルダーレジスト、１３：入出力端子、１３ａ：配線パターン、１４：第１の絶縁樹脂層、１５：ビアホール、１５ａ：ビアホール、１６：第１の配線パターン、１７：ビア導体、１７ａ：ビア導体、１８：第２の絶縁樹脂層、１９：第２の配線パターン、２０：接続部材、２１：半導体素子、２２：封止樹脂、２３：孔、２４：プローブ、２５：半田ボール[0001]
BACKGROUND OF THE INVENTION
The present invention is a semiconductor device mounted on the insulating resin body obtained by buildup on the metal plate, after resin sealing with the sealing resin, a method of manufacturing a semiconductor circuit portion product formed by removing the metal plate by etching .
[0002]
[Prior art]
In recent years, in semiconductor circuit components formed by mounting semiconductor elements, the wiring density of circuit boards on which semiconductor elements are mounted has become higher due to the higher integration of semiconductor elements. A multilayer wiring board by the method is used. A typical manufacturing method for this build-up multilayer wiring board is to first drill a hole for a through hole in a core substrate made of glass epoxy or the like, apply a catalyst such as Pd, and perform electroless copper plating on the entire surface. On this, an opening made of a dry film resist is formed by a photolithography method, and an electrolytic copper plating layer is formed in the opening by passing a current through the electroless copper plating layer. Thereafter, the dry film is removed, the exposed electroless copper plating layer is removed by etching, and a lower wiring pattern layer made of electroless copper plating and electrolytic copper plating is formed. Then, a photosensitive insulating resin is applied onto the wiring pattern layer by screen printing or a roll coater and dried, and then a pattern mask for forming vias is brought into close contact with the photosensitive insulating resin layer, exposed to ultraviolet rays, and developed. As a result, a photosensitive insulating resin layer having vias is formed. Next, the photosensitive insulating resin layer is cured to form a lower insulating resin layer, and the lower insulating resin surface with the vias is roughened with an insulating resin roughening solution such as chromic acid or permanganic acid, After applying a catalyst such as Pd, electroless copper plating is applied to the entire surface, then a dry film is applied, a pattern mask is adhered, exposed to ultraviolet rays, and developed to provide openings for wiring pattern conductors and via conductors. Forming part. Next, electrolytic copper plating is formed in this opening, and after the dry film is peeled off, the copper plating surface is etched and the thin electroless copper plating portion of the copper plating layer is peeled off and the copper plating layer is thickened by electrolytic copper plating. The wiring pattern layer on the upper layer side is formed by leaving the wiring pattern conductor and via conductor in the formed portion. Thereafter, the same process is sequentially repeated to form a multilayer. A semiconductor element is mounted on the build-up multilayer wiring board formed as described above, resin-sealed with a sealing resin, and solder balls as external terminals are formed to form a semiconductor circuit component.
[0003]
[Problems to be solved by the invention]
However, the conventional semiconductor circuit components and the manufacturing method thereof as described above have the following problems.
(1) To form a build-up multilayer wiring board, a core board having a large number of through holes is used, and this core board accounts for a large proportion of the manufacturing cost of the build-up multilayer wiring board.
(2) On the other hand, the market demand is for low-priced products, and there is a high demand for further cost reduction of semiconductor circuit components. However, the build-up multilayer wiring board using the current core board has almost no cost reduction factor.
(3) In recent years, the clock frequency of semiconductor elements has been rapidly increased, and a circuit design capable of reducing inductance is required for a substrate on which the semiconductor elements are mounted. In the current build-up multilayer wiring board, the inductance of the through hole portion of the core board occupies most of the ratio, and reduction of the inductance cannot be expected when the core board is used.
(4) Furthermore, when the clock frequency exceeds 1 GHz in the future, it is expected that it is difficult to cope with the build-up multilayer wiring board using the current core board.
SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and is a semiconductor circuit component that is inexpensive and has excellent high-frequency characteristics by mounting a semiconductor element on an insulating resin body on which a build-up circuit is formed without using a core substrate. And it aims at providing the manufacturing method.
[0004]
[Means for Solving the Problems]
The semiconductor circuit component according to the present invention that meets the above-mentioned object has an input / output terminal on the lower surface, connects an insulating resin body in which a circuit is formed with a wiring pattern and a via conductor, and a semiconductor element, and is sealed with a sealing resin. In a semiconductor circuit component, a semiconductor element is mounted on an insulating resin body formed on a metal plate and sealed with resin, and then the metal plate is removed by etching. Since a core substrate is not required, the manufacturing cost can be kept low, and since there is no through-hole portion, there is no problem of inductance reduction. Furthermore, it is possible to cope with a case where the future clock frequency exceeds 1 GHz.
Here, the semiconductor element may be mounted on a pad for flip chip bonding on the upper surface of the insulating resin body. As a result, the mounting area can be reduced, and a high-density and small-sized semiconductor circuit component can be provided.
In addition, the semiconductor element can be mounted on an insulating resin body of a non-defective circuit whose electrical characteristics have been finished in advance. Thus, mounting on an insulating resin body having a disconnection or a short circuit is avoided, and an expensive semiconductor element is not wasted.
[0005]
A method of manufacturing a semiconductor circuit component according to the present invention that meets the above-described object includes a step of forming an insulating resin body having a circuit comprising a wiring pattern and a via conductor on one side of a metal plate, and exposing an input / output terminal portion of the circuit. As described above, a hole is formed by etching in a metal plate, a probe for electrical inspection is inserted into the hole, electrical inspection is performed, and a semiconductor element is mounted on an insulating resin body that has been judged to be non-defective by electrical inspection. a step of sealing with a sealing resin, saw including a step of removing all of the metal plate by etching, before the step of forming the insulating resin material in a metal plate, input-output terminal portions of the one surface of the metal plate Au plating is applied to the part opposite to . Thereby, since the core substrate is not required, it is relatively inexpensive, the problem of inductance reduction does not occur, and the case where the clock frequency exceeds 1 GHz can be dealt with. Furthermore, by conducting an electrical inspection of the circuit before mounting the semiconductor element, the semiconductor element can be mounted only on an insulating resin body having a non-defective circuit.
Here, the insulating resin body may be formed of an insulating resin layer composed of a plurality of layers. Thereby, a multi-terminal semiconductor circuit component having a high wiring density can be manufactured.
Further, a plurality of the insulating resin bodies can be formed on one metal plate and cut into pieces. Thereby, a semiconductor circuit component can be manufactured efficiently. Further, by forming solder balls as external terminals on the input / output terminals after the separation, a BGA (Ball Grid Array) type semiconductor circuit component can be easily formed.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention.
FIG. 1 is a partially enlarged sectional view of a semiconductor circuit component according to an embodiment of the present invention. FIG. 2 is a partially enlarged sectional view for explaining a method for manufacturing a semiconductor circuit component according to an embodiment of the present invention. FIG.
[0007]
First, the structure of a semiconductor circuit component 10 according to an embodiment of the present invention will be described with reference to FIG. For example, copper, copper alloy, 42 alloy, SUS304, SUS430, or the like is used as the metal plate 11 as a base for forming the buildup layer, and surface roughening is performed to increase adhesion with the resin. ing. A solder resist 12 is formed on the metal plate 11, and an input / output terminal 13 formed of a metal film is formed in the opening. A wiring pattern 13a is formed on the solder resist 12 by electroless copper plating and electrolytic copper plating. Further, a first insulating resin layer 14 is formed on the solder resist 12, and a via hole 15 is formed at a predetermined position of the first insulating resin layer 14 by a photolithography method or the like. A first wiring pattern 16 and a via conductor 17 are formed (circuit formation) on the surface of the first insulating resin layer 14 and the via hole 15 by electroless copper plating and electrolytic copper plating. The first wiring pattern 16 on the first insulating resin layer 14 is electrically connected via the via conductor 17 through the wiring pattern 13 a on the solder resist 12. Further, a second insulating resin layer 18 is laminated on the first wiring pattern 16, and a via hole 15a is formed at a predetermined position of the second insulating resin layer 18 by a photolithography method or the like. The second wiring pattern 19 and a via conductor 17a are formed. The first and second insulating resin layers 14 and 18 form an insulating resin body. In the case of further multilayering, the above method is repeated.
[0008]
A semiconductor element 21 is mounted on the via hole 15a of the uppermost insulating resin layer (second insulating resin layer 18 in FIG. 1) via a connecting member 20. Further, the semiconductor element 21 is sealed with a sealing resin 22. After the sealing resin 22 is formed, the metal plate 11 is removed by etching, and the semiconductor circuit component 10 having the input / output terminals 13 on the lower surface is formed. FIG. 1 shows only two insulating resin layers (three layers if a solder resist layer is inserted), but the number of insulating resin layers is one or three or more. It may be.
[0009]
Next, a method for manufacturing a semiconductor circuit component according to an embodiment of the present invention will be described with reference to FIGS.
(1) Process of forming an insulating resin body having a circuit on one side of the metal plate 11 Since a circuit is formed on one side of the metal plate by a build-up method, the metal plate is likely to warp. Therefore, as a selection of the metal plate, a material having a small difference in thermal expansion coefficient from the insulating resin material and having a certain mechanical strength against the warp is required in order to suppress the warp to the minimum. In addition, an inexpensive material applicable to mass production is also required. As a result, copper, copper alloy, 42 alloy, SUS304, SUS430 and the like are fried, but copper or copper alloy is selected as a preferred form. A plate thickness of about 0.1 to 0.5 mm is used. The material used for build-up is applicable to any existing material. In addition, there are a photo via method and a laser via method, which are existing via formation, as a process, and a circuit formation method includes a subtractive method, a semi-additive method, a full additive method, and the like, and is not particularly limited.
[0010]
Here, a description will be given of a build-up manufacturing method by a semi-additive method using a metal plate 11 made of tough pitch copper having a plate thickness of about 0.3 mm. First, in order to improve the adhesion between the metal plate 11 and the resin, the surface of the metal plate 11 is subjected to a jet scrub treatment or the like to roughen the surface. In order to protect the back surface of the metal plate 11 from various plating and etching processes, a cover film having excellent chemical resistance is formed. A photosensitive solder resist 12 is printed on the entire surface of the metal plate 11 with a thickness of about 20 μm, a pattern mask is placed by photolithography, and exposed to, for example, 600 mJ / cm 2 of ultraviolet light and developed. Further, ultraviolet curing and thermal curing are performed and cured to form an opening that becomes the input / output terminal 13. A metal coating, for example, Au plating or Ni plating is applied to the surface of the metal plate 11 in the opening. In addition, when performing Au plating and Ni plating as a metal coating, when removing the metal plate 11 mentioned later, it is necessary to perform Au plating first so that an Au plating surface may become a plating resist, and to perform Ni plating later. is there. The Au plating and the Ni plating may be either electrolytic plating or electroless plating, and the plating thickness is about 0.1 μm for Au plating and about 5 μm for Ni plating.
[0011]
Next, a wiring pattern 13 a is formed on the surface of the solder resist 12. For this purpose, first, the surface of the solder resist 12 is roughened with chromic acid, potassium permanganate or the like in order to improve the adhesion between the solder resist 12 and the copper plating. Next, after applying a catalyst such as Pd, electroless copper plating is performed, a photosensitive dry film resist is laminated thereon, a pattern mask is adhered, exposed, developed, and an opening is formed by the dry film resist. To do. Thereafter, a current is passed through the electroless copper plating layer to form an electrolytic copper plating layer in the opening. Next, the dry film resist is removed and etched, so that the thin copper portion of only the electroless copper plating layer is removed by etching to form a wiring pattern 13a composed of electroless copper plating and electrolytic copper plating.
[0012]
Next, in order to improve the adhesion to the resin, the surface of the copper wiring pattern 13a is roughened by CZ treatment or the like, and then a photosensitive insulating resin is applied onto the solder resist 12 by screen printing or a roll coater. After drying, the pattern mask is brought into close contact, exposed to ultraviolet light, and developed to open the via hole 15, and then cured by ultraviolet curing and thermal curing to form the first insulating resin layer 14. . In the method of forming a circuit including the first wiring pattern 16 and the via conductor 17 on the first insulating resin layer 14, the wiring pattern 13a and the input / output terminal 13 are formed on the solder resist 12. A method similar to the method is adopted.
Further, the above method is repeated to form the second insulating resin layer 18, the via hole 15a, the second wiring pattern 19, and the via conductor 17a.
After the circuit of the second wiring pattern 19 and the via conductor 17a on the second insulating resin layer 18 on which the semiconductor element is mounted is formed, a solder resist or a metal coating such as Ni plating or Au plating is applied.
Through the above process, an insulating resin body for mounting a semiconductor element is formed on the metal plate 11.
[0013]
(2) Electrical inspection process Normally, a semiconductor element mounting package performs an electrical inspection of circuit breakage and short circuit as a package before mounting the semiconductor element 21. This is to prevent an expensive semiconductor element from functioning due to an electrical failure of the semiconductor element mounting package after being mounted on the semiconductor element mounting package. However, in the embodiment of the present invention, since an insulating resin body for mounting a semiconductor element is formed on the metal plate 11 and the semiconductor element 21 is mounted in this state, all terminals are short-circuited by the metal plate 11. It is in. Therefore, this process is a method that enables this electrical inspection.
First, the cover film formed on the back surface of the metal plate 11 is peeled off, a photosensitive dry film is attached, a pattern mask is placed, UV exposure and development are performed, and the input / output terminal 13 portion is exposed. An opening having a size sufficient to be formed is formed. Next, using the dry film as an etching resist, the metal plate 11 at the opening of the dry film is etched and removed using a normal etching solution, for example, an etching solution such as FeCl 3 . In the electrical inspection, the probe 24 is inserted into the opened hole 23 of the metal plate 11 and inspected by a disconnection / short inspection machine capable of inspecting between the input / output terminal 13 side and the connection terminal of the semiconductor element. Only the insulating resin bodies determined as non-defective products in the inspection results are provided for mounting semiconductor elements.
When a large number of insulating resin bodies are manufactured with a single large panel, means for reflecting the result of this electrical inspection on individual insulating resin bodies on the panel, for example, marking is performed on defective insulating resin bodies. It is preferable to perform such treatment.
[0014]
(3) Mounting of semiconductor element and resin sealing process A semiconductor element 21 is placed on an insulating resin body that has become a non-defective product by electrical inspection via a connection member 20, and is heated and connected in an infrared reflow furnace or oven. The connection method is preferably a flip chip bonding method. As the connection member 20, a solder bump, an Au ball bump using wire bonding, an Au plating bump, or the like is usually formed in the via hole portion on the insulating resin body side and / or the connection pad of the semiconductor element 21.
After the semiconductor element 21 is mounted on the insulating resin body, the semiconductor element 21 is resin-sealed with a sealing resin 22. The method is not particularly limited, and is performed by a normal potting method, a transfer mold method, or the like.
[0015]
(4) Metal plate removal step The metal plate 11 is etched and removed using a normal etching solution, for example, an etching solution such as FeCl 3 , so that the semiconductor circuit component 10 is obtained.
When manufacturing a large number of insulating resin bodies with a single large panel, the individual semiconductor circuit components 10 are obtained by cutting them into pieces with a dicing saw or the like.
[0016]
(5) External terminal formation process Solder balls 25 as external terminals are formed on the input / output terminals 13 of the separated semiconductor circuit component 10. The solder balls 25 are formed by a heat treatment using an infrared reflow furnace, an oven, or the like by placing the solder balls at predetermined positions by a solder ball transfer method using a flux.
[0017]
【The invention's effect】
4. The semiconductor circuit component according to claim 1, wherein the insulating resin body is formed on the metal plate, the semiconductor element is mounted, and after the resin sealing (airtight sealing), the metal plate is removed by etching. Since it is formed, the core substrate is not used for the semiconductor circuit component. Therefore, the manufacturing cost can be kept low. Further, since the core substrate is not used, there is no through hole, and there is no problem of inductance reduction. Furthermore, it is possible to cope with future clock frequencies exceeding 1 GHz.
Particularly, in the semiconductor circuit component according to claim 2, since the semiconductor element is mounted on the flip chip bonding pad on the upper surface of the insulating resin body, a small mounting area is required, and a high-density and small-sized semiconductor circuit component is provided. it can.
In the semiconductor circuit component according to claim 3, since the semiconductor element is mounted on the insulating resin body of a non-defective circuit whose electrical characteristics have been finished in advance, it is not mounted on a defective insulating resin body and is expensive. There is no waste of semiconductor elements.
[0018]
A method of manufacturing a semiconductor circuit component according to claim 4, wherein a step of forming an insulating resin body provided with a circuit comprising an insulating resin, a wiring pattern and a via conductor on one side of a metal plate, and an input / output terminal portion of the circuit are provided. A hole is formed by etching in the metal plate so as to be exposed, a probe for electrical inspection is inserted into the hole, and an electrical inspection is performed, and a semiconductor element is mounted on a non-defective insulating resin body by electrical inspection. Including a step of sealing the metal plate with a sealing resin and a step of removing all of the metal plate by etching, so that a core substrate is not required and can be manufactured at a relatively low cost, without causing problems of inductance reduction, and a clock frequency. 1 GHz can also be supported, and furthermore, by conducting an electrical inspection of the circuit before mounting the semiconductor element, the semiconductor element can be mounted only on the insulating resin body of the non-defective circuit.
In particular, in the method of manufacturing a semiconductor circuit component according to claim 5, since the insulating resin body is formed by the insulating resin layer composed of a plurality of layers, a multi-terminal semiconductor circuit component having a high wiring density can be manufactured.
In the method of manufacturing a semiconductor circuit component according to claim 6, since a plurality of insulating resin bodies are formed on a single metal plate and cut into pieces, it can be formed efficiently.
[Brief description of the drawings]
FIG. 1 is a partially enlarged cross-sectional view of a semiconductor circuit component according to an embodiment of the present invention.
FIG. 2 is a partially enlarged cross-sectional view for explaining a method for manufacturing a semiconductor circuit component according to one embodiment of the present invention.
[Explanation of symbols]
10: semiconductor circuit component, 11: metal plate, 12: solder resist, 13: input / output terminal, 13a: wiring pattern, 14: first insulating resin layer, 15: via hole, 15a: via hole, 16: first wiring Pattern: 17: Via conductor, 17a: Via conductor, 18: Second insulating resin layer, 19: Second wiring pattern, 20: Connection member, 21: Semiconductor element, 22: Sealing resin, 23: Hole, 24 : Probe, 25: Solder ball

Claims (4)

金属板の片面に配線パターン及びビア導体からなる回路を備えた絶縁樹脂体を形成する工程と、前記回路の入出力端子部を露出するように、前記金属板にエッチングで孔を穿設し、該孔に電気検査用のプローブを挿入し、電気検査する工程と、前記電気検査で良品とされた前記絶縁樹脂体に半導体素子を実装し、該半導体素子を封止樹脂で封止する工程と、前記金属板の全てをエッチングで除去する工程と、を含み、
前記金属板に前記絶縁樹脂体を形成する工程の前において、前記金属板の前記片面のうち前記入出力端子部と対向する部分にＡｕめっきを施す半導体回路部品の製造方法。A step of forming an insulating resin body provided with a circuit comprising a wiring pattern and a via conductor on one side of the metal plate, and a hole is formed in the metal plate by etching so as to expose an input / output terminal portion of the circuit; Inserting a probe for electrical inspection into the hole and performing electrical inspection; mounting a semiconductor element on the insulating resin body made good by the electrical inspection; and sealing the semiconductor element with a sealing resin; , look-containing and a step of removing all of the metal plate by etching,
Prior to the step of forming the insulating resin body on the metal plate, a method of manufacturing a semiconductor circuit component in which Au plating is performed on a portion of the one surface of the metal plate facing the input / output terminal portion . 請求項１記載の半導体回路部品の製造方法において、複数層からなる絶縁樹脂層で前記絶縁樹脂体を形成することを特徴とする半導体回路部品の製造方法。 2. The method of manufacturing a semiconductor circuit component according to claim 1 , wherein the insulating resin body is formed of a plurality of insulating resin layers. 請求項１又は２記載の半導体回路部品の製造方法において、１枚の前記金属板に複数個の前記絶縁樹脂体を形成し、個片化切断することを特徴とする半導体回路部品の製造方法。 3. The method of manufacturing a semiconductor circuit component according to claim 1 , wherein a plurality of the insulating resin bodies are formed on one metal plate and cut into pieces. 請求項１ないし３いずれか１項に記載の半導体回路部品の製造方法において、 In the manufacturing method of the semiconductor circuit component according to any one of claims 1 to 3,
前記Ａｕめっきを施す前に、前記金属板の前記片面に、前記入出力端子部を形成する部分に開口部を有するソルダーレジスト層を形成し、Before applying the Au plating, a solder resist layer having an opening in the portion where the input / output terminal portion is formed is formed on the one surface of the metal plate,
前記絶縁樹脂体を形成する工程において、前記ソルダーレジスト層上に前記絶縁樹脂体を形成する半導体回路部品の製造方法。A method of manufacturing a semiconductor circuit component, wherein in the step of forming the insulating resin body, the insulating resin body is formed on the solder resist layer.
JP2000342404A 2000-11-09 2000-11-09 Manufacturing method of semiconductor circuit components Expired - Fee Related JP4589519B2 (en)

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JP2005251780A (en) * 2004-03-01 2005-09-15 Matsushita Electric Ind Co Ltd Semiconductor circuit component and its manufacturing method
CN1791311B (en) * 2004-12-01 2012-02-22 新光电气工业株式会社 Method of manufacturing a circuit substrate and method of manufacturing an electronic parts packaging structure
JP5653144B2 (en) * 2004-12-16 2015-01-14 新光電気工業株式会社 Manufacturing method of semiconductor package
KR100887475B1 (en) * 2007-02-26 2009-03-10 주식회사 네패스 Semiconductor package and fabrication method thereof
JP5545779B2 (en) * 2012-11-06 2014-07-09 新光電気工業株式会社 WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
JP7007882B2 (en) 2017-12-08 2022-01-25 新光電気工業株式会社 Wiring board and its manufacturing method

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WO1995026047A1 (en) * 1994-03-18 1995-09-28 Hitachi Chemical Company, Ltd. Semiconductor package manufacturing method and semiconductor package
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JPH10125818A (en) * 1996-10-16 1998-05-15 Toppan Printing Co Ltd Substrate for semiconductor device, semiconductor device and manufacture thereof

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JPH10125818A (en) * 1996-10-16 1998-05-15 Toppan Printing Co Ltd Substrate for semiconductor device, semiconductor device and manufacture thereof

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