TWI404468B - Package substrate having single-layer circuit and fabrication method thereof - Google Patents

Abstract

Disclosed is a package substrate formed with a single-layer circuit, including a substrate body have upper and lower surfaces, a circuit layer formed on the upper surface, a strengthened layer formed on the lower surface, and an insulating protective layer formed on the upper and lower surfaces of the substrate body, the circuit layer and the strengthened layer, thereby providing a warpage-preventing substrate. The invention further provides a method for fabricating the package substrate as described above.

Description

Single-layer circuit package substrate and preparation method thereof

The invention relates to a package substrate, in particular to a package substrate of a single layer circuit and a preparation method thereof.

With the evolution of semiconductor technology, semiconductor products have developed different package product types. Generally, a package substrate of a multi-layer circuit is provided with a semiconductor chip having a strong electrical function, so as to achieve a line out function by a circuit layer of the package substrate, and then the package substrate and the wafer are placed on a motherboard or other Circuit board. As shown in Fig. 1, a package substrate 1 of a conventional multilayer wiring is formed by forming a build-up wiring layer 12 on a substrate body 10 having an upper and lower surface 10a, 10b having a wiring layer 11. As the number of the wiring layers 11, 12 of the package substrate 1 increases, the manufacturing cost increases, and the manufacturing time also increases.

Therefore, when the package substrate is configured with a lower-order semiconductor wafer, and the above-mentioned high-order package substrate is not required, the industry has developed a single-layer circuit package substrate to reduce production cost and reduce production time, thereby facilitating the amount. Production.

As shown in FIG. 2, it is a package substrate 2 of a conventional single-layer circuit, comprising: a substrate body 20 having an upper surface 20a and a lower surface 20b; a circuit layer 22 formed on the upper surface 20a of the substrate body 20, A first insulating protective layer 23a formed on the upper surface 20a of the substrate body 20 and the wiring layer 22, and a second insulating protective layer 23b formed on the lower surface 20b of the substrate body 20. The substrate body 20 has a through slot 200 for communicating with the upper surface 20a and the lower surface 20b of the substrate body 20, and the circuit layer 22 has a wire pad 220 for electrically connecting the wafer for wire bonding (or metallization). a bump pad of the bump) and a ball pad 221 for electrically connecting the solder ball of the circuit board. Furthermore, the first insulating protective layer 23a has a first opening 230a for exposing the bonding pad 220 to the first opening 230a, and the second insulating protective layer 23b has a second opening 230b for communicating with the through slot 200. The ball pad 221 is exposed in the through slot 200 and the second opening 230b. Moreover, the wire bonding pad 220 and the ball pad 221 have a surface treatment layer 24, which is one of an alloy of nickel, palladium, gold, or a plurality of layers.

However, since the conventional package substrate 2 is formed only on one side (upper surface 20a) of the substrate body 20, the circuit layer 11 having a symmetrical number of layers on the upper and lower sides of the package substrate 1 of the multilayer wiring cannot be used. 12, in order to cancel each other's stress, resulting in a problem of unidirectional warpage of the package substrate 2 of the single-layer circuit, and thus the subsequent packaging process such as the connection of the wafer, or the reliability of the terminal product is not good. And other issues.

Therefore, how to provide a single-layer circuit package substrate to overcome the problem of substrate warpage of the prior art is an important issue.

In order to overcome the problem of the warpage of the prior art, the present invention provides a package substrate of a single-layer circuit, comprising: a substrate body having a first surface and a second surface opposite to each other, formed on the first surface of the substrate body a circuit layer, a strengthening layer formed on the second surface of the substrate body, a first insulating protective layer formed on the first surface of the substrate body and the circuit layer, and a second surface and a strengthening layer formed on the substrate body The second insulating protective layer on the top.

In the above package substrate, the substrate body has a groove for communicating with the first surface and the second surface of the substrate body, and a portion of the first surface of the substrate body (the surface having no wiring layer above) is a spacer region. The enhancement layer corresponds to the spacer. Also, the thickness of the reinforcing layer may be greater or less than the thickness of the wiring layer. Furthermore, the first insulating protective layer has a first opening such that one side of the wiring layer is exposed to the first opening, and the second insulating protective layer has a second opening to communicate the through-groove, so that the circuit layer The other side is exposed in the through slot and the second opening.

As can be seen from the above, the package substrate of the single-layer circuit of the present invention has a reinforcing layer on the second surface of the substrate body, so that the stress on one side of the substrate body is balanced with the other side, compared with the prior art. The package substrate of the asymmetric single-layer circuit can mutually offset the stress, thereby overcoming the problem of unidirectional warpage.

In addition, according to the package substrate aspect of the single-layer circuit of the present invention, the present invention provides a method for manufacturing the package substrate of the single-layer circuit, and the specific technical details thereof will be described later.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower" and "one" are used in the description for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship may be changed or Adjustments, where there is no material change, are considered to be within the scope of the invention.

Please refer to FIGS. 3A to 3E for the manufacturing method of the package substrate of the single layer circuit of the present invention.

As shown in FIG. 3A, a substrate body 30 having an upper surface (first surface) 30a and a lower surface (second surface) 30b is provided, and a metal is applied on the upper and lower surfaces 30a, 30b of the substrate body 30. Layers 300a, 300b.

In this embodiment, a copper foil (metal layer 300a, 300b) is pressed on both sides of the Prepreg material (substrate body 30) to form a copper foil substrate, and the BT material is not used as the core board, so that the production cost can be reduced. .

As shown in FIG. 3B, a patterning process is performed to form a first resist layer 31a and a second resist layer 31b on the metal layers 300a, 300b of the upper and lower surfaces 30a, 30b of the substrate body 30, respectively.

In this embodiment, the positions of the first resist layer 31a and the second resist layer 31b are shifted from each other, that is, the same position on the upper and lower sides of the substrate body 30 does not have a resist layer at the same time. However, this is one of the many implementations, and the layout of the upper and lower barrier layers still varies according to product requirements.

Furthermore, the first resistive layer 31a and the second resistive layer 31b may be photoresists to displace the first resistive layer 31a and the second resistive layer 31b from each other by exposure and development.

As shown in FIG. 3C, the exposed metal layers 300a, 300b of the upper and lower surfaces 30a, 30b of the substrate body 30 are etched away, so that a portion of the upper surface 30a of the substrate body 30 is separated by a metal layer 300a to form a spacer. 301, and the metal layer 300a under the first resist layer 31a serves as a wiring layer 32a, and the metal layer 300b under the second resist layer 31b serves as a reinforcing layer 32b.

The circuit layer 32a has an upper side (third surface) 320a and a lower side (fourth surface) 321a, and a lower side 321a is bonded to the upper surface 30a of the substrate body 30.

The thickness of the reinforcing layer 32b may also be equal to, greater than or less than the thickness of the circuit layer 32a, by forming a copper foil (metal layer 300a, 300b) on both sides of the Prepreg material (substrate body 30) to form In the case of a copper foil substrate, the copper foil on one side may be thicker, thinner than or equal to the copper foil on the other side as required.

Therefore, the present invention can form a different type of strengthening layer by patterning different kinds of copper foils, or control the thickness of the copper foil to achieve different thicknesses of the reinforcing layer and the circuit layer, so as to achieve the upper and lower surfaces of the structure. The purpose of stress.

Then, the first resistive layer 31a and the second resistive layer 31b are removed, so that the wiring layer 32a is formed on the upper surface 30a of the substrate body 30, and the upper side 320a of the circuit layer 32a has a wire pad 320 (or for planting) A bump pad of the metal bump, and the reinforcing layer 32b is formed on the lower surface 30b of the substrate body 30 and corresponds to the spacer 301.

The upper and lower surfaces 30a, 30b of the substrate body 30 are covered with a metal material (the wiring layer 32a and the reinforcing layer 32b) by a patterning process, and the upper and lower positions of the circuit layer 32a and the reinforcing layer 32b are shifted from each other. That is, the same position on the upper and lower sides of the substrate body 30 does not have a copper layer at the same time.

Further, the reinforcing layer 32b may have a mesh shape or may be formed in other shapes depending on the wiring layer 32a.

As shown in FIG. 3D, a plurality of through slots 300 are formed in the substrate body 30 to communicate the upper and lower surfaces 30a, 30b of the substrate body 30, so that a portion of the lower side 321a of the circuit layer 32a is exposed to the through slots. In 300, 俾 is used as a ball pad 321 .

As shown in FIG. 3E, a first insulating protective layer 33a is formed on the upper surface 30a of the substrate body 30 and the circuit layer 32a. The first insulating protective layer 33a has a plurality of first openings 330a for the bonding pads 320. Correspondingly exposed to each of the first openings 330a.

At the same time, a second insulating protective layer 33b is formed on the lower surface 30b of the substrate body 30 and the reinforcing layer 32b. The second insulating protective layer 33b has a plurality of second openings 330b for connecting the through slots 300. The ball pad 321 is also exposed to each of the second openings 330b to complete the fabrication of the package substrate 3.

In the embodiment, the first and second insulating protective layers 33a, 33b are solder resist layers, and the aperture of the second opening 330b is larger than the aperture of the through slot 300, so that the second opening 330b is completely The through slot 300 is exposed.

Moreover, the package substrate 3 can be formed on the wire pad 320 or the ball pad 321 as needed, and the surface treatment layer 34 is an alloy of nickel, palladium, gold, or a plurality of layers of metal. One.

In addition, since the reinforcing layer 32b has no electrical function, the second opening 330b does not need to expose the reinforcing layer 32b.

In summary, the package substrate of the single-layer circuit of the present invention and the method for fabricating the same are mainly designed by designing a non-electrically conductive metal layer on the lower surface 30b of the package substrate 3 (on the side without the wiring layer 32a) (strengthening layer) 32b), in order to balance the stress, effectively achieve the purpose of avoiding warpage of the package substrate 3.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1,2,3. . . Package substrate

10,20,30. . . Substrate body

10a, 20a, 30a. . . Upper surface

10b, 20b, 30b. . . lower surface

11,12,22,32a. . . Circuit layer

200,300. . . Grooving

220,320. . . Line mat

221,321. . . Ball pad

23a, 33a. . . First insulating protective layer

23b, 33b. . . Second insulating protective layer

230a, 330a. . . First opening

230b, 330b. . . Second opening

24,34. . . Surface treatment layer

300a, 300b. . . Metal layer

301. . . Spacer

31a. . . First resistive layer

31b. . . Second resistive layer

32b. . . Strengthening layer

320a. . . Upper side

321a. . . Lower side

1 is a schematic cross-sectional view of a package substrate of a conventional multilayer circuit;

2 is a schematic cross-sectional view of a package substrate of a conventional single-layer line;

3A to 3E are schematic cross-sectional views showing a method of manufacturing a package substrate of a single-layer wiring of the present invention.

3. . . Package substrate

30. . . Substrate body

30a. . . Upper surface

30b. . . lower surface

300. . . Grooving

32a. . . Circuit layer

320. . . Line mat

321. . . Ball pad

32b. . . Strengthening layer

33a. . . First insulating protective layer

33b. . . Second insulating protective layer

330a. . . First opening

330b. . . Second opening

34. . . Surface treatment layer

Claims (14)

A package substrate of a single-layer circuit includes: a substrate body having opposite first and second surfaces, and the substrate body has a plurality of slots for communicating with the first surface and the second surface of the substrate body; a circuit layer is formed on the first surface of the substrate body, such that the first surface of the substrate body on which the circuit layer is not formed is used as a spacer, and the circuit layer has a third surface and a fourth surface opposite to each other. Forming a portion of the fourth surface of the circuit layer in the plurality of through grooves; a reinforcing layer formed on the second surface of the substrate body and corresponding to the spacer; a first insulating protective layer formed on the substrate a first surface of the body and the circuit layer, and having a plurality of first openings, wherein a portion of the third surface of the circuit layer is exposed to the first openings; and a second insulating protective layer is formed on the substrate body The two surfaces and the reinforcing layer have a plurality of second openings to expose a portion of the fourth surface of the circuit layer corresponding to the grooves. The package substrate of the single-layer circuit according to claim 1, wherein a portion of the fourth surface exposed by the circuit layer in the through-hole is used as a ball-forming pad. The package substrate of the single-layer circuit of claim 1, wherein a portion of the third surface exposed by the circuit layer in the first opening is used as a bump pad or a wire pad. A package substrate of a single-layer line as described in claim 1 of the patent scope, The thickness of the reinforcing layer is greater or smaller than the thickness of the wiring layer. The package substrate of the single-layer circuit according to claim 1, wherein the first or second insulating protective layer is a solder resist layer. The package substrate of the single-layer circuit of claim 1, wherein the aperture of the second opening is larger than the aperture of the through slot, so that the second opening completely exposes the through slot. The package substrate of the single-layer circuit according to claim 1, further comprising a surface treatment layer formed on the exposed third or fourth surface of the circuit layer. A method for manufacturing a package substrate of a single-layer circuit includes: providing a substrate body having a first surface and a second surface; forming a circuit layer on the first surface of the substrate body, so that the substrate body is not formed a first surface of the circuit layer is used as a spacer, and a reinforcing layer is formed on the second surface of the substrate body and corresponds to the spacer region, and the circuit layer has opposite third and fourth surfaces, the circuit layer The fourth surface is bonded to the first surface of the substrate body; a plurality of grooves are formed in the substrate body to communicate with the first surface and the second surface of the substrate body, so that a portion of the fourth surface of the circuit layer is exposed And forming a first insulating protective layer on the first surface of the substrate body and the circuit layer, the first insulating protective layer having a plurality of first openings, such that a portion of the third surface of the circuit layer is exposed The first openings and forming a second insulating protective layer on the second surface of the substrate body and the reinforcing layer The second insulating protective layer has a plurality of second openings to communicate the through grooves to expose a portion of the fourth surface of the circuit layer. The method for manufacturing a package substrate of a single-layer circuit according to claim 8, wherein a portion of the fourth surface exposed by the circuit layer in the through-hole is used as a ball-forming pad. The method of manufacturing a package substrate of a single-layer circuit according to claim 8, wherein a portion of the third surface exposed by the circuit layer in the first opening is used as a bump pad or a wire pad. The method for manufacturing a package substrate of a single-layer circuit according to claim 8, wherein the thickness of the reinforcement layer is greater than or less than a thickness of the circuit layer. The method for manufacturing a package substrate of a single-layer circuit according to claim 8, wherein the first or second insulating protective layer is a solder resist layer. The method for manufacturing a package substrate of a single-layer circuit according to claim 8, wherein the aperture of the second opening is larger than the aperture of the through slot, so that the second opening completely exposes the through slot. The method for manufacturing a package substrate of a single-layer circuit according to claim 8 further comprises forming a surface treatment layer on the exposed third or fourth surface of the circuit layer.