1247363 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體載板及其製造方式，尤指一種 對於高密度及高散熱的載板以及無核心載板（c〇reless Substrate)，提供實心微小導孔之高密度，高良率製作方法。 【先前技術】 由於電子產品輕薄短小之趨勢，加上功能之不斷增多，使得 1C之I/O數快速增加，相對的封裝技術也不斷更新，由早期插件 式到表面黏著〔SMT〕·、打線式球狀陣列〔BGA〕，現今在高階產 品中已多數採用增層法製作ic載板，例如覆晶載板(FlipChip)、 多晶載板（MCM-Multi-Chip Module BGA)、含散熱片Ic載板 (Embedded Thermal Dissipation)、無電導線載板(Wire—free) 等’封裝密度也不斷地提高。然:而，此種高密度增層載板需要使 用填孔電鑛(Via Filled Plating)之結構，制之雷射鑽微小導 孔再電鍍之技術製程及結構，無論在設備投資不僅昂貴，在製造 方法上更有許多缺點。習知的IC載板結構—般為二層至八層的多 層印刷電路板，其所用材料為_或有機材料，而其多層結構的 線路通導則以機械鑽孔或雷射鑽微小孔為之，再配合電鍵導孔方 式。因雷射鑽微小孔孔内品質檢查不易，而且造成之缺點如導孔 輕微開路或孔域諫ierQ Via Qpen)，以現植增路電性測試 機不易伽彳到。等產品送至客戶難，在織過賴受多次熱應 力才造成斷路，發現問題時已經造成大量損失。 1247363 雷射鑽第二=技:較(== 孔Ci射鑽孔時造成“鍍= ί ΐί!( ) ’圖—（D)所示為電職孔時產生氣 拾杏^疋微小孔之孔内品㈣題或填孔紐時所產生問題，因 一苎均以抽檢為之。所以傳統習用之製造方法，無Ξ ㈣、ίί本及1^信賴性之㊅密度增層IC載板之製作。開發新晶片 封裝載板的結構及製造方法以提供解崎策乃是#務之急。 【發明内容】 < 基於上述習知麟之缺失’本拥提供—種高密度增層 1C載板結構’其主要特徵在於採用疊孔(Stack Via)結構之實心微 小導孔(Solid Micro Via)，除了傳統之核心載板，本發明亦可實 施於無核心載板製作，以滿足高密度IC載板對散熱，信賴性有更 高之需求。 本發明更提供一種南密度增層1C載板製作方法，主要精神在 於以高密度載板對填孔電鍍(Via Filled Plating)，取代習知之 以雷射鑽孔再加以電鍍之技術，以提供低成本提升良率之Ic载 板。 基於上述之目標，本發明提供一種以多層感光阻劑形成線路 及微小導孔，配合傳統電鍍蝕刻剥阻劑及電鍍製作金屬柱，如鋼 柱（Copper Column)，方式形成實心微小導孔(Sol id Micro Via)， 1247363 再施以增層材料及金屬接連層（可為銅皮），配合研磨方法將微小 導孔之連接面打開’再施以沉積金屬（如化學銅），即可連接至外 層線路訊麟。如此，金屬柱可提供_高溫時材料應力變化的 緩衝功能，也可提供高散熱傳導性能。 * ;、 _、 同時，此方法也可提供未來更輕薄之載板製作，如無核心 (Coreless)載板之製作，以更高密度之疊孔結構，與填孔鍍等方 式’更可大幅降低完絲板厚‘度。此製造方法解決習知雷騎微 小孔再施以狀缺失，且可因應未來無核心板〖載板之需 求’對於提高高密度晶片封裝之良率，且降低高密度增層ic載板 的製作成本’係為有效之解決方案。 解 為其能對本發明之目的、功效及構造特财找翻確 ’茲舉可實施力併配合圖示說明如後： ’、 【實施方式】 第一圖（A)_二(R)為本發明之一種實心微小導孔載板製造方 法之示意圖。其中，圖三(A)一三(E)為製作已電路圖案化的載板之 示思圖，而圖三(F)-三(K)則揭示了本發明主要的製造方法，即製 作實心微λ!、導孔之倾，含其上之連接層。圖三([〇縣形成另一 增層電路’而圖三(Μ)-三(R)則為在一實心微小導孔上層製作另一 實、微小導孔，以形成疊孔結構之步驟。其中，圖三⑺一三(κ)與 1247363 圖三(Μ)-三(R)之步驟完全相同，並可視需要重複以形成更多層之 載板結構。以下’首先說明本發明的詳細製造方法。 如第二圖（A)-三(e)所示，製作一具有電路圖案的載板。首先， 提供一厚度約為0·1〜〇.8刪的核心基板(Core Lami.nate)301， 並在其上下兩侧各披覆厚度約為3〜12//m的第一金屬層302於基 板301上如圖二(a)所示。基板綱的材質一般選用Bismaieimide Triazine(BT)或其他有機材料‘，甚至為陶瓷材質。而第一金屬層 可為銅(Cu)。接著，以機械鑽孔，貫穿第一金屬層3〇2和基板3〇1， 形成寬度約為1〇〇〜250/zm的核心基板通孔3〇3(c〇re through hole) ’如圖二⑻所示。然後，形成一沉積金屬層（或再電鍍薄 銅）’其厚度約為〇· 5-3//m於第-金屬層上3〇2以及核心絲通 孔303侧壁上形成通孔訊號導通金屬層綱，如圖三⑹所示。該 /儿積金屬層可為化學銅。再施以第—層感光_ 3()5，並以遮罩 (Mask)方《進行影像轉移以形成線路，如圖三⑼所示。最後再施 以-層電鍍銅及姓刻阻劑3〇6(可為鎳、錄/金、金、…等金属）， 如圖三（E)所示。 第—圖(F)一二(κ)為製作實心微小導孔之步驟。首先，施以第 -層感光阻#丨307’並以遮罩(Mask)方式進行影像轉移以形成微小 導孔(Micro Via) 308，如圖王⑺所示。接著，以填孔電鍵方式 !247363 將微小導孔填滿，以形成實心微小導孔(s〇lid Micr〇 Via)3〇9， 如圖王⑹所示。然後’將第-層感光阻劑3〇5及第二層感光阻劑 3〇7剝除，再蝕刻形成核心載板301的導通孔、線路及實心微小導 孔309 ’如圖三〇〇所示。至此，完成核心載板3〇1上之導通孔、 第一層線路及實心微小導孔309。接著，在其上僅施以一增層材料 介電層310(或再施以敏311披覆於介電材料表面），如圖三⑴ 所不。其中銅皮311之需要與否，有賴於所使用之介電層材料。 舉例來說，若所用之介電層3.ί〇材料為有機介電層材料(如非BT 材料的樹脂(Resin)層無玻纖加強材料），則可不加一銅皮3ιι。再 以研磨方式將覆蓋於實心微小導孔3Q9上之增層材料介電層 31〇(或含銅皮311磨去），以露出實心微小導孔_之連^面， 如圖王⑺所示。最後，再施以第二層沉積錄層（或再電錢糊 以形成第-層實心微小導孔3〇9_號導通金屬層312，如圖三⑴ 所示。沉積金屬層可為化學銅。 第二圖⑻-三⑻則為在一實心微小導孔上層製作另一層實 心微小導孔，鄉成疊孔結構之步驟。首先，施料三層感^阻 劑影313像轉移形成線路再電鑛銅314及侧阻劑315，如圖三江、 所示’此步驟係朗三⑼及圖三⑻相同。接著，施以第喝感 光阻劑316 ’並以遮罩(Mask)方式進行影像轉移㈣成微小導曰孔 (Micro Via) 317 ’如圖三⑻所示，此步驟係與圖三(f)相同。接 1247363 著，以填孔電鍍方式將微小導孔填滿，以形成實心微小導孔(Solid Micro Via)318 ’如圖三(N)所示，此步驟係與圖三(G)相同。然後， 將第二層感光阻劑313及第四層感光阻劑316剝除，再蝕刻形成 增層介電層線路及實心微小導孔318，如圖三⑼所示，此步驟係 與圖三(H)相同。至此，完成第二層線路及實心微小導孔318。接 著’在其上再施以一增層材料介電層(或再施以銅皮320披覆 於介電材料表面），如圖三(p)所示，此步驟係與圖三⑴相同。其 中銅皮320之需要與否，有賴^所使用之介電層材料。舉例來說， 若所用之介電層319材料為有機介電層材料(如非BT材料之樹脂 (hin)層無雜加肖機），啊不加—财咖。再以研磨方式 將覆蓋於實心微小導孔318 1之增層材料介電層319(或含銅皮 32〇)磨去，以露出實心微小導孔318之連接面，如圖三⑻所示， =驟係與圖三⑺相同。最後，再施以第三沉積金屬層（或再電 二銅即形成第二層實心微小導孔318與外層線路層的訊號導通 屬声風Γ三⑻所Γ此步驟係與圖三00相同。該沉積金 曰”、，七5。至此’完成增層實心微小導孔（即第二層微小導 層實讀__層、親層的触。重翻 驟，可繼續形成叠孔結構之增層疊孔結構。，—（）步 第四圖⑴-四〇〇為本發明無核心基板叠孔結構之實心微小導 1247363 孔於之製作方法不意圖。如圖⑷所示，無核心載板之製作，係以 -銅皮（3〜12U_1取代基板謝，再施以感光阻劑搬，並以遮 罩(Mask)方式進行影像轉移以形成微小導孔⑽⑽備，如 _(B所示。接著，以填孔電鑛方式將微小導孔填滿，以形成實 心微小導通孔(Solid Micro Via)4()4，如圖四⑹所示。然後，將 感光阻劑402剝除，接著，在其上僅施以一增層材料介電層4〇5(或 再把以銅皮406披覆於介電層材料表面），再以研磨方式將覆蓋 於實心微小導孔404上之增<材料介電層傷（或含銅皮權磨鲁 去）’以路出實心微小導通孔4〇4之連接面，如圖四③)所示。其 中銅皮406之需要與否，有賴於所使用之介電層材料。舉例來說， 右所用之介電層405材料為有機介電層材料(如非BT材料之樹脂 (ReSln)層無玻纖加強材料），則可不加一銅皮娜。另一方面，若 之’丨電層405材料為BT，則無需力口-銅皮406。再施以沉積 屬曰（或再電鍍薄銅）以形成無基板(C〇reiess)實心微小導通孔 4〇4和外層線路層的訊號導通連金屬層407，如圖四®所示。φ a接著’施以第一層感光阻劑侧，並以遮罩(Mask)方式進行 "像轉移卿魏路，再顧—層電賴及侧關獅(可為 X 、金、···等金屬），如圖四（F)所示。施以第二層感光阻 劑410 ’並以遮罩(Mask)方歧行影像轉移以形成微小導孔(Micro )411再以填孔電鍍方式將微小導孔填滿，以形成實心微小 11 1247363 導孔(Solid Mi㈣Via)412，如圖四⑹所示。然後，將第一層感 光阻劑408及第二層感光阻劑4關除，再餘刻形成無核心載板 的導通孔、線路及實心微小導孔412 ’如圖四（η)所示。 第四圖⑺-四(K)則為在-實心微小導孔上層t作另一層實心 微小導孔，以减$孔結構之步驟。首先，在其上再施以一增層 材料介電層413(或可加-層銅皮414)，如圖四⑴所示。其中銅 皮414之需要與否，有賴於所’使用之介電層材料。舉例來說，若 所用之介電層413材料為有機介電層材料(如非βτ材料之樹脂 ⑽咖層無玻纖加強材料），則可不加—銅皮414。再以研磨方式 將覆蓋於實心微小導孔412上之增層材料介電層413(或含銅皮 414磨去）’以露出實心微小導孔412之連接面，如圖四⑺所示。 最後’再施概積金屬層（或再電鑛薄銅）即形成實心導孔412* 外層線路層的訊餅通金屬層415，如_(κ)_。該沉積金屬 層可為化學銅。至此，完成增層實心導小導孔412，亦形成實心微 小導孔與後續增層線路層的連接。 重複第四圖⑻_四(1〇之步驟，可繼續形成疊孔結構之增層a 孔結構。如圖四⑹所示，即施以第—層感光阻劑，並以^ (MaSk)方式進行影像轉移以形成線路，再施以-層電_ 瓣且劑(糊、綠、金、·..糊），此娜圖四⑽ί 12 1247363 同。 以上_露乃為本㈣之和微小導賴其疊孔架構之製 作’載板麟之如防焊_及最終絲[處理⑻㈣ 、1247363 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor carrier and a method of manufacturing the same, and more particularly to a carrier board having high density and high heat dissipation and a core carrier (c〇reless Substrate). Provides high density, high yield manufacturing methods for solid microvias. [Prior Art] Due to the trend of thin and light electronic products and the increasing functions, the number of I/Os of 1C is rapidly increasing, and the relative packaging technology is constantly updated, from early plug-in to surface adhesion (SMT). Ball Array (BGA), most of today's high-end products have used the build-up method to make ic carrier boards, such as FlipChip, MCM-Multi-Chip Module BGA, with heat sink The package density of the Ic carrier (Embedded Thermal Dissipation) and the wire-free carrier (Wire-free) is also constantly increasing. However, such a high-density layered carrier requires the use of a Via Filled Plating structure, and the technical process and structure of the laser-guided micro-via re-plating, which is not only expensive in equipment investment, but also There are many disadvantages in the manufacturing method. The conventional IC carrier structure is generally a two-layer to eight-layer multilayer printed circuit board, the material used is _ or organic material, and the multi-layer structure of the line guide is mechanical drilling or laser drilling micro hole Then, with the key hole guiding method. It is not easy to check the quality of the micro-holes in the laser drill, and the shortcomings such as the slight opening of the guide hole or the 谏ierQ Via Qpen) are not easy to garble with the current planting electrical tester. When the products are sent to the customer, it is difficult to cause a disconnection after being subjected to multiple thermal stresses. When the problem is discovered, it has caused a lot of damage. 1247363 Laser drill second = skill: Compared with (== hole Ci shot hole caused by "plating = ί ΐί! ( ) 'Fig. - (D) shows the electric hole when the gas pick apricot ^ 疋 tiny hole The problems caused by the inner product (4) or the filling of the hole are all due to the sampling test. Therefore, the traditional manufacturing method is flawless (four), ίί本 and 1^reliability of the six density-added IC carrier board. It is an urgent task to develop a new chip package carrier structure and a manufacturing method to provide a solution to the problem. [Summary of the Invention] < Based on the above-mentioned lack of the conventional Lin's provided by the company, a high-density layered 1C carrier structure 'The main feature is the use of Solid Via Via with stacked Via structure. In addition to the traditional core carrier, the present invention can also be implemented on a coreless carrier to meet high density IC carrier. There is a higher demand for heat dissipation and reliability. The present invention further provides a method for fabricating a south density-increasing layer 1C carrier, the main spirit of which is to replace the conventional laser with a high-density carrier plate (Via Filled Plating). Drilling and electroplating technology to provide low cost Ic Based on the above objectives, the present invention provides a multilayer photoreceptor forming a line and a micro-via, and a metal plating column, such as a steel column, is formed by a conventional electroplating etch stripping agent and electroplating to form a solid micro-guide. Sol id Micro Via, 1247363 is further applied with a layered material and a metal connecting layer (which can be copper), and the connection surface of the micro-via is opened by the grinding method to apply a deposited metal (such as chemical copper). It can be connected to the outer layer Xilin. In this way, the metal column can provide the buffering function of the material stress change at high temperature, and can also provide high heat conduction performance. *;, _, at the same time, this method can also provide a thinner carrier board in the future. Production, such as the production of Coreless carrier plates, with a higher density of the stacked structure, and the method of filling and plating, can greatly reduce the thickness of the finished wire. This manufacturing method solves the conventional mine riding micro hole The application is missing, and it can be effective in response to the demand for the carrier board in the future without increasing the yield of the high-density chip package and reducing the manufacturing cost of the high-density layered ic carrier. Solution: It can solve the purpose, function and structure of the invention. It can be implemented and matched with the illustrations as follows: ', [Embodiment] The first picture (A) _ two ( R) is a schematic diagram of a method for manufacturing a solid micro-conductor carrier according to the present invention, wherein FIG. 3(A) and FIG. 3(E) are diagrams for fabricating a circuitized carrier, and FIG. 3(F) - Three (K) reveals the main manufacturing method of the present invention, that is, the solid micro λ!, the tilt of the via hole, and the connection layer thereon. Figure 3 ([〇县形成 another build-up circuit] and Figure 3 (Μ)-three (R) is a step of forming another solid and small via hole in the upper layer of a solid microvia to form a stacked structure. Among them, the steps of Fig. 3 (7) - 13 (κ) and 1247363 Fig. 3 (Μ) - 3 (R) are exactly the same, and can be repeated as needed to form more layers of the carrier structure. Hereinafter, the detailed production method of the present invention will be described first. As shown in the second diagrams (A) to III (e), a carrier having a circuit pattern is fabricated. First, a core substrate (Core Lami.nate) 301 having a thickness of about 0·1 to 〇.8 is provided, and a first metal layer 302 having a thickness of about 3 to 12/m is coated on the upper and lower sides thereof. On the substrate 301 is shown in Figure 2 (a). The material of the substrate is generally selected from Bismaieimide Triazine (BT) or other organic materials, or even ceramic materials. The first metal layer may be copper (Cu). Then, through the first metal layer 3〇2 and the substrate 3〇1, a core substrate through hole 3〇3 (c〇re through hole) having a width of about 1〇〇~250/zm is formed by mechanical drilling. Two (8). Then, a deposited metal layer (or re-plated thin copper) is formed, which has a thickness of about 5·5-3//m, and a through-hole signal is formed on the sidewall of the first metal layer 3〇2 and the core wire via 303. The metal layer is shown in Figure 3 (6). The metal layer can be chemical copper. Then apply the first layer of sensitization _ 3 () 5, and use the mask (Mask) side to perform image transfer to form the line, as shown in Figure 3 (9). Finally, a layer of electroplated copper and a surname 3〇6 (which can be nickel, gold, gold, etc.) can be applied, as shown in Fig. 3(E). Fig. (F) and Fig. 2 (κ) are steps for making a solid microvia. First, a first layer of photosensitive resist #丨307' is applied and image transfer is performed in a mask manner to form a micro via 308, as shown in Fig. 7 (7). Next, fill the tiny via holes with the hole-filling method !247363 to form a solid tiny via hole (s〇lid Micr〇 Via) 3〇9, as shown in Figure (6). Then, the first layer of photoresist 3 〇 5 and the second layer of photoresist 3 〇 7 are stripped, and then the via holes, the lines and the solid microvias 309 of the core carrier 301 are formed to be etched. Show. At this point, the via holes on the core carrier 3〇1, the first layer line, and the solid microvia 309 are completed. Next, only a build-up material dielectric layer 310 is applied thereto (or a sensitive layer 311 is applied over the surface of the dielectric material) as shown in Fig. 3(1). The need for copper 311 depends on the dielectric layer material used. For example, if the dielectric layer used is an organic dielectric material (such as a non-BT material (Resin) layer without a glass fiber reinforced material), then a copper foil 3 ιι is not added. Then, the dielectric layer 31〇 of the build-up material (or the copper-containing skin 311 is covered) covered on the solid micro-via 3Q9 is polished to expose the surface of the solid micro-via, as shown in FIG. . Finally, a second layer of deposited recording layer is applied (or a battery paste is formed to form a first layer of solid microvias 3 〇 9 _ conductive metal layer 312, as shown in Figure 3 (1). The deposited metal layer can be chemical copper The second figure (8)-three (8) is the step of making another layer of solid micro-conducting holes in the upper layer of a solid micro-conducting hole, and the step of forming a stacked hole structure. First, the three layers of resisting agent 313 are transferred to form a line. Electro-mineral copper 314 and side resist agent 315, as shown in Figure Sanjiang, 'this step is the same as Lang San (9) and Figure 3 (8). Then, the first drink of photosensitive resist 316 ' is applied and the image is masked. Transfer (4) into a micro-via (Micro Via) 317 ' As shown in Figure 3 (8), this step is the same as Figure 3 (f). Connected to 12437363, filling the tiny vias with hole-filling to form a solid The micro-via (Solid Micro Via) 318' is shown in Figure 3 (N), this step is the same as Figure 3 (G). Then, the second layer of photoresist 313 and the fourth layer of photoresist 316 are stripped. And etching to form the build-up dielectric layer line and the solid micro-via 318, as shown in Figure 3 (9), this step is the same as Figure 3 (H). Thus, the second layer of circuitry and the solid microvia 318 are completed. Then, a dielectric layer of a build-up material is applied thereto (or a copper foil 320 is applied over the surface of the dielectric material), as shown in FIG. As shown in p), this step is the same as in Figure 3 (1). The need for the copper foil 320 depends on the dielectric layer material used. For example, if the dielectric layer 319 is an organic dielectric layer. Material (such as non-BT material resin (hin) layer without miscellaneous addition machine), do not add - money coffee. Then grind the cover layer of solid layer 318 1 of the layered material dielectric layer 319 (or Bronze 32 〇) is ground to expose the connection surface of the solid micro-via 318, as shown in Figure 3 (8), the sequence is the same as Figure 3 (7). Finally, the third deposited metal layer is applied (or re-powered) The copper forms the second layer of solid micro-via 318 and the outer layer of the signal layer is connected to the sound of the wind (3). This step is the same as that of Figure 30. The deposited gold 曰",, seven. 5. So complete the layer Solid micro-conducting holes (ie, the second layer of micro-conducting layer is actually read __ layer, the contact of the pro-layer. Re-turning, can continue to form a layer of stacked structure Pore structure., -() Step 4 (1) - Four 〇〇 is the solid micro-guide 127393 of the coreless substrate stack structure of the present invention. The method of making the hole is not intended. As shown in Figure (4), the production of the coreless carrier is not shown. , with - copper (3 ~ 12U_1 replaced substrate, and then applied with a photoresist), and image transfer by mask (Mask) to form tiny vias (10) (10), as shown in _ (B. Then, The micro via hole is filled in a hole-filling method to form a solid micro via (Solid Micro Via) 4 () 4, as shown in Fig. 4 (6). Then, the photoresist 402 is stripped, and then, Applying only a layer of dielectric material 4〇5 (or coating the surface of the dielectric layer with copper 406), and then grinding the material over the solid microvia 404. Dielectric layer damage (or copper-containing right to rub) "to connect the solid micro-via 4,4 connection surface, as shown in Figure 4). The need for copper 406 depends on the dielectric layer material used. For example, the material of the dielectric layer 405 used for the right side is an organic dielectric layer material (for example, a resin of a non-BT material (ReSln) layer without a glass fiber reinforced material), and no copper pinna may be added. On the other hand, if the material of the electric layer 405 is BT, the force-copper 406 is not required. Further, a deposition enamel (or re-plated copper) is applied to form a solid via hole 4 〇 4 of the substrate and a signal conducting metal layer 407 of the outer wiring layer, as shown in FIG. φ a then 'apply the first layer of photoresist on the side, and in the form of a mask (Mask), "like transfer of Wei Road, and then - layer of electricity and side lions (can be X, gold, · · · Equivalent metal), as shown in Figure 4 (F). Applying a second layer of photoresist 410' and transferring the image by masking to form a micro via 411, and filling the micro via with fillet plating to form a solid tiny 11 1247363 via hole (Solid Mi (V) Via) 412, as shown in Figure 4 (6). Then, the first layer of photoresist 408 and the second layer of photoresist 4 are turned off, and the via holes, the lines and the solid microvias 412' of the coreless carrier are formed as shown in FIG. 4(n). The fourth figure (7)-four (K) is a step of making another layer of solid micro-via holes in the upper layer of the solid micro-via hole to reduce the structure of the hole. First, a build-up material dielectric layer 413 (or an additive-layer copper bump 414) is applied thereto as shown in Fig. 4 (1). The need for copper 414 depends on the dielectric layer material used. For example, if the dielectric layer 413 material used is an organic dielectric layer material (e.g., a non-βτ material resin (10) coffee layer without a glass fiber reinforced material), the copper skin 414 may not be added. Then, the build-up material dielectric layer 413 (or the copper-containing skin 414 is polished) over the solid micro-via 412 is polished to expose the connection surface of the solid micro-via 412, as shown in Fig. 4 (7). Finally, the metal layer (or remineralized copper) is formed to form a solid via 412* of the outer layer of the layer of the metal layer 415, such as _(κ)_. The deposited metal layer can be chemical copper. At this point, the thickened solid small vias 412 are completed, and the solid microvias are also connected to the subsequent buildup wiring layers. Repeat the fourth figure (8) _ four (1 step, you can continue to form the layered a hole structure of the stacked structure. As shown in Figure 4 (6), the first layer of photoresist is applied, and ^ (MaSk) Perform image transfer to form a line, and then apply a layer of electricity _ lobes and agent (paste, green, gold, ·.. paste), this Natu four (10) ί 12 1247363 the same. Above _ Lu Nai (4) and the small guide The production of Laiqi's stacked-hole structure's such as the welding board _ and the final wire [processing (8) (four),
Finishing)製程，大凡熟悉載板製造技藝之人士均可自行實施， 在此不再說明。 經由以上本發明之一實施‘例與現有之習知技術比冑，本發明 有以下之優點·· 1·以滿足對散&，信賴性有更高需求，之載板。 2·改善雷射鑽微小孔及電鍍填孔的品質問題，提高生產良 率，。 3·減少電射鑽孔機的設備投資，降低高密度增層1C載板 的製作成本。 4·提供無核心載板之製作，可提高載板内層佈線密度。 命因此，本發明之一種實心微小導孔載板製造方法，確能藉所 揭路之技藝，達到所預期之目的與功效，符合發明專利之新穎性， 進步性與產業利用性之要件。 准’以上所揭露之圖示及說明，僅為本發明之較佳實施例而 非為用以限定本發明之實施，大凡熟悉該項技藝之人士其所 13 依本發明之轉，鱗之變 凊專利範圍内。 錦，白應/函盍在以下本案之申 【圖式簡單說明】 第一圖⑷—⑻為習知技術之缺點示意圖 ir圖為本發明之疊孔結構之實心微小導孔之結構示意圖 二圖（A)'三(R)為本發明之纽結構之實讀小導孔之製作方 法示意圖 i 第四圖（A)’（l)為本發明《疊孔結構之實心微小導孔於無核心 基板之製作方法示意圖 【主要元件符號說明】 基板 301 第一金屬層 302 核心基板通孔 303 通孔訊號導通銅層 304 第一層感光阻劑 305 電鐘銅及餘刻阻劑 306 第二層感光阻劑 307 徽小導孔 308 實心微小導孔 309 增層材料介電層 310 銅皮 311 1247363 第一層實心微小導孔和外層線路之訊號導通金屬層312 第三層感光阻劑 313 電鍍銅 314 蝕刻阻劑 315 第四層感光阻劑 316 微小導孔 317 實心微小導孔 318 增層材料介電層 319 1 銅皮 320 第二層實心微小導孔和外層線路之訊號導通金屬層321 銅皮 401 感光阻劑 402 微小導孔 403 實心微小導通孔 404 介電層 405 銅皮 406 第一層實心微小導孔和外層線路之訊號導通金屬屬層406 沉積金屬層及電鍍薄銅407 第一層感光阻劑 408 電鍍銅及蝕刻阻劑 409 第二層感光阻劑 410 15 1247363 微小導孔 411 實心微小導孔 412 介電層 413 銅皮 414 第二層實心微小導孔和外層線路層之訊號訊號導通金屬層415 感光阻劑 416 電鍍銅 417 16Finishing) Processes, which are familiar to those who are familiar with the manufacturing technology of the carrier board, can be implemented by themselves and will not be explained here. The present invention has the following advantages over the prior art of the present invention. The present invention has the following advantages: 1. A carrier board that satisfies the need for higher reliability and reliability. 2. Improve the quality of laser drilling micro holes and plating holes to improve production yield. 3. Reduce the equipment investment of the electro-radiation drilling machine and reduce the production cost of the high-density layered 1C carrier. 4. Provide the production of the coreless carrier board, which can increase the wiring density of the inner layer of the carrier board. Therefore, the method for manufacturing a solid micro-conductor carrier plate of the present invention can achieve the intended purpose and effect by utilizing the technique of uncovering the road, and conforms to the novelty, advancement and industrial utilization requirements of the invention patent. The illustrations and descriptions disclosed above are merely preferred embodiments of the present invention and are not intended to limit the implementation of the present invention, and those skilled in the art will be able to change the scale according to the present invention. Within the scope of the patent. Jin, Bai Ying / 盍 盍 in the following case [simplified description of the schema] The first figure (4) - (8) is a shortcoming of the conventional technology diagram ir diagram is a schematic diagram of the structure of the solid micro-via hole of the stacked structure (A) 'Three (R) is a schematic diagram of the method for making a small read hole of the new structure of the present invention. i The fourth figure (A) '(l) is the solid micro-via of the stacked structure in the core of the present invention. Schematic diagram of manufacturing method of substrate [Major component symbol description] Substrate 301 First metal layer 302 Core substrate via 303 Through-hole signal conduction copper layer 304 First layer photoresist 305 Electric clock copper and residual resist 306 Second layer photosensitive Resistor 307 small via 308 solid microvia 309 build-up dielectric layer 310 copper 311 1247363 first layer of solid microvia and outer layer signal conduction metal layer 312 third layer photoresist 313 electroplated copper 314 Etch Resist 315 Fourth Layer Resistant 316 Tiny Via 317 Solid Tin Via 318 Additive Material Dielectric Layer 319 1 Copper 320 Second Layer Solid Small Via and Outer Line Signal Conductive Metal Layer 321 Copper 401 Photoresist 402 Small via 403 Solid micro via 404 Dielectric layer 405 Copper 406 First layer of solid microvia and outer layer signal conduction metal layer 406 Deposited metal layer and plated thin copper 407 First layer sensitization Resistor 408 Electroplated copper and etch resist 409 Second layer photoresist 410 15 1247363 Tiny via 411 Solid micro via 412 Dielectric layer 413 Copper 414 Second layer solid microvia and outer layer layer signal signal conduction Metal layer 415 photosensitive resist 416 electroplated copper 417 16