CN104093272A - Improved semiconductor packaging substrate structure and manufacturing method thereof - Google Patents
Improved semiconductor packaging substrate structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN104093272A CN104093272A CN201410361659.XA CN201410361659A CN104093272A CN 104093272 A CN104093272 A CN 104093272A CN 201410361659 A CN201410361659 A CN 201410361659A CN 104093272 A CN104093272 A CN 104093272A
- Authority
- CN
- China
- Prior art keywords
- layer
- increasing
- pad
- metal column
- photosensitive resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides an improved semiconductor packaging substrate structure. According to the improved semiconductor packaging substrate structure, the distance between substrate bonding pads is effectively shortened, and meanwhile the reliability of the substrate bonding pads is guaranteed. The improved semiconductor packaging substrate structure includes a core plate and is characterized in that the two sides of the core plate are provided with layer-adding layers; the layer-adding layers are connected with the core plate through blind holes; the bottoms of the blind holes are connected with bonding pads of the layer-adding layers on the lower surface of the core plate; the layer-adding layers on the upper surface and the lower surface of the core plate or the interiors of the layer-adding layers are provided with conducting circuits; the core plate is provided with via holes, the conducting circuits on the upper surface and the lower surface of the core plate are connected through the via holes, and hole plugging materials are arranged in the via holes; metal columns are arranged in the layer-adding layer on the upper surface of the core plate and arranged in the corresponding layer-adding layer; the metal columns are connected with an inner conducting layer; the peripheries of the metal columns are provided with layer-adding material for protection; the layer-adding layer on the lower surface of the core plate is provided with the bonding pads which are exposed out of the surface of a substrate, and the peripheries of the bonding pads are covered with solder resist ink. Meanwhile, the invention provides a manufacturing method of the improved semiconductor packaging substrate structure.
Description
Technical field
The technical field that the present invention relates to microelectronic packaging process, is specifically related to a kind of improved conductor package substrate construction and preparation method thereof.
Background technology
Along with the development of semiconductor technology, Moore's Law approaches the edge losing efficacy.In industrial chain, the difficulty of IC design, wafer manufacture, packaging and testing links continues to increase.Constantly diminishing of chip bonding pad spacing, because the development of base plate for packaging back-off solder pad space length cannot be caught up with the paces that chip bonding pad spacing changes.The solder pad space length that how to dwindle base plate for packaging becomes problem demanding prompt solution.
In existing base plate for packaging manufacturing process, all use and increase layer (Build-up) technique.After having made outermost layer circuit, print welding resistance ink (Solder Mask) by technique formation pads such as exposure, developments, the making of welding resistance ink technique in common process, because poor the brought substrate pads spacing of the low and physical and chemical performance of welding resistance ink material optical resolution is large and the problem such as poor reliability.
Summary of the invention
For the problems referred to above, the invention provides a kind of improved conductor package substrate construction, when effectively having dwindled substrate pads spacing, guaranteed the reliability of substrate pads, the present invention provides a kind of improved conductor package substrate construction simultaneously
Its technical scheme is as follows:
A kind of improved conductor package substrate construction, it comprises central layer, central layer both sides are provided with increasing layer by layer, described increasing is connected by blind hole layer by layer with between central layer, blind hole bottom is connected with the pad that line face increases layer by layer, described in described central layer upper and lower surface, increase to go up layer by layer or increase inside layer by layer and be provided with conducting wire, on described central layer, be provided with via, between the described conducting wire of described central layer upper and lower surface, by described via, connect, in described via, be provided with consent material, above be provided with metal column in described increasing layer by layer, described metal column is arranged in described increasing layer by layer, described metal column is connected with inner-layer conducting layer, described metal column periphery is provided with and increases layer protective material, below be provided with pad in described increasing layer by layer, described pad exposes substrate surface, described pad periphery covers welding resistance ink.
It is further characterized in that: upper and lower described increasing includes layer by layer multilayer and increases layer by layer, between described increasing layer by layer, by blind hole, connect, in described increasing layer by layer, be respectively arranged with conducting wire, in increasing layer by layer above described in outermost layer, be provided with metal column, in increasing layer by layer below described in outermost layer, be provided with pad, described pad exposes substrate surface, and described pad periphery covers welding resistance ink.
A manufacture method for improved conductor package substrate construction, it comprises the following steps:
(1), the making of central layer, double face copper forms via, adopts the process deposits of via metal to make via connect the metal of copper-clad plate upper and lower surface, in via inside, fills consent material, by circuit, form technique, at copper-clad plate tow sides, form conducting wire;
(2), increase layer by layer and make, it comprises: (a), in central layer positive back side laminating, increase layer material, form blind hole, blind hole bottom exposed pad increasing on layer material; (b), increasing depositing conducting layer on layer material, form conducting wire, on conductive layer, apply photosensitive resin; (c), remove photosensitive resin and unnecessary conductive layer, complete increasing and make layer by layer;
(3), form first window, apply again photosensitive resin increasing the positive back side layer by layer, the mode by exposure imaging forms first window on positive photosensitive resin, first window exposes positive needed conducting wire and pad;
(4), form metal column, use electroplating technique first plated conductive material in window to form metal column, the height of metal column, higher than the height of photosensitive resin, is not removed photosensitive resin and Seed Layer;
(5), increase layer material increasing positive laminating layer by layer, backside coating welding resistance ink, increases layer material metal column is covered;
(6), on the welding resistance ink of the base plate for packaging back side, form Second Window, form the second pad, the pad exposing is carried out to surface anticorrosion processing, base plate for packaging front attenuate, removes surface part and increases layer material, exposes copper post.
It is further characterized in that, the technique of repeating step (2) and step (3) forms multilayer and increases layer by layer, between increasing layer by layer, by blind hole, connects, and between increasing layer by layer, by blind hole, connects, and in increasing layer by layer, is respectively arranged with conducting wire.
In step (1), double face copper forms via by machine drilling or laser drill, via metal metallization processes comprises the black hole of sputter, electroless copper plating, shadow, electro-coppering or printing conductive medium technique, consent material comprises resin or conducting medium, and circuit forms technique and comprises that coating photosensitive resin, exposure, development, etching, laser scribing groove form conducting wire technique;
In step (2), laminating type comprises hot pressing, roll extrusion, vacuum pressing-combining, quick pressing, printing, spin coating, spraying coating process, increase layer material and comprise that prepreg, ink, polyimides, pure glue, gum Copper Foil, ABF material or other can be for the dielectric materials of printed circuit board (PCB), use machine drilling or laser drill mode to form blind hole increasing on layer material;
Adopt half additive process to form conducting wire;
In step (3), in the flow process of outermost layer half additive process, remove after photosensitive resin, retain conductive layer, the mode by exposure imaging forms window on positive photosensitive resin;
In step (4), use electroplating technique plated conductive material in window to form metal column, copper column section can be circular, also can be square, pentagon, hexagon, octagon and the figure that can form by photoetching development technique arbitrarily, electric conducting material comprises Cu, Ag, Au, Sn, Al material or alloy material.
In step (5), the processing mode that increases layer material and welding resistance ink 114 comprises hot pressing, roll extrusion, vacuum pressing-combining, quick pressing, printing, spin coating, spraying coating process, bi-material can be fitted simultaneously and also can separately be fitted, increase layer material and comprise that prepreg, ink, polyimides, pure glue, gum Copper Foil, ABF material (Ajinomoto Build-up Film) or other can be for the dielectric materials of printed circuit board (PCB), increase top layer by layer and be no more than 10 microns to the distance at metal column top;
In step (6), the mode by exposure imaging forms Second Window on the welding resistance ink of the base plate for packaging back side, uses polish-brush, grinding, mechanical polishing, sandblast, CMP technique to expose metal column increasing layer material surface.
It is above-mentioned that employing the present invention is
structurein; because central layer both sides are provided with increasing layer by layer; increase and by blind hole, be connected layer by layer with between central layer; central layer upper and lower surface is provided with conducting wire on increasing layer by layer; on described central layer, be provided with via; between the conducting wire of central layer upper and lower surface, by via, connect; upper and lower increasing layer by layer surface is provided with pad; pad exposes substrate surface; pad is arranged in described increasing layer by layer; pad periphery is provided with and increases layer material protection, has guaranteed the reliability of substrate pads when effectively having dwindled substrate pads spacing.
Accompanying drawing explanation
Fig. 1 is the improved conductor package substrate construction schematic diagram of the present invention;
Fig. 2 is the making schematic diagram of central layer;
Fig. 3 makes schematic diagram layer by layer for increasing;
Fig. 4 makes schematic diagram layer by layer for increasing;
Fig. 5 is for forming first window schematic diagram;
Fig. 6 is for forming metal column schematic diagram;
Fig. 7 increases layer material, backside coating welding resistance ink schematic diagram for increasing positive laminating layer by layer;
Fig. 8 is for forming Second Window, and removal part increases layer material surface and exposes copper post schematic diagram;
Fig. 9 is that schematic diagram is made in multilayer increasing layer by layer;
Figure 10 is the improved conductor package substrate construction sandwich construction of the present invention schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, invention is described in detail, but present embodiment is not limited to the present invention, the conversion in the structure that those of ordinary skill in the art makes according to present embodiment, method or function, is all included in protection scope of the present invention.
See Fig. 1, a kind of improved conductor package substrate construction, it comprises central layer (Core Layer) 101, central layer 101 both sides are provided with increasing (Build-up Layer) 102 layer by layer, increase layer by layer and by blind hole (Blind Via) 105, be connected between (Build-up Layer) 102 and central layer 101, blind hole 105 bottoms are connected with the pad 109 that line face increases layer by layer, in blind hole 105, be provided with consent material, central layer 101 upper and lower surfaces increasings are provided with conducting wire 103 on (Build-up Layer) 102 layer by layer, conducting wire can be arranged in increasing also can be embedded into increasing inside layer by layer in surface layer by layer, on central layer 101, be provided with via (Through Hole) 104, 103 of the conducting wires of central layer 101 upper and lower surfaces connect by via (Through Hole) 104, in via 104, be provided with consent material, upper and lower increasing layer by layer (Build-up Layer) 102 surfaces is provided with pad 109, pad 109 exposes substrate surface, pad 109 is arranged on increasing layer by layer in (Build-up Layer) 102, pad periphery is provided with and increases layer protective material.Increase above layer by layer and to be provided with metal column 113 on 102; top and bottom increase layer by layer in 102 and are provided with metal column; metal column 113 connecting conductive layers 110 or pad 109; metal column 113 peripheries are provided with and increase layer protective material; form skin and increase 102a layer by layer; increase and in (Build-up Layer) 102, be provided with pad 109 layer by layer below, pad reveals 109 and goes out substrate surface, and pad 109 peripheries cover welding resistance ink 114.
Increase up and down (Build-up Layer) 102 layer by layer and can comprise one deck, also can include multilayer increases layer by layer, between increasing layer by layer, by blind hole (Blind Via) 105, connect, increase and in (Build-up Layer) 102, be respectively arranged with conducting wire 103 layer by layer, top and bottom outermost layers is provided with metal column in increasing layer by layer, by the consent material in blind hole (Blind Via) 105, realized being connected of metal column 113 and central layer 101.
In the present embodiment; for convenience; metal column 113 is arranged on and increases above layer by layer on (Build-up Layer) 102; pad 109 is arranged on and increases below layer by layer on (Build-up Layer); certainly pad 109 also can be arranged on and increase above layer by layer on (Build-up Layer) 102; below metal column 113 also can be arranged on, increasing (Build-up Layer) layer by layer above, is all the protection range of invention.
A manufacture method for improved conductor package substrate construction, it comprises the following steps:
See Fig. 2, the making of (1), central layer, double face copper forms via, adopt the process deposits of via metal to make via connect the metal of copper-clad plate upper and lower surface, at the inner consent material of filling of via, by circuit, form technique, at copper-clad plate tow sides, form conducting wire; The double face copper 106 of fixed dimension forms via 104 by machine drilling or laser drill.The process deposits of via metal makes via 104 can connect the metal of copper-clad plate upper and lower surface.Via metal metallization processes comprises the techniques such as the black hole of sputter (Black Hole), electroless copper plating, shadow (Black Shadow), electro-coppering or printing conductive medium.At the inner consent material 107 of filling of via, consent material comprises resin or conducting medium.By circuit, form technique, at copper-clad plate tow sides, form conducting wire 103.Circuit forms technique and comprises techniques such as applying photosensitive resin (photosensitive resin is included in conducting wire, not shown in FIG.), exposure, development, etching.Central layer 101 can be two layers of wiring structure, can be also Miltilayer wiring structure.
See Fig. 3, Fig. 4, (2), increase layer by layer and make, it comprises: (a), in central layer positive back side laminating, increase layer material, form blind hole, blind hole bottom exposed pad increasing on layer material; (b), increasing depositing conducting layer on layer material, on conductive layer, form conducting wire, conducting wire is included in conductive layer and applies photosensitive resin technique (photosensitive resin is included in conducting wire, not shown in FIG.); (c), remove photosensitive resin and unnecessary conductive layer, complete increasing and make layer by layer.
In central layer 101 positive back side laminating, increase layer material 108.Laminating type comprises the techniques such as hot pressing, roll extrusion, vacuum pressing-combining, quick pressing, printing, spin coating, spraying.Increase layer material and comprise that prepreg, ink, polyimides, pure glue, gum Copper Foil, ABF material (Ajinomoto Build-up Film) or other can be for the dielectric materials of printed circuit board (PCB).Use the modes such as machine drilling or laser drill to form blind hole 105, blind hole 105 bottom exposed pads 109 on increasing layer material 108.
Use half additive process (SAP, Semi-Additive Process), form conducting wire 103 increasing on layer material 108, so also formed and increased layer by layer 102.First half additive process deposits one deck conductive layer 110 on increasing layer material 108, (photosensitive resin is included in conducting wire on conductive layer 110, to apply photosensitive resin, not shown in FIG.), by using the technique of exposure, development, electroplated metal layer to form conducting wire 103.Remove photosensitive resin 111 and unnecessary conductive layer 110, increase layer by layer 102 just make complete.
See Fig. 5, (3), form first window, apply photosensitive resin again increasing the positive back side layer by layer, and the mode by exposure imaging forms first window on the photosensitive resin at the positive back side, and first window exposes positive needed conducting wire and pad.
In the flow process of outermost layer half additive process, remove after photosensitive resin, retain conductive layer 110, in increasing, apply again photosensitive resin 111 in the 102 positive back sides layer by layer, mode by exposure imaging forms first window 112 on positive photosensitive resin, and first window 112 exposes positive needed conducting wire 103 and pad 109.
See Fig. 5, Fig. 6, (4), formation metal column, used electroplating technique first plated conductive material in window to form metal column, and the height of metal column, higher than the height of photosensitive resin, is not removed photosensitive resin and Seed Layer, and Seed Layer is attached to increasing and goes up layer by layer.
Use electroplating technique plated conductive material in window 112 to form metal column 113, the height of metal column 113 is higher than the height of photosensitive resin 111, copper column section can be circular, also can be the figure that square, pentagon, hexagon, octagon etc. can form by photoetching development technique arbitrarily.Electric conducting material comprises material or the alloy materials such as Cu, Ag, Au, Sn, Al.Remove photosensitive resin and Seed Layer.
See Fig. 7, (5), increase layer material increasing positive laminating layer by layer, backside coating welding resistance ink, increases layer material metal column is covered.
Increasing 102 positive laminating increasing layer materials 108 layer by layer, backside coating welding resistance ink 114.The processing mode that increases layer material and welding resistance ink 114 comprises the techniques such as hot pressing, roll extrusion, vacuum pressing-combining, quick pressing, printing, spin coating, spraying, and bi-material can be fitted simultaneously and also can separately be fitted.Increase layer material and comprise that prepreg, ink, polyimides, pure glue, gum Copper Foil, ABF material (Ajinomoto Build-up Film) or other can be for the dielectric materials of printed circuit board (PCB).Increasing layer material 108 covers copper post.Increase the distance of top Dao Tong column top layer by layer and be no more than 10 microns.
See Fig. 8, (6), on the welding resistance ink of the base plate for packaging back side, form Second Window, form the second pad, and the pad exposing is carried out to surface anticorrosion processing, remove part and increase layer material surface and expose copper post.
Mode by exposure imaging forms Second Window on base plate for packaging back side welding resistance ink 114.Use the techniques such as polish-brush, grinding, mechanical polishing, sandblast, CMP to expose copper post 113 on increasing layer material 108 surfaces.The pad 109 exposing is carried out to surface anticorrosion processing.
See Fig. 9, can repeating step (2) and the technique of step (3), form multilayer and increase layer by layer 102, by blind hole, connect between increasing layer by layer, be respectively arranged with conducting wire in increasing layer by layer.
In the manufacture method of the above-mentioned improved conductor package substrate construction that employing the present invention is, when effectively having dwindled substrate pads spacing, guaranteed the reliability of substrate pads.
Claims (10)
1. an improved conductor package substrate construction, it comprises draws together central layer, it is characterized in that: described central layer both sides are provided with increasing layer by layer, described increasing is connected by blind hole layer by layer with between central layer, blind hole bottom is connected with the pad that line face increases layer by layer, described in described central layer upper and lower surface, increase to go up layer by layer or increase inside layer by layer and be provided with conducting wire, on described central layer, be provided with via, between the described conducting wire of described central layer upper and lower surface, by described via, connect, in described via, be provided with consent material, above be provided with metal column in described increasing layer by layer, described metal column is arranged in described increasing layer by layer, described metal column is connected with inner-layer conducting layer, described metal column periphery is provided with and increases layer protective material, below be provided with pad in described increasing layer by layer, described pad exposes substrate surface, described pad periphery covers welding resistance ink.
2. a kind of improved conductor package substrate construction according to claim 1, it is characterized in that: upper and lower described increasing includes layer by layer multilayer and increases layer by layer, between described increasing layer by layer, by blind hole, connect, in described increasing layer by layer, be respectively arranged with conducting wire, in increasing layer by layer above described in outermost layer, be provided with metal column, in increasing layer by layer below described in outermost layer, be provided with pad, described pad exposes substrate surface, and described pad periphery covers welding resistance ink.
3. a manufacture method for improved conductor package substrate construction, is characterized in that: it comprises the following steps:
(1), the making of central layer, double face copper forms via, adopts the process deposits of via metal to make via connect the metal of copper-clad plate upper and lower surface, in via inside, fills consent material, by circuit, form technique, at copper-clad plate tow sides, form conducting wire;
(2), increase layer by layer and make, it comprises: (a), in central layer positive back side laminating, increase layer material, form blind hole, blind hole bottom exposed pad increasing on layer material; (b), increasing depositing conducting layer on layer material, form conducting wire, on conductive layer, apply photosensitive resin; (c), remove photosensitive resin and unnecessary conductive layer, complete increasing and make layer by layer;
(3), form first window, apply again photosensitive resin increasing the positive back side layer by layer, the mode by exposure imaging forms first window on positive photosensitive resin, first window exposes positive needed conducting wire and pad;
(4), form metal column, use electroplating technique first plated conductive material in window to form metal column, the height of metal column, higher than the height of photosensitive resin, is not removed photosensitive resin and Seed Layer;
(5), increase layer material increasing positive back side laminating layer by layer, backside coating welding resistance ink, increases layer material metal column is covered;
(6), on the welding resistance ink of the base plate for packaging back side, form Second Window, form the second pad, the pad exposing is carried out to surface anticorrosion processing, base plate for packaging front attenuate, removes surface part and increases layer material, exposes copper post.
4. the manufacture method of a kind of improved conductor package substrate construction according to claim 3, it is characterized in that: the technique of repeating step (2) and step (3), form multilayer and increase layer by layer, between increasing layer by layer, by blind hole, connect, in increasing layer by layer, be respectively arranged with conducting wire.
5. the manufacture method of a kind of improved conductor package substrate construction according to claim 3, it is characterized in that: in step (1), double face copper forms via by machine drilling or laser drill, via metal metallization processes comprises the black hole of sputter, electroless copper plating, shadow, electro-coppering or printing conductive medium technique, consent material comprises resin or conducting medium, and circuit forms technique and comprises that coating photosensitive resin, exposure, development, etching, laser scribing groove form conducting wire technique.
6. the manufacture method of a kind of improved conductor package substrate construction according to claim 3, it is characterized in that: in step (2), laminating type comprises hot pressing, roll extrusion, vacuum pressing-combining, quick pressing, printing, spin coating, spraying coating process, increase layer material and comprise that prepreg, ink, polyimides, pure glue, gum Copper Foil, ABF material or other can be for the dielectric materials of printed circuit board (PCB), use machine drilling or laser drill mode to form blind hole increasing on layer material;
Adopt half additive process to form conducting wire.
7. the manufacture method of a kind of improved conductor package substrate construction according to claim 3, it is characterized in that: in step (3), in the flow process of outermost layer half additive process, remove after photosensitive resin, retain conductive layer, the mode by exposure imaging forms window on positive photosensitive resin.
8. the manufacture method of a kind of improved conductor package substrate construction according to claim 3, it is characterized in that: in step (4), use electroplating technique plated conductive material in window to form metal column, copper column section can be circular, also can be square, pentagon, hexagon, octagon and the figure that can form by photoetching development technique arbitrarily, electric conducting material comprises Cu, Ag, Au, Sn, Al material or alloy material.
9. the manufacture method of a kind of improved conductor package substrate construction according to claim 3, it is characterized in that: in step (5), the processing mode that increases layer material and welding resistance ink 114 comprises hot pressing, roll extrusion, vacuum pressing-combining, quick pressing, printing, spin coating, spraying coating process, bi-material can be fitted simultaneously and also can separately be fitted, increase layer material and comprise prepreg, ink, polyimides, pure glue, gum Copper Foil, ABF material (Ajinomoto Build-up Film) or other can be for the dielectric materials of printed circuit board (PCB), increase top layer by layer and be no more than 10 microns to the distance at metal column top.
10. the manufacture method of a kind of improved conductor package substrate construction according to claim 3, it is characterized in that: in step (6), mode by exposure imaging forms Second Window on the welding resistance ink of the base plate for packaging back side, uses polish-brush, grinding, mechanical polishing, sandblast, CMP technique to expose metal column on increasing layer material surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410361659.XA CN104093272B (en) | 2014-07-25 | 2014-07-25 | A kind of conductor package substrate construction and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410361659.XA CN104093272B (en) | 2014-07-25 | 2014-07-25 | A kind of conductor package substrate construction and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104093272A true CN104093272A (en) | 2014-10-08 |
| CN104093272B CN104093272B (en) | 2018-01-16 |
Family
ID=51640933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410361659.XA Active CN104093272B (en) | 2014-07-25 | 2014-07-25 | A kind of conductor package substrate construction and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104093272B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105517374A (en) * | 2015-12-17 | 2016-04-20 | 深圳崇达多层线路板有限公司 | Method for making HDI board with thin core board |
| CN107624002A (en) * | 2017-10-12 | 2018-01-23 | 安捷利（番禺）电子实业有限公司 | The FPC and its pad pasting preparation technology of a kind of circuit flush type |
| CN114900962A (en) * | 2022-04-18 | 2022-08-12 | 广州广芯封装基板有限公司 | Printed circuit board and layer adding method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001937A1 (en) * | 2000-06-30 | 2002-01-03 | Nec Corporation | Semiconductor package board using a metal base |
| EP1432293A1 (en) * | 2001-09-28 | 2004-06-23 | Ibiden Co., Ltd. | Printed wiring board and production method for printed wiring board |
| CN1957649A (en) * | 2004-05-27 | 2007-05-02 | 揖斐电株式会社 | Multilayer printed wiring board |
| TW200838387A (en) * | 2007-03-02 | 2008-09-16 | Phoenix Prec Technology Corp | Warp-proof circuit board structure |
-
2014
- 2014-07-25 CN CN201410361659.XA patent/CN104093272B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001937A1 (en) * | 2000-06-30 | 2002-01-03 | Nec Corporation | Semiconductor package board using a metal base |
| EP1432293A1 (en) * | 2001-09-28 | 2004-06-23 | Ibiden Co., Ltd. | Printed wiring board and production method for printed wiring board |
| CN1957649A (en) * | 2004-05-27 | 2007-05-02 | 揖斐电株式会社 | Multilayer printed wiring board |
| TW200838387A (en) * | 2007-03-02 | 2008-09-16 | Phoenix Prec Technology Corp | Warp-proof circuit board structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105517374A (en) * | 2015-12-17 | 2016-04-20 | 深圳崇达多层线路板有限公司 | Method for making HDI board with thin core board |
| CN105517374B (en) * | 2015-12-17 | 2019-02-05 | 深圳崇达多层线路板有限公司 | A kind of production method of thin core plate HDI plate |
| CN107624002A (en) * | 2017-10-12 | 2018-01-23 | 安捷利（番禺）电子实业有限公司 | The FPC and its pad pasting preparation technology of a kind of circuit flush type |
| CN114900962A (en) * | 2022-04-18 | 2022-08-12 | 广州广芯封装基板有限公司 | Printed circuit board and layer adding method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104093272B (en) | 2018-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8383950B1 (en) | Metal etch stop fabrication method and structure | |
| US20150357277A1 (en) | Wiring substrate | |
| JP5048005B2 (en) | Printed circuit board having metal bumps and manufacturing method thereof | |
| JP2010135721A (en) | Printed circuit board comprising metal bump and method of manufacturing the same | |
| US9159614B2 (en) | Packaging substrate and method for manufacturing same | |
| US20090095508A1 (en) | Printed circuit board and method for manufacturing the same | |
| TW201427522A (en) | Package circuit board, method for manufacturing same, and package structure | |
| TWI492690B (en) | Method for manufacturing circuit board | |
| TWI511250B (en) | Ic substrate,semiconductor device with ic substrate and manufucturing thereof | |
| KR20130057314A (en) | Printed circuit board and method of manufacturing a printed circuit board | |
| CN104093272A (en) | Improved semiconductor packaging substrate structure and manufacturing method thereof | |
| TWI553787B (en) | Ic substrate,semiconductor device with ic substrate and manufucturing method thereof | |
| CN104091790A (en) | Semiconductor packaging substrate structure and manufacturing method of semiconductor packaging substrate structure | |
| KR101669534B1 (en) | Circuit board with bumps and method of manufacturing the same | |
| JP2010135860A (en) | Method of manufacturing printed circuit board | |
| KR20150065029A (en) | Printed circuit board, manufacturing method thereof and semiconductor package | |
| KR100908986B1 (en) | Coreless Package Substrate and Manufacturing Method | |
| TWI581697B (en) | Method for manufacturing heat dissipation structure of ceramic substrate | |
| JP7007882B2 (en) | Wiring board and its manufacturing method | |
| CN104105340A (en) | Package substrate via hole structure and manufacture method | |
| KR100925669B1 (en) | Method of fabricating a solder on pad for coreless package substrate technology | |
| TW201431454A (en) | Circuit board and method for manufacturing same | |
| KR102141102B1 (en) | Method for manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same | |
| KR100547349B1 (en) | Semiconductor packaging substrate and manufacturing method thereof | |
| KR101313155B1 (en) | Plating Method for PCB and Method for Manufacturing Flexible PCB Using the Same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |