KR100925669B1 - Method of fabricating a solder on pad for coreless package substrate technology - Google Patents

Method of fabricating a solder on pad for coreless package substrate technology

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Publication number
KR100925669B1
KR100925669B1 KR1020070138735A KR20070138735A KR100925669B1 KR 100925669 B1 KR100925669 B1 KR 100925669B1 KR 1020070138735 A KR1020070138735 A KR 1020070138735A KR 20070138735 A KR20070138735 A KR 20070138735A KR 100925669 B1 KR100925669 B1 KR 100925669B1
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South Korea
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solder
copper plating
plating
copper
pad
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KR1020070138735A
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Korean (ko)
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KR20090070649A (en
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조원진
윤상근
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대덕전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices

Abstract

본 발명은 캐리어의 동박에 드라이 필름의 패턴에 따라 노출된 동박을 해프 에칭하여 요철 형태를 형성하고, 솔더 도금으로 요철 내부에 솔더를 형성하고, 솔더 위에 동도금으로 요철을 충진하고 적층 빌드업 및 홀가공을 통해 상기 솔더 위에 동도금된 패드를 형성하고 캐리어를 박리함으로써 솔더 패드는 동도금으로 형성하고 솔더 역시 도금 방식으로 형성함으로써 편차를 최소화하고 솔더 온 패드 사이에는 절연층으로 구성된 댐이 존재하므로 플립 칩 실장 시에 솔더가 퍼져서 서로 단락되는 것이 원천 차단된다. The present invention forms a concave-convex shape by half-etching the copper foil exposed to the copper foil of the carrier according to the pattern of the dry film, to form a solder inside the concave-convex by solder plating, filling the concave-convex with copper plating on the solder and laminated build-up and hole By forming a copper-plated pad on the solder and peeling the carrier through the processing, the solder pad is formed of copper plating and the solder is also formed by plating method to minimize the deviation, and there is a dam composed of an insulating layer between the solder-on pads. Solder spreads and shorts from each other are blocked at the source.

초박형 기판, 패키지 기판, 코어리스, 플립 칩, 솔더, SIP, SOP. Ultra-thin substrates, package substrates, coreless, flip chip, solder, SIP, SOP.

Description

코어리스 패키지 기판 제조 공법에 의한 솔더 온 패드 제조 방법{METHOD OF FABRICATING A SOLDER ON PAD FOR CORELESS PACKAGE SUBSTRATE TECHNOLOGY}METHOD OF FABRICATING A SOLDER ON PAD FOR CORELESS PACKAGE SUBSTRATE TECHNOLOGY}

본 발명은 반도체 다이를 플립 칩(flip chip) 방식으로 패키지 기판에 실장할 때에 필요한 솔더 온 패드(SoP; Solder on Pad; 이하 "솔더 온 패드"라 칭하기로 한다)를 형성하는 방법에 관한 것으로, 특히 150 ㎛ 피치 급 이하의 코어리스 패키지 기판의 솔더 온 패드(SoP)를 구현하는 방법에 관한 것이다.The present invention relates to a method for forming a solder on pad (SoP; referred to as "solder on pad") required for mounting a semiconductor die on a package substrate in a flip chip method, In particular, the present invention relates to a method of implementing a solder on pad (SoP) of a coreless package substrate having a pitch of 150 μm or less.

최근 들어, 전자제품이 소형화 되어감에 따라 반도체 칩을 웨이퍼 레벨 또는 칩 레벨에서 패키지 기판에 직접 실장하는 기술이 통용되고 있다. 반도체 칩("반도체 다이"라고 칭하기도 함)을 패키지 기판에 탑재하기 위해서는, 반도체 다이의 리드를 솔더를 사이에 두고 직접 플립 칩 방식으로 기판의 패드에 접속하게 된다. 따라서, 플립칩 실장 기술에 있어서 반도체 다이의 리드선 간격이 미세화되는 추세를 맞추기 위해서는 플립 칩을 위한 솔더 온 패드(SoP) 사이의 피치 간격도 점점 좁아져야 한다. In recent years, as electronic products become smaller, technologies for directly mounting a semiconductor chip on a package substrate at a wafer level or a chip level are commonly used. In order to mount a semiconductor chip (also referred to as a "semiconductor die") on a package substrate, the lead of the semiconductor die is directly connected to the pad of the substrate by a flip chip method with solder interposed therebetween. Therefore, in order to meet the trend of miniaturization of the lead wire spacing of the semiconductor die in the flip chip mounting technology, the pitch spacing between the solder on pads (SoP) for the flip chip should be gradually narrowed.

도1a 내지 도1h는 종래 기술에 따라 기판에 솔더를 형성하는 과정을 나타낸 도면이다. 도1a를 참조하면, 절연층 수지와 동박 회로를 다층 적층하여 형성한 기판(100)이 도시되어 있으며, 관통홀(10) 및 비아홀(20)이 도시되어 있다. 이어서, 기판의 일 표면에 메탈 스퍼터(도1b)을 진행하여 스퍼터 메탈층(25)을 형성하고, 드라이 필름(30)을 도포하고 노광 현상 공정을 진행하여 드라이 필름을 패턴 형성한다(도1c). 이어서, 도금 공정을 진행하여 범프 도금(40)을 노출된 동박 위에 형성한다(도1d).1A to 1H illustrate a process of forming solder on a substrate according to the related art. Referring to FIG. 1A, a substrate 100 formed by multilayering an insulating layer resin and a copper foil circuit is illustrated, and a through hole 10 and a via hole 20 are illustrated. Subsequently, a metal sputter (FIG. 1B) is formed on one surface of the substrate to form a sputter metal layer 25, a dry film 30 is applied, and an exposure developing process is performed to form a dry film (FIG. 1C). . Next, a plating process is performed to form bump plating 40 on the exposed copper foil (FIG. 1D).

그리고 나면, 드라이 필름(30)을 박리하고(도1e) Ni/Au 도금(45)과 솔더 도금(50)을 진행한다(도1f). 이어서, 스퍼터 메탈층(25)을 제거한다(도1g). 그리고 나면, 범프 도금 위에 Ni/Au 도금(45)과 솔더 도금(50)이 피복된 솔더(110)가 형성되는데, 리플로우 프로세스를 통해 도1h에서와 같이 솔더를 동그랗게 볼 형태로 가공한다.Then, the dry film 30 is peeled off (FIG. 1E) and Ni / Au plating 45 and solder plating 50 are performed (FIG. 1F). Next, the sputter metal layer 25 is removed (Fig. 1G). Then, a solder 110 coated with Ni / Au plating 45 and solder plating 50 is formed on the bump plating, and the solder is processed into a round ball shape as shown in FIG. 1H through a reflow process.

그런데, 도1a 내지 도1h에 도시한 종래 기술의 경우, 도전층 형성을 위해서 고비용의 메탈 스퍼터 프로세스(도1b)가 필요한 단점이 있고, 솔더(110)와 솔더(110) 사이에 댐이 없으므로 플립칩 접합 시에 솔더 온 패드가 서로 전기적으로 단락될 위험이 상존하고 있으며, 도1f의 솔더 도금 과정에서 도금의 편차 관리가 용이하지 않은 기술적 한계가 있다. 또한, 종래 기술은 솔더 리플로우(reflow) 과정에서 편차 관리를 하는데 어려움이 있다. However, the prior art shown in FIGS. 1A to 1H has a disadvantage in that an expensive metal sputter process (FIG. 1B) is required to form a conductive layer, and since there is no dam between the solder 110 and the solder 110, the flip is flipped. There is a risk that the solder-on pads are electrically shorted to each other during chip bonding, and there is a technical limitation that the deviation of plating is not easily managed in the solder plating process of FIG. 1F. In addition, the prior art has a difficulty in managing the deviation during the solder reflow (reflow) process.

따라서, 본 발명의 제1 목적은 도전층 형성을 위하여 메탈 스퍼터 공정 및 후속 단계에서 이를 박리하는 공정이 필요없는 솔더 온 패드(SoP; solder on pad) 형성 방법을 제공하는 데 있다. Accordingly, it is a first object of the present invention to provide a method for forming a solder on pad (SoP) that does not require a metal sputtering process and a step of peeling it off in a subsequent step to form a conductive layer.

본 발명의 제2 목적은 상기 제1 목적에 부가하여, 솔더 온 패드(SoP) 사이의 전기적 단락의 발생을 최소화하면서 피치 간격을 미세화할 수 있는 구리 코어(copper core) 솔더 온 패드 형성 방법을 제공하는 데 있다.In addition to the first object, a second object of the present invention is to provide a method for forming a copper core solder on pad capable of minimizing a pitch interval while minimizing occurrence of an electrical short between the solder on pads (SoP). There is.

상기 목적을 달성하기 위하여, 본 발명은 캐리어의 동박에 드라이 필름의 패턴에 따라 노출된 동박을 해프 에칭하여 요철 형태를 형성하고, 솔더 도금으로 요철 내부에 솔더를 형성하고, 솔더 위에 동도금으로 요철을 충진하고 적층 빌드업 및 홀가공을 통해 상기 솔더 위에 동도금된 패드를 형성하고 캐리어를 박리함으로써 솔더 패드는 동도금으로 형성하고 솔더 역시 도금 방식으로 형성함으로써 편차를 최소화하고 솔더 온 패드 사이에는 절연층으로 구성된 댐이 존재하므로 플립 칩 실장 시에 솔더 온 패드가 퍼져서 서로 단락되는 것이 원천 차단된다. In order to achieve the above object, the present invention forms a concave-convex shape by half-etching the copper foil exposed to the copper foil of the carrier according to the pattern of the dry film, to form a solder inside the concave-convex by solder plating, the concave-convex by copper plating on the solder Filling, lamination build-up and hole forming to form a copper plated pad on the solder and peeling the carrier, the solder pad is formed of copper plating and the solder is also formed by plating method to minimize the deviation and the insulating layer between the solder-on pad The presence of a dam prevents solder-on pads from spreading during flip-chip mounting, preventing them from shorting to each other.

본 발명은 반도체 다이를 플립칩 방식으로 실장하기 위한 기판 패드와 솔더 온 패드(SoP)를 형성하는 방법에 있어서, (a) 제1 절연층을 사이에 두고 양면에 제1 동박이 피복된 구조의 제1 동박 위에 접착층을 형성하고 그 위에 제2 동박을 적층하여 캐리어를 형성하고, 제2 동박 표면에 드라이 필름을 도포하고 패드를 형성할 위치를 정의하는 패턴을 전사하여 상기 드라이 필름을 선택 식각하는 단계; (b) 상기 선택 식각된 드라이 필름 패턴에 의해 표면이 노출된 제2 동박의 표면을 해프 에칭하여 제2 동박의 표면에 요철을 형성하는 단계; (c) 상기 제2 동박의 요철 표면에 솔더 도금을 형성하는 단계; (d) 상기 솔더 도금 위의 요철을 충진하도록 동도금을 수행하여, 상기 요철의 표면에 덮여 있는 솔더 도금 위에 제1 동도금을 형성하는 단계; (e) 상기 드라이 필름을 박리하고 표면을 연마하여 패드가 형성될 부위에는 제1 동도금이 노출되고, 나머지 부분은 제2 동박 표면이 노출되도록 평탄화하는 단계; (f) 상기 단계 (e) 결과 평탄화된 구조물의 양 표면 위에, 제2 절연층을 적층하고 상기 제2 절연층을 선택 식각하여 제1 홀을 형성하여 상기 제1 동도금 표면을 노출하고, 상기 제1 홀을 충진 하도록 동도금을 진행하여 상기 제1 동도금 표면 위에 제2 동도금을 형성하고, 상기 제2 동도금을 선택 식각함으로써 상기 솔더 도금 위에 제1 동도금과 제2 동도금이 적층 연결된 패드를 형성하는 단계; 및 (g) 상기 캐리어 위에 형성된 구조물에 대하여 접착층을 벗겨내어(peel off) 캐리어를 박리함으로써 상하 두 개의 적층 구조로 분리하고, 박리된 적층 구조를 알칼리 에칭하고 노출된 제2 동박을 식각 제거함으로써, 동도금이 적층 연결되어 패드를 형성하고 그 위에 솔더 도금 형성된 솔더 온 패드를 노출 형성하는 단계를 포함하는 제조 방법을 제공한다.The present invention provides a method for forming a substrate pad and a solder on pad (SoP) for mounting a semiconductor die in a flip chip method, comprising: (a) a structure in which a first copper foil is coated on both surfaces with a first insulating layer interposed therebetween; Forming an adhesive layer on the first copper foil and laminating a second copper foil thereon to form a carrier, applying a dry film to the surface of the second copper foil, transferring a pattern defining a position to form a pad, and selectively etching the dry film. step; (b) half-etching the surface of the second copper foil whose surface is exposed by the selective etched dry film pattern to form irregularities on the surface of the second copper foil; (c) forming solder plating on the uneven surface of the second copper foil; (d) performing copper plating to fill the unevenness on the solder plating to form a first copper plating on the solder plating covered on the surface of the unevenness; (e) peeling the dry film and polishing the surface to planarize the first copper plating to be exposed to the site where the pad is to be formed and the remaining part to expose the second copper foil surface; (f) forming a first hole by stacking a second insulating layer and selectively etching the second insulating layer on both surfaces of the planarized structure as a result of step (e) to expose the first copper plating surface, and Performing copper plating to fill one hole to form a second copper plating on the first copper plating surface, and selectively etching the second copper plating to form a pad in which the first copper plating and the second copper plating are laminated on the solder plating; And (g) peeling off an adhesive layer to the structure formed on the carrier to peel off the carrier to separate the upper and lower laminated structures, alkali-etching the peeled laminated structure and etching away the exposed second copper foil, Copper plating is laminated to form a pad, and to provide a manufacturing method comprising the step of exposing and forming a solder-plated solder on pad thereon.

본 발명은 종래 기술과 달리 고비용의 스퍼터 공정 및 박리 공정이 필요 없으며, 솔더 온 패드 내부에 구리 코어가 존재하므로 플립 칩 접합 시에 전기적 단락의 위험성이 전혀 없는 장점이 있다. 더욱이, 본 발명은 소프트 골드 도금과 같은 고가의 패드 피니시 처리가 필요 없으므로 제조 원가를 낮출 수 있는 장점이 있다. Unlike the prior art, the present invention does not require an expensive sputtering process and a peeling process, and there is no risk of an electrical short circuit during flip chip bonding because a copper core is present inside the solder-on pad. Furthermore, the present invention has the advantage of lowering the manufacturing cost since no expensive pad finish treatment such as soft gold plating is required.

이하에서는, 첨부 도면 도2a 내지 도2j를 참조하여 본 발명에 따라 플립 칩 실장을 위한 솔더 온 패드 제조 방법을 상세히 설명한다. Hereinafter, a method of manufacturing a solder on pad for flip chip mounting according to the present invention will be described in detail with reference to FIGS. 2A to 2J.

도2a 내지 도2j는 본 발명의 양호한 실시예에 따른 솔더 온 패드 제조 공법을 나타낸 도면이다. 도2a를 참조하면, 제1 절연층(210)의 상하 양쪽 표면에 제1 동박(211, 212)이 피복된 레이어(copper cladded laminate; 통상 당업계에서는 "CCL"이라 칭하고 있다)에 제2 동박(220)을 접착층(221)을 사이에 두고 서로 적층한다. 본 발명의 양호한 실시예로서, 접착층(221)은 도전성 접착제를 사용할 수 있다. 2A to 2J are views illustrating a solder on pad manufacturing method according to a preferred embodiment of the present invention. Referring to FIG. 2A, a second copper foil is formed on a copper cladded laminate (commonly referred to as “CCL” in the art) coated with first copper foils 211 and 212 on upper and lower surfaces of the first insulating layer 210. The 220 is laminated with each other with the adhesive layer 221 interposed therebetween. As a preferred embodiment of the present invention, the adhesive layer 221 may use a conductive adhesive.

도2b를 참조하면, 캐리어(250) 표면에 드라이 필름(260)을 도포하고 패드(pad)가 위치할 곳이 노출되도록 드라이 필름(260)을 패턴 형성한다. 이어서, 도2c를 참조하면, 드라이 필름(260) 패턴에 의해 노출된 제2 동박(220) 표면을 해프 에칭함으로써 약 15 ㎛ 정도 깊이를 갖도록 요철 형태(215)로 식각을 한다.Referring to FIG. 2B, the dry film 260 is coated on the surface of the carrier 250, and the dry film 260 is patterned to expose a place where a pad is located. Subsequently, referring to FIG. 2C, the surface of the second copper foil 220 exposed by the dry film 260 pattern is etched into the uneven shape 215 to have a depth of about 15 μm by half etching.

도2d를 참조하면, 해프 에칭되어 노출된 표면에 솔더 도금(265)을 진행하고 이어서 동도금을 진행해서 요철 형태(215)를 솔더 도금(265)과 제1 동도금(270)으로 완전히 충진한다. 도2e를 참조하면, 드라이 필름(260)을 박리 제거하고 표면을 연마(grinding)한다.Referring to FIG. 2D, the solder etched surface 265 is half-etched and then copper plated to completely fill the uneven form 215 with the solder plating 265 and the first copper plating 270. Referring to FIG. 2E, the dry film 260 is peeled off and the surface is ground.

이어서, 기판의 표면에 제2 절연층(280), 예를 들어 프리프레그를 적층하고 홀가공을 통해 제2 절연층(280)에 제1 홀(281)을 형성한다. 도2g를 참조하면, 동도금 공정을 진행해서 제1 홀(281) 내부를 제2 동도금(285)으로 충진하도록 진행하여 동박을 기판 표면에 형성하고, 드라이 필름(도시하지 않음)으로 패드와 패드가 분리되도록 패턴을 형성하고 식각하여 솔더 온 패드를 구성한다. 이어서, 드라이 필름을 박리 제거한 후 표면을 연마하여 평탄화하고, 빌드업(build-up) 공정을 수행한다(도2h).Subsequently, a second insulating layer 280, for example, a prepreg, is stacked on the surface of the substrate, and a first hole 281 is formed in the second insulating layer 280 through hole processing. Referring to FIG. 2G, the copper plating process is performed to fill the inside of the first hole 281 with the second copper plating 285 to form copper foil on the surface of the substrate, and the pad and the pad are formed of a dry film (not shown). The solder-on pad is formed by patterning and etching to separate. Subsequently, after peeling off the dry film, the surface is polished and planarized, and a build-up process is performed (FIG. 2H).

도2h에서 생략한 빌드 업 공정은 절연층과 적층한 후, 드라이필름으로 패턴을 형성하여 재차 제2 홀 가공을 하고 제3 동도금을 수행하여 적층된 형태의 솔더 온 패드가 제작된다. 이어서, 도2h의 감광성 레지스트 잉크(296)를 도포하고 접착제(221)를 필 오프(peel off)하여 캐리어(250) 상하로 형성된 적층 구조를 캐리어(250)로부터 박리하면, 도2i와 같은 적층 구조 두 개를 얻게 된다. 이어서, 알칼리 에칭을 통해 제2 동박(220)을 식각 제거하면, 도2j와 같은 솔더 온 패드와 패드가 형성된다. The build-up process, which is omitted in FIG. 2H, is stacked with an insulating layer, and then a pattern is formed of a dry film to perform second hole processing and third copper plating to fabricate a stacked solder-on pad. Subsequently, when the photosensitive resist ink 296 of FIG. 2H is applied, the adhesive 221 is peeled off, and the laminated structure formed above and below the carrier 250 is peeled from the carrier 250, the laminated structure as shown in FIG. 2I. You get two. Subsequently, when the second copper foil 220 is etched away through alkali etching, a solder-on pad and a pad as shown in FIG. 2J are formed.

전술한 내용은 후술할 발명의 특허 청구 범위를 더욱 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개선하였다. 본 발명의 특허 청구 범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다. The foregoing has somewhat broadly improved the features and technical advantages of the present invention to better understand the claims that follow. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용될 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가능하다. In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

이상과 같이, 본 발명에 솔더 온 패드 형성 기술은 솔더 사이에 댐이 형성되 어 있으므로 플립칩 접합 시에 전기적 단락의 위험성이 제거된다. 따라서, 솔더 온 패드 피치 간격을 미세화할 수 있다. 또한, 본 발명은 패드에 대한 피니시(finish) 처리가 필요 없어지므로 제조 원가가 감소하는 효과가 있다. As described above, in the solder-on-pad forming technique of the present invention, since dams are formed between the solders, the risk of an electrical short when flip-chip bonding is eliminated. Therefore, the solder-on pad pitch interval can be refined. In addition, since the present invention eliminates the need for a finish treatment on the pad, there is an effect of reducing the manufacturing cost.

도1a 내지 도1h는 종래 기술에 따라 기판에 솔더를 형성하는 과정을 나타낸 도면.1A to 1H illustrate a process of forming solder on a substrate according to the prior art.

도2a 내지 도2j는 본 발명의 양호한 실시예에 따른 솔더 온 패드 제조 공법을 나타낸 도면.2A-2J illustrate a solder on pad fabrication process in accordance with a preferred embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10: 관통홀        10: through hole

20: 비아홀        20: Via Hole

25: 스퍼터 메탈층        25: sputter metal layer

30, 260: 드라이 필름   30, 260: dry film

40: 범프 도금        40: bump plating

45: Ni/Au 도금        45: Ni / Au Plating

50, 265: 솔더 도금   50, 265: solder plating

110: 솔더       110: solder

210: 제1 절연층       210: first insulating layer

211, 212: 제1 동박  211, 212: first copper foil

220: 제2 동박       220: second copper foil

221: 접착층       221: adhesive layer

250: 캐리어       250: carrier

270: 제1 동도금       270: first copper plating

Claims (3)

반도체 다이를 플립칩 방식으로 실장하기 위한 기판 패드와 솔더 온 패드(SoP)를 형성하는 방법에 있어서, In the method for forming a substrate pad and a solder on pad (SoP) for mounting a semiconductor die in a flip chip method, (a) 제1 절연층을 사이에 두고 양면에 제1 동박이 피복된 구조의 제1 동박 위에 접착층을 형성하고 그 위에 제2 동박을 적층하여 캐리어를 형성하고, 제2 동박 표면에 드라이 필름을 도포하고 패드를 형성할 위치를 정의하는 패턴을 전사하여 상기 드라이 필름을 선택 식각하는 단계; (a) Forming an adhesive layer on a first copper foil having a structure in which first copper foil is coated on both surfaces with a first insulating layer interposed therebetween, laminating a second copper foil thereon to form a carrier, and drying the dry film on the surface of the second copper foil. Selectively etching the dry film by transferring a pattern defining a location to apply and form a pad; (b) 상기 선택 식각된 드라이 필름 패턴에 의해 표면이 노출된 제2 동박의 표면을 해프 에칭하여 제2 동박의 표면에 요철을 형성하는 단계; (b) half-etching the surface of the second copper foil whose surface is exposed by the selective etched dry film pattern to form irregularities on the surface of the second copper foil; (c) 상기 제2 동박의 요철 표면에 솔더 도금을 형성하는 단계; (c) forming solder plating on the uneven surface of the second copper foil; (d) 상기 솔더 도금 위의 요철을 충진하도록 동도금을 수행하여, 상기 요철의 표면에 덮여 있는 솔더 도금 위에 제1 동도금을 형성하는 단계; (d) performing copper plating to fill the unevenness on the solder plating to form a first copper plating on the solder plating covered on the surface of the unevenness; (e) 상기 드라이 필름을 박리하고 표면을 연마하여 패드가 형성될 부위에는 제1 동도금이 노출되고, 나머지 부분은 제2 동박 표면이 노출되도록 평탄화하는 단계; (e) peeling the dry film and polishing the surface to planarize the first copper plating to be exposed to the site where the pad is to be formed and the remaining part to expose the second copper foil surface; (f) 상기 단계 (e) 결과 평탄화된 구조물의 양 표면 위에, 제2 절연층을 적층하고 상기 제2 절연층을 선택 식각하여 제1 홀을 형성하여 상기 제1 동도금 표면을 노출하고, 상기 제1 홀을 충진 하도록 동도금을 진행하여 상기 제1 동도금 표면 위에 제2 동도금을 형성하고, 상기 제2 동도금을 선택 식각함으로써 상기 솔더 도금 위에 제1 동도금과 제2 동도금이 적층 연결된 패드를 형성하는 단계; 및(f) forming a first hole by stacking a second insulating layer and selectively etching the second insulating layer on both surfaces of the planarized structure as a result of step (e) to expose the first copper plating surface, and Performing copper plating to fill one hole to form a second copper plating on the first copper plating surface, and selectively etching the second copper plating to form a pad in which the first copper plating and the second copper plating are laminated on the solder plating; And (g) 상기 캐리어 위에 형성된 구조물에 대하여 접착층을 벗겨내어(peel off) 캐리어를 박리함으로써 상하 두 개의 적층 구조로 분리하고, 박리된 적층 구조를 알칼리 에칭하고 노출된 제2 동박을 식각 제거함으로써, 동도금이 적층 연결되어 패드를 형성하고 그 위에 솔더 도금 형성된 솔더 온 패드를 노출 형성하는 단계(g) Peel-off the adhesive layer to the structure formed on the carrier to peel off the carrier to separate the upper and lower laminated structure, alkali-etched the peeled laminated structure and etched away the exposed second copper foil, copper plating Forming the pads by lamination and exposing the solder-plated solder-on pads thereon; 를 포함하는 제조 방법. Manufacturing method comprising a. 제1항에 있어서, 상기 단계 (f)에 후속하여 제3 절연층을 적층하고 상기 제3 절연층을 선택적으로 식각하여 상기 제1 동도금과 제2 동도금이 적층 연결된 패드 위에 제2 홀을 형성하여 상기 제2 동도금 표면을 노출하고, 상기 제2 홀을 충진 하도록 동도금을 진행하여 제2 동도금 표면에 제3 동도금을 형성하고, 상기 제3 동도금을 선택 식각함으로써 상기 솔더 도금 위에 제1 동도금, 제2 동도금 및 제3 동도금이 적층 연결된 패드를 형성하는 단계를 더 포함하는 제조 방법.The method of claim 1, wherein after the step (f), a third insulating layer is stacked and the third insulating layer is selectively etched to form a second hole on a pad to which the first copper plating and the second copper plating are laminated. The first copper plating, the second copper plating on the solder plating by exposing the second copper plating surface, copper plating to fill the second hole to form a third copper plating on the second copper plating surface, and selectively etching the third copper plating. And forming a pad in which copper plating and third copper plating are laminated. 제1항 또는 제2항에 따라 제조된 솔더 온 패드를 구비한 패키지 기판.A package substrate with a solder on pad made according to claim 1.
KR1020070138735A 2007-12-27 2007-12-27 Method of fabricating a solder on pad for coreless package substrate technology KR100925669B1 (en)

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