KR101100034B1 - Method for fabricating integral interposer pcb and pcb thereby - Google Patents

Abstract

PURPOSE: An interposer integrated printed circuit board and a manufacturing method thereof are provided to form a micro circuit pattern by forming a silicon interposer and a printed circuit board into one body. CONSTITUTION: An insulating board is composed so that first circuit patterns are impregnated. A silicon interposer board(400) is faced in the side in which first circuit patterns of the insulating substrate are impregnated. A first via hole and a penetration groove pass through the silicon interposer board. A second via hole exposes one among first circuit patterns by selectively eliminating a part of the insulating board which is exposed to the floor of the first via hole. A first penetration via(440) which fills the first via hole and the second via hole and second circuit patterns which fills the grooves are formed. The first penetration via is connected to a semiconductor chip(600) which is mounted in the silicon interposer board.

Description

Interposer integrated printed circuit board and manufacturing method {Method for fabricating integral interposer PCB and PCB hence}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board (PCB) technology, and more particularly, to a printed circuit board and a manufacturing method integrated with a silicon interposer (Si interposer) and a PCB substrate (substrate).

Printed circuit boards (PCBs) have circuit wires comprising copper plating layers or copper plating vias that are electrically conductive within an epoxy insulating layer. Since the PCB has circuit wirings and an insulating layer, the semiconductor silicon chip and the thermal expansion coefficient of the PCB are different from each other. Accordingly, thermal stress is induced to connect the chip and the PCB. Cracks may be caused in the member, such as solder balls or chips or vias. Due to the difference in thermal expansion coefficients between active chips such as semiconductor chips and PCBs, component damage and reliability problems are on the rise.

In addition, as the development of large-capacity and ultra-small components is required, very small sized fine patterns are required for packages. For example, in the SIP (System In Package) technology, a fine pattern is required to implement a fine circuit, but the PCB structure has a limitation in forming a fine pattern. In addition, efforts to minimize loss due to impedance mismatch and signal delay and to improve the mounting area per unit area are required.

The present invention aims to provide a printed circuit board and a manufacturing method in which an interposer and a substrate are integrated, which can improve thermal and electrical performance by improving thermal heat dissipation and implement a fine circuit pattern.

One aspect of the invention, forming the first circuit patterns on the first seed layer of the carrier substrate; Introducing and pressing an insulating substrate and a silicon interposer substrate on the carrier substrate so that the first circuit patterns are impregnated to the insulating substrate; Forming first via holes and through grooves through the silicon interposer substrate; Selectively removing a portion of the insulating substrate exposed to the bottom of the first via hole to form a second via hole exposing any one of the first circuit patterns; Forming first through vias filling the first and second via holes together and second circuit patterns filling the grooves; Detaching the carrier substrate; And exposing the bottom surface of the first circuit patterns by removing the first seed layer exposed by the detachment of the carrier substrate.

The method may further include forming a copper layer on the interface between the carrier substrate and the first seed layer to serve as a detachable release layer of the carrier substrate.

The first seed layer may be formed on the carrier substrate including a copper layer to copper plate the first circuit patterns.

The forming of the first via hole and the grooves may include forming a first resist pattern on the silicon interposer substrate; And selectively dry etching the portions of the silicon interposer substrate exposed to the first resist pattern.

The forming of the second via hole may include drilling a bottom of the insulating substrate exposed to the first via hole.

The forming of the first through via and the second circuit patterns may be formed on the top surface of the first circuit pattern exposed to the first through via hole and the insulating substrate portions exposed to the bottom of the through grooves. Forming a second seed layer extending over the interposer substrate; Forming a second resist pattern exposing a portion located in the first through via hole and the grooves of the second seed layer; Forming a conductive layer on a portion of the second seed layer exposed to the second resist pattern; And removing the second resist pattern.

After removing the second resist pattern, the conductive layer and the second seed layer portion are sanded and polished to expose the surface of the interposer substrate, thereby separating the electrode into the first through via and the second circuit patterns. It may further comprise the step.

Forming a solder mask exposing a top surface of the first through via and a bottom surface of the first circuit pattern connected to the first through via; Forming a first connection member on a top surface of the first through via for connection with a semiconductor chip; And forming a second connection member on the bottom surface of the first circuit pattern for connection with the module substrate.

The first and second connection members may be attached with solder balls or formed into bumps, and gold may be formed on the upper surface of the exposed first through vias and the lower surface of the first circuit pattern before attaching or forming the solder balls. , Silver (Ag), nickel gold (NiAu), nickel silver (NiAg), nickel silver (NiAgAu), Ni palladium (NiPd), nickel palladium gold (NiPdAu), tin (Sn), or OSP (Organic solderability Preservatives) The method may further include forming a surface treatment layer including a.

Prior to detaching the carrier substrate, forming a passivation layer covering the first through via and the second circuit patterns; And forming second circuit vias passing through the passivation layer and third circuit patterns on the passivation layer.

The passivation layer may be formed by stacking, depositing, or applying an insulating material including an epoxy resin, silicon oxide, or silicon nitride.

The step of forming the passivation layer, the second through via, and the third circuit patterns may be repeated a plurality of times to form a multilayer wiring structure.

Another aspect of the invention, the first circuit pattern impregnated insulating substrate; A silicon interposer substrate attached to an opposite surface opposite to the surface on which the first circuit patterns of the insulating substrate are impregnated; And a first through via penetrating the silicon interposer substrate and the insulating substrate to be connected to the first circuit pattern and to a semiconductor chip to be mounted on the silicon interposer substrate. .

The semiconductor device may further include second circuit patterns penetrating the interposer substrate and insulated by the insulating substrate.

A passivation layer formed on the silicon interposer substrate; And a second through via penetrating through the passivation layer and a third circuit pattern formed on the passivation layer.

According to the present invention, a printed circuit board in which a silicon (Si) interposer and a PCB substrate are integrated can be manufactured, and an integrated printed circuit board using a silicon interposer having substantially the same thermal expansion coefficient as an active semiconductor chip can be realized. have. The application of silicon interpose improves heat dissipation to effectively suppress thermal deformation, and also enables the implementation of fine circuit patterns, thereby overcoming component damage and reliability problems caused by thermal deformation, and signal delay and impedance mismatch. Loss can be suppressed, and the mounting area per unit area can be maximized, enabling the development of large-capacity and ultra-small components. Accordingly, it is possible to implement thermal and electrical performance improvement of the package component.

1 to 18 illustrate an interposer integrated printed circuit board manufacturing method according to an exemplary embodiment of the present invention.
19 and 20 illustrate a modified example of a method of manufacturing an interposer integrated printed circuit board according to an exemplary embodiment of the present invention.

Embodiments of the present invention provide a method of integrally fabricating a silicon interposer and a PCB substrate. The circuit wiring electrically connected inside the silicon interposer can be implemented, so that the circuit embedding can provide a fine circuit pattern compared to a general PCB substrate. By implementing a silicon interposer with substantially the same thermal expansion coefficient as a silicon active semiconductor chip, thermal stress relief can improve reliability problems and improve thermal conductivity. Accordingly, heat dissipation may be improved when the chip is mounted on a SIP, a module, or a package on package (POP). The silicon interposer may provide a buffering effect for suppressing interlayer thermal stress in manufacturing a high-layer substrate. Since the interconnection between the silicon interposer and the PCB substrate is integrated, crack generation due to thermal stress on the solder ball can be effectively prevented.

Referring to FIG. 1, a carrier substrate 100 is introduced into a handling member for performing a process. The carrier substrate 100 may be introduced into an insulating layer such as epoxy or a stainless steel (SUS) substrate. The first copper foil layer 110 and the second copper foil layer 120 are formed on the carrier substrate 100. The first copper foil layer 110 is introduced to act as a release layer when leaving the carrier substrate 100 in a subsequent process, and the second copper foil layer 120 is a first seed layer when forming the first circuit pattern. It is used as the underlying layer.

When the carrier substrate 100 is removed after the circuit pattern is formed, the first copper foil layer 110 serves as a release layer, and the first copper foil layer 110 and the second copper foil layer 120 are substantially the same copper ( Since it is formed of a Cu) layer, the thickness of the second copper foil layer 120, which is the first seed layer remaining upon release of the carrier substrate 100, may be induced to have a thinner thickness. When the second copper foil layer 120 is a release adhesive layer other than the copper layer, the thickness of the second copper foil layer 120 is limited to be thin, and thus the thickness to be removed in the etching process of removing the subsequent second copper foil layer 120. Becomes large. Therefore, by introducing the first copper foil layer 110 as a release layer, the second copper foil layer 120 can be made thin, and thus a process of removing the second copper foil layer 120 after the circuit pattern is formed can be shortened. The productivity increase effect can be realized. In addition, by attaching a copper clad laminate film such as CCL on the carrier substrate 100, the first and second copper foil layers 110 and 120 may be stacked on the carrier substrate 100. Using a structure in which the first and second copper foil layers 110 and 120 are stacked on the substrate 100 is more advantageous when considering the productivity of the process.

Referring to FIG. 2, a first circuit pattern 210 including a copper layer is formed on the second copper foil layer 120. The first circuit pattern 210 is formed by forming a first resist pattern 201 on a second copper foil layer 120 by a lithography process including attaching, exposing and developing a dry resist film. Thereafter, copper plating may be performed using a portion of the second copper foil layer 120 exposed to the first resist pattern 201 as a first seed layer, and then stripped off the first resist pattern 201. have. In this case, a deposition process such as sputtering may be introduced instead of copper plating. Alternatively, after the copper plating layer is plated on the entire surface of the second copper foil layer 120, a first resist pattern is formed on the plating layer, and then the first circuit pattern 210 is formed by selectively etching the plating layer using the same. It may be. Considering that the first circuit pattern 210 should be patterned to have a smaller size and that the selective etching of the copper layer is quite difficult, the first circuit pattern 210 is formed after forming the first resist pattern 201. The process of forming the first circuit pattern 210 by copper plating is more advantageous to form the first circuit pattern 210 having a finer size in a more precise shape.

Referring to FIG. 3, an insulating substrate 300 and an interposer substrate 400 are introduced over the carrier substrate 100 including the first circuit pattern 210. The insulating substrate 300 may be an insulating resin such as a prepreg substrate, but a resin copper foil coating agent (RCC) resin or an ABF resin blended with an epoxy resin and a thermoplastic resin may be used. The interposer substrate 400 may be a silicon semiconductor chip or a silicon (Si) substrate which is the same material as the silicon forming the active chip.

Referring to FIG. 4, an insulating substrate 300, which is a prepreg substrate, is stacked on a carrier substrate 100 including a first circuit pattern 210, and a silicon interposer substrate 400 is disposed on the insulating substrate 300. After lamination | stacking, it press-presses and attaches. At this time, the first circuit pattern 210 is impregnated and embedded in the prepreg of the insulating substrate 300.

Referring to FIG. 5, a second resist pattern 205 is formed on the interposer substrate 400. The second resist pattern 205 is a mold for patterning a first via hole and a second circuit pattern passing through the interposer substrate 400 through a lithography process of attaching, exposing and developing a dry resist film. It can be formed to expose the portion where the through grooves as will be located.

Referring to FIG. 6, a portion of the interposer substrate 400 exposed by the second resist pattern 205 may be selectively etched to penetrate the first via hole 401 and the second circuit pattern. Through grooves 402 are formed. In this case, the etching process may be performed as an anisotropic dry etching process. Since the first via hole 401 and the through grooves 402 may be formed by the silicon process, the size of the first via hole 401 and the through grooves 402 may be formed to have a finer size. The silicon interposer substrate 400 may be introduced at a very thin thickness, for example, between 100 μm and several tens of μm. Even when the silicon interposer substrate 400 is introduced in such a thin thickness, the process is performed while the interposer substrate 400 is attached to the carrier substrate 100, and thus, the thin interposer substrate 400 Wrappage of the silicon interposer substrate 400 may be suppressed. That is, the substrate curling phenomenon can be suppressed, and the thickness of the silicon interposer substrate 400 can be introduced at a very thin thickness. Since the thickness of the silicon interposer substrate 400 can be introduced thinly, the process burden can be relatively reduced to perform the dry etching process of forming the first via holes 401 and the through grooves 402, and moreover. It is possible to form the first via hole 401 and the through grooves 402 in a fine size. Therefore, it can be effectively applied to mounting a micro semiconductor chip or an active chip.

Referring to FIG. 7, a silicon oxide layer is formed by selectively removing the second resist pattern 205 and forming an insulating layer for insulating the sidewalls of the first via hole 401 and the through grooves 402 through thermal oxidation. And not shown). Since the interposer substrate 400 is made of silicon, silicon oxide may be formed as an insulating layer by oxidation of silicon.

Referring to FIG. 8, the second via hole 403 connected to the first via hole 401 is formed through the lower insulating substrate 300 to expose the first circuit pattern 210. A portion of the lower insulating substrate 300 exposed by the first via hole 401 is drilled to form a second via hole 403 exposing the lower first circuit pattern 210. Accordingly, the through via hole 410 penetrating the interposer substrate 400 and the insulating substrate 300 is formed to have the first and second via holes 401 connected thereto. The drilling process can be performed with a laser drilling process.

Referring to FIG. 9, the second seed layer 430 is deposited on the first circuit pattern 210 exposed by the through via hole 410 and on the portion of the insulating substrate 300 exposed by the through groove 402. do. The second seed layer 430 may be deposited including a copper layer and may extend on sidewalls of the through via hole 410 and the through groove 402.

Referring to FIG. 10, in order to form the first through via and the second circuit pattern to be connected to the first circuit pattern 210, the second seed layer 430 and the interposer substrate of the bottom portion of the through via hole 410 are formed. A third resist pattern 207 is formed to open portions of the second seed layer 430 at the bottom of the through groove 402 penetrating only the 400. The third resist pattern 207 may be formed by performing a lithography process including attaching, exposing and developing a dry resist film.

Referring to FIG. 11, a first through via 440 filling the through via hole 410 is formed by performing a conductive layer formation process such as copper plating on a portion of the second seed layer 430 exposed to the third resist pattern 207. And second circuit patterns 450 filling the through grooves 402. Thereafter, the third resist pattern 207 is selectively stripped. The first through via 440 penetrates the interposer substrate 400 and the insulating substrate 300 to provide an electrical connection path, and the second circuit pattern 450 is electrically connected to the first through via 400. A circuit can be provided.

Referring to FIG. 12, the upper surface of the silicon interposer substrate 400 is planarized to remove the second seed layer 430, thereby separating the first through via 440 and the second circuit patterns 450 from each other. (node separation) In this case, the planarization process may be performed by an abrasive sanding process such as chemical mechanical polishing (CMP) process. The first seeding via 440 and the second circuit patterns 450 may be polished by grinding the second seed layer 430, the first through via 440, and the upper part of the second circuit patterns 450 by the sanding process. The top surface of) has a surface height that is substantially the same as the top surface of interposer substrate 400. Accordingly, the surface of the interposer substrate 400 has a flat surface.

Referring to FIG. 13, the carrier substrate 100 is detached. In this case, since the first copper foil layer 110 serves as a release layer, as shown in FIG. 13, the second copper foil layer 120 on the top remains and the carrier substrate 100 is detached. Referring to FIG. 14, after the protective layer 209 is attached and masked on the interposer substrate 400, the first copper foil layer 110 on the lower surface is etched and removed. Accordingly, the bottom surface of the first circuit pattern 210 is exposed to the outside. The removal of the first copper foil layer 110 may be performed by a wet etching process, and the protective layer 209 may be introduced into a dry resist film to protect the upper surface of the interposer substrate 400 during wet etching. Thereafter, the protective layer 209 may be selectively removed.

Referring to FIG. 15, pretreatment, eg, copper surfaces, on the upper surface of the first through via 410 of the exposed interposer substrate 400 and the exposed surface of the first and second circuit patterns 210, 450. After the roughening process, a solder mask 510 is formed. The solder mask 510 may be formed to expose a portion to which a first connection member such as solder ball is attached, for example, an upper surface of the first through via 440 and a lower surface of the first circuit pattern 210 connected thereto. The solder mask 510 may be formed through coating, drying, exposure and development, heating or ultraviolet irradiation for curing of the solder mask material. Some of the first circuit patterns 210 and the second circuit patterns 450 that are patterned for the inner circuit wiring without being exposed to the outside are blocked by the solder mask 510.

Referring to FIG. 16, a surface treatment layer 530 is formed on the surface of the first circuit pattern 210 and the surface of the first through via 440 exposed to the solder mask 510. As the surface treatment process, soft gold plating or electroless nickel immersion gold (ENIG) process may be mainly used. In addition, general surface treatment processes such as electroless Ni and electroless Pd and immersion gold (ENEPIG) and TIN plating may be used. That is, the surface treatment layer 530 is gold (Au), silver (Ag), nickel gold (NiAu), nickel silver (NiAg), nickel silver (NiAgAu), Ni palladium (NiPd), nickel palladium gold (NiPdAu ), Tin (Sn) or OSP (Organic solderability Preservatives) layer may be formed. Thereafter, a router process of separating the individual substrate parts may be performed.

Referring to FIG. 17, a first connection member such as the first solder ball 550 is attached to the surface treatment layer 530 through a SOP (Solder On Pad) process. In this case, a bump may be formed instead of the first solder ball 550.

Referring to FIG. 18, the semiconductor chip 600 or the active chip is mounted using the first solder ball 550. In this case, since the semiconductor chip 600 and the silicon interpose substrate 400 are positioned to face the semiconductor chip 600, the thermal expansion coefficients of the semiconductor chip 600 and the silicon interpose substrate 400 may be substantially similar. In addition, it is possible to effectively suppress the occurrence of a crack in the connecting member such as the first brush ball 550 by thermal stress. Heat generated in the semiconductor chip 600 is transferred to the interpose substrate 400, and the degree of expansion due to the heat can be maintained similarly between the semiconductor chip 600 and the interpose substrate 400, so that the first solder Excessive thermal stress can be prevented from being applied to the connection member such as the ball 550. The interposer substrate 400 may function to buffer and alleviate the release of heat and thermal stress from lowering reliability.

Electrical connection passages by the first connection member such as the first solder ball 550 connected to the semiconductor chip 600 are connected to the first circuit pattern 210 through the first through via 440, and the first circuit pattern. It may be connected to another PCB substrate such as module PCB 700 by another second connection member such as second solder ball 570 attached to 210.

Meanwhile, by forming a passivation layer on the interposer substrate 400 and forming second through vias and third circuit patterns penetrating the interlayer substrate 400, a multilayer wiring structure may be implemented.

Referring to FIG. 19, a passivation layer 310 is formed to cover and block the interposer substrate 400. The passivation layer 310 may be formed by stacking, depositing, or applying an insulating layer such as epoxy resin, silicon oxide, or silicon nitride.

Referring to FIG. 20, after forming the third through via hole 311 penetrating the passivation layer 310, a conductive layer, for example, a copper layer filling the third through via hole 311 is formed on the passivation layer 310. do. Lithography and etching processes of patterning the conductive layer may be performed to form second through vias 313 and third circuit patterns 315 filling the third through vias 311. By repeating these processes, a multilayer wiring structure can be realized.

Thereafter, as described with reference to FIG. 15, a solder mask forming process, a surface treatment layer forming process, an SOP process, and a chip mounting process may be performed.

Embodiments of the present invention as described above provide a method of integrally manufacturing a silicon interposer and a PCB substrate. The circuit wiring electrically connected inside the silicon interposer can be implemented, so that the circuit embedding can provide a fine circuit pattern compared to a general PCB substrate. By implementing a silicon interposer with substantially the same thermal expansion coefficient as a silicon active semiconductor chip, thermal stress relief can improve reliability problems and improve thermal conductivity.

100: carrier substrate, 210, 315, 450: circuit pattern,
300: insulated substrate, 313, 440: through via,
400: silicon interposer substrate.

Claims (15)

Forming first circuit patterns on a first seed layer of a carrier substrate;
Introducing and pressing an insulating substrate and a silicon interposer substrate on the carrier substrate so that the first circuit patterns are impregnated to the insulating substrate;
Forming first via holes and through grooves through the silicon interposer substrate;
Selectively removing a portion of the insulating substrate exposed to the bottom of the first via hole to form a second via hole exposing any one of the first circuit patterns;
Forming first through vias filling the first and second via holes together and second circuit patterns filling the grooves;
Detaching the carrier substrate; And
And removing the first seed layer exposed by the detachment of the carrier substrate to expose the bottom surfaces of the first circuit patterns.
The method of claim 1,
And forming a copper layer on the interface between the carrier substrate and the first seed layer to serve as a release layer when the carrier substrate is desorbed.
The method of claim 1,
And the first seed layer is formed on the carrier substrate including a copper layer to copper plate the first circuit patterns.
The method of claim 1,
Forming the first via hole and grooves
Forming a first resist pattern on the silicon interposer substrate; And
Selectively dry etching the portions of the silicon interposer substrate exposed to the first resist pattern.
The method of claim 1,
Forming the second via hole
And drilling a bottom of the insulating substrate exposed to the first via hole.
The method of claim 1,
Forming the first through via and the second circuit patterns
Forming a second seed layer formed on upper portions of the first circuit pattern exposed to the second through via hole and portions of the insulating substrate exposed on the bottom of the through grooves and extending onto the silicon interposer substrate. ;
Forming a second resist pattern exposing a portion located in the first through via hole and the grooves of the second seed layer;
Forming a conductive layer on a portion of the second seed layer exposed to the second resist pattern; And
And removing the second resist pattern.
The method of claim 6,
After removing the second resist pattern,
And sanding and polishing the conductive layer and the second seed layer portions to expose the surface of the interposer substrate to separate the electrodes into the first through vias and the second circuit patterns. Printed circuit board manufacturing method.
The method of claim 1,
Forming a solder mask exposing a top surface of the first through via and a bottom surface of the first circuit pattern connected to the first through via;
Forming a first connection member on a top surface of the first through via for connection with a semiconductor chip; And
And forming a second connection member on the lower surface of the first circuit pattern to connect with the module substrate.
The method of claim 8,
The first and second connection members are attached with solder balls or formed as bumps,
Gold (Au), silver (Ag), nickel gold (NiAu), nickel silver (NiAg), nickel on the upper surface of the exposed first through via and the lower surface of the first circuit pattern prior to the solder ball attachment or bump formation An interposer integrated printed circuit further comprising forming a surface treatment layer comprising silver gold (NiAgAu), Ni palladium (NiPd), nickel palladium gold (NiPdAu), tin (Sn), or organic solderability preservatives (OSP). Substrate manufacturing method.
The method of claim 1,
Before the step of detaching the carrier substrate,
Forming a passivation layer covering the first through via and the second circuit patterns; And
And forming third circuit patterns on the passivation layer and second through vias passing through the passivation layer.
The method of claim 10,
The passivation layer is
An interposer integrated printed circuit board manufacturing method formed by stacking, depositing, or applying an insulating material including epoxy resin, silicon oxide, or silicon nitride.
The method of claim 10,
And repeating the steps of forming the passivation layer, the second through via, and the third circuit patterns a plurality of times to form a multi-layered wiring structure.
An insulating substrate impregnated with first circuit patterns;
A silicon interposer substrate attached to an opposite surface opposite to the surface on which the first circuit patterns of the insulating substrate are impregnated; And
And a first through via penetrating the silicon interposer substrate and the insulating substrate to be connected to the first circuit pattern and to a semiconductor chip to be mounted on the silicon interposer substrate.
The method of claim 13,
And a second circuit pattern passing through the interposer substrate and insulated by the insulating substrate.
The method of claim 13,
A passivation layer formed on the silicon interposer substrate; And
And a multi-layer interconnection structure comprising a second through via penetrating through the passivation layer and third circuit patterns formed on the passivation layer.

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