TWI364814B - Edge removal of silicon-on-insulator transfer wafer - Google Patents

Edge removal of silicon-on-insulator transfer wafer Download PDF

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Publication number
TWI364814B
TWI364814B TW094141169A TW94141169A TWI364814B TW I364814 B TWI364814 B TW I364814B TW 094141169 A TW094141169 A TW 094141169A TW 94141169 A TW94141169 A TW 94141169A TW I364814 B TWI364814 B TW I364814B
Authority
TW
Taiwan
Prior art keywords
wafer
transfer
circumferential lip
grinding
transfer wafer
Prior art date
Application number
TW094141169A
Other languages
English (en)
Chinese (zh)
Other versions
TW200629469A (en
Inventor
Raymond John Donohoe
Krishna Vepa
Paul V Miller
Ronald Rayandayan
Hong Wang
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of TW200629469A publication Critical patent/TW200629469A/zh
Application granted granted Critical
Publication of TWI364814B publication Critical patent/TWI364814B/zh

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40Chemomechanical polishing [CMP]
    • H10P52/402Chemomechanical polishing [CMP] of semiconductor materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12Preparing bulk and homogeneous wafers
    • H10P90/16Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/974Substrate surface preparation

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
TW094141169A 2004-11-26 2005-11-23 Edge removal of silicon-on-insulator transfer wafer TWI364814B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/998,289 US7402520B2 (en) 2004-11-26 2004-11-26 Edge removal of silicon-on-insulator transfer wafer

Publications (2)

Publication Number Publication Date
TW200629469A TW200629469A (en) 2006-08-16
TWI364814B true TWI364814B (en) 2012-05-21

Family

ID=36113834

Family Applications (2)

Application Number Title Priority Date Filing Date
TW094141169A TWI364814B (en) 2004-11-26 2005-11-23 Edge removal of silicon-on-insulator transfer wafer
TW097114902A TWI333259B (en) 2004-11-26 2005-11-23 Edge removal of silicon-on-insulator transfer wafer

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW097114902A TWI333259B (en) 2004-11-26 2005-11-23 Edge removal of silicon-on-insulator transfer wafer

Country Status (4)

Country Link
US (3) US7402520B2 (https=)
EP (2) EP1662560B1 (https=)
JP (2) JP5455282B2 (https=)
TW (2) TWI364814B (https=)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7402520B2 (en) * 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer
US20070148917A1 (en) * 2005-12-22 2007-06-28 Sumco Corporation Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer
JP4913484B2 (ja) * 2006-06-28 2012-04-11 株式会社ディスコ 半導体ウエーハの研磨加工方法
KR100839355B1 (ko) * 2006-11-28 2008-06-19 삼성전자주식회사 기판의 재생 방법
EP2015354A1 (en) * 2007-07-11 2009-01-14 S.O.I.Tec Silicon on Insulator Technologies Method for recycling a substrate, laminated wafer fabricating method and suitable recycled donor substrate
US8089055B2 (en) * 2008-02-05 2012-01-03 Adam Alexander Brailove Ion beam processing apparatus
WO2009124060A1 (en) * 2008-03-31 2009-10-08 Memc Electronic Materials, Inc. Methods for etching the edge of a silicon wafer
US7833907B2 (en) * 2008-04-23 2010-11-16 International Business Machines Corporation CMP methods avoiding edge erosion and related wafer
US20100022070A1 (en) * 2008-07-22 2010-01-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
JP5478166B2 (ja) * 2008-09-11 2014-04-23 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR20110099108A (ko) * 2008-11-19 2011-09-06 엠이엠씨 일렉트로닉 머티리얼즈, 인크. 반도체 웨이퍼의 에지를 스트리핑하기 위한 방법 및 시스템
EP2213415A1 (en) 2009-01-29 2010-08-04 S.O.I. TEC Silicon Device for polishing the edge of a semiconductor substrate
EP2219208B1 (en) 2009-02-12 2012-08-29 Soitec Method for reclaiming a surface of a substrate
US8871109B2 (en) * 2009-04-28 2014-10-28 Gtat Corporation Method for preparing a donor surface for reuse
EP2246882B1 (en) * 2009-04-29 2015-03-04 Soitec Method for transferring a layer from a donor substrate onto a handle substrate
DE102009030298B4 (de) * 2009-06-24 2012-07-12 Siltronic Ag Verfahren zur lokalen Politur einer Halbleiterscheibe
CN102460642A (zh) * 2009-06-24 2012-05-16 株式会社半导体能源研究所 半导体衬底的再加工方法及soi衬底的制造方法
US8633090B2 (en) * 2009-07-10 2014-01-21 Shanghai Simgui Technology Co., Ltd. Method for forming substrate with buried insulating layer
US8318588B2 (en) * 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
FR2950733B1 (fr) * 2009-09-25 2012-10-26 Commissariat Energie Atomique Procede de planarisation par ultrasons d'un substrat dont une surface a ete liberee par fracture d'une couche enterree fragilisee
SG178179A1 (en) * 2009-10-09 2012-03-29 Semiconductor Energy Lab Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate
FR2952224B1 (fr) * 2009-10-30 2012-04-20 Soitec Silicon On Insulator Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante.
FR2953988B1 (fr) * 2009-12-11 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de detourage d'un substrat chanfreine.
FR2956822A1 (fr) * 2010-02-26 2011-09-02 Soitec Silicon On Insulator Technologies Procede d'elimination de fragments de materiau presents sur la surface d'une structure multicouche
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
JP5799740B2 (ja) 2011-10-17 2015-10-28 信越半導体株式会社 剥離ウェーハの再生加工方法
JP2013115307A (ja) * 2011-11-30 2013-06-10 Sumitomo Electric Ind Ltd Iii族窒化物複合基板の製造方法
US8853054B2 (en) 2012-03-06 2014-10-07 Sunedison Semiconductor Limited Method of manufacturing silicon-on-insulator wafers
JP2016046341A (ja) * 2014-08-21 2016-04-04 株式会社荏原製作所 研磨方法
JP6086754B2 (ja) * 2013-02-25 2017-03-01 株式会社ディスコ ウェーハの加工方法
JP2014167996A (ja) * 2013-02-28 2014-09-11 Ebara Corp 研磨装置および研磨方法
JP6214901B2 (ja) * 2013-04-04 2017-10-18 株式会社ディスコ 切削装置
US10464184B2 (en) * 2014-05-07 2019-11-05 Applied Materials, Inc. Modifying substrate thickness profiles
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
JP6723892B2 (ja) * 2016-10-03 2020-07-15 株式会社ディスコ ウエーハの加工方法
FR3074608B1 (fr) * 2017-12-05 2019-12-06 Soitec Procede de preparation d'un residu de substrat donneur, substrat obtenu a l'issu de ce procede, et utilisation d'un tel susbtrat
TWI735275B (zh) * 2020-07-03 2021-08-01 聯華電子股份有限公司 半導體結構的製作方法
CN112959211B (zh) * 2021-02-22 2021-12-31 长江存储科技有限责任公司 晶圆处理装置和处理方法
FR3120159B1 (fr) 2021-02-23 2023-06-23 Soitec Silicon On Insulator Procédé de préparation du résidu d’un substrat donneur ayant subi un prélèvement d’une couche par délamination
JP2024134661A (ja) * 2023-03-22 2024-10-04 株式会社東芝 半導体装置の製造方法

Family Cites Families (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US616275A (en) * 1898-12-20 Reciprocating valve
US5000113A (en) * 1986-12-19 1991-03-19 Applied Materials, Inc. Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process
US4721548A (en) * 1987-05-13 1988-01-26 Intel Corporation Semiconductor planarization process
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2839801B2 (ja) * 1992-09-18 1998-12-16 三菱マテリアル株式会社 ウェーハの製造方法
US5770465A (en) * 1995-06-23 1998-06-23 Cornell Research Foundation, Inc. Trench-filling etch-masking microfabrication technique
KR100227924B1 (ko) * 1995-07-28 1999-11-01 가이데 히사오 반도체 웨이퍼 제조방법, 그 방법에 사용되는 연삭방법 및 이에 사용되는 장치
CN1132223C (zh) 1995-10-06 2003-12-24 佳能株式会社 半导体衬底及其制造方法
JPH09270400A (ja) * 1996-01-31 1997-10-14 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
JPH09270401A (ja) * 1996-01-31 1997-10-14 Shin Etsu Handotai Co Ltd 半導体ウェーハの研磨方法
JP3620554B2 (ja) * 1996-03-25 2005-02-16 信越半導体株式会社 半導体ウェーハ製造方法
JP3321527B2 (ja) * 1996-07-22 2002-09-03 シャープ株式会社 半導体装置の製造方法
SG65697A1 (en) 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
US6054363A (en) 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
US5821166A (en) * 1996-12-12 1998-10-13 Komatsu Electronic Metals Co., Ltd. Method of manufacturing semiconductor wafers
JPH10256498A (ja) * 1997-03-06 1998-09-25 Toshiba Corp 半導体記憶装置及びその製造方法
US6159824A (en) 1997-05-12 2000-12-12 Silicon Genesis Corporation Silicon-on-silicon wafer bonding process using a thin film blister-separation method
US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US5920764A (en) * 1997-09-30 1999-07-06 International Business Machines Corporation Process for restoring rejected wafers in line for reuse as new
SG71903A1 (en) * 1998-01-30 2000-04-18 Canon Kk Process of reclamation of soi substrate and reproduced substrate
JP3271658B2 (ja) * 1998-03-23 2002-04-02 信越半導体株式会社 半導体シリコン単結晶ウェーハのラップ又は研磨方法
US6200199B1 (en) 1998-03-31 2001-03-13 Applied Materials, Inc. Chemical mechanical polishing conditioner
JP3932369B2 (ja) 1998-04-09 2007-06-20 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
US6221774B1 (en) * 1998-04-10 2001-04-24 Silicon Genesis Corporation Method for surface treatment of substrates
JP3500063B2 (ja) * 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JP3358550B2 (ja) 1998-07-07 2002-12-24 信越半導体株式会社 Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ
US6246667B1 (en) 1998-09-02 2001-06-12 Lucent Technologies Inc. Backwards-compatible failure restoration in bidirectional multiplex section-switched ring transmission systems
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ
US6276997B1 (en) * 1998-12-23 2001-08-21 Shinhwa Li Use of chemical mechanical polishing and/or poly-vinyl-acetate scrubbing to restore quality of used semiconductor wafers
JP2000223682A (ja) 1999-02-02 2000-08-11 Canon Inc 基体の処理方法及び半導体基板の製造方法
DE19905737C2 (de) * 1999-02-11 2000-12-14 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Halbleiterscheibe mit verbesserter Ebenheit
KR100343136B1 (ko) * 1999-03-18 2002-07-05 윤종용 이중 연마저지층을 이용한 화학기계적 연마방법
US6468923B1 (en) 1999-03-26 2002-10-22 Canon Kabushiki Kaisha Method of producing semiconductor member
FR2794891A1 (fr) 1999-06-14 2000-12-15 Lionel Girardie Preparation de substrats aux techniques de collage direct
US6376378B1 (en) * 1999-10-08 2002-04-23 Chartered Semiconductor Manufacturing, Ltd. Polishing apparatus and method for forming an integrated circuit
JP3943782B2 (ja) * 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
WO2001048825A1 (en) * 1999-12-24 2001-07-05 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
US20010039101A1 (en) * 2000-04-13 2001-11-08 Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Ag Method for converting a reclaim wafer into a semiconductor wafer
US20020164876A1 (en) * 2000-04-25 2002-11-07 Walitzki Hans S. Method for finishing polysilicon or amorphous substrate structures
JP3991300B2 (ja) * 2000-04-28 2007-10-17 株式会社Sumco 張り合わせ誘電体分離ウェーハの製造方法
DE10058305A1 (de) 2000-11-24 2002-06-06 Wacker Siltronic Halbleitermat Verfahren zur Oberflächenpolitur von Siliciumscheiben
JP4156200B2 (ja) * 2001-01-09 2008-09-24 株式会社荏原製作所 研磨装置及び研磨方法
US6448152B1 (en) 2001-02-20 2002-09-10 Silicon Genesis Corporation Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer
US6699356B2 (en) * 2001-08-17 2004-03-02 Applied Materials, Inc. Method and apparatus for chemical-mechanical jet etching of semiconductor structures
JP2003209075A (ja) * 2002-01-15 2003-07-25 Speedfam Co Ltd ウェハエッジ研磨システム及びウェハエッジ研磨制御方法
JP3911174B2 (ja) * 2002-03-01 2007-05-09 シャープ株式会社 半導体素子の製造方法および半導体素子
FR2842648B1 (fr) 2002-07-18 2005-01-14 Commissariat Energie Atomique Procede de transfert d'une couche mince electriquement active
JP2004087522A (ja) * 2002-08-22 2004-03-18 Sumitomo Mitsubishi Silicon Corp 半導体ウェーハの製造方法
EP1427001A1 (en) * 2002-12-06 2004-06-09 S.O.I. Tec Silicon on Insulator Technologies S.A. A method for recycling a surface of a substrate using local thinning
TWI233154B (en) * 2002-12-06 2005-05-21 Soitec Silicon On Insulator Method for recycling a substrate
JP4125148B2 (ja) * 2003-02-03 2008-07-30 株式会社荏原製作所 基板処理装置
JP3534115B1 (ja) * 2003-04-02 2004-06-07 住友電気工業株式会社 エッジ研磨した窒化物半導体基板とエッジ研磨したGaN自立基板及び窒化物半導体基板のエッジ加工方法
JP2005072070A (ja) 2003-08-28 2005-03-17 Sumitomo Mitsubishi Silicon Corp 剥離ウェーハの再生処理方法及び再生されたウェーハ
JP4492054B2 (ja) 2003-08-28 2010-06-30 株式会社Sumco 剥離ウェーハの再生処理方法及び再生されたウェーハ
US7276787B2 (en) * 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US7402520B2 (en) 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer
JP2007019323A (ja) 2005-07-08 2007-01-25 Shin Etsu Handotai Co Ltd ボンドウエーハの再生方法及びボンドウエーハ並びにssoiウエーハの製造方法
JP4715470B2 (ja) 2005-11-28 2011-07-06 株式会社Sumco 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ
JP5314838B2 (ja) 2006-07-14 2013-10-16 信越半導体株式会社 剥離ウェーハを再利用する方法
KR100839355B1 (ko) 2006-11-28 2008-06-19 삼성전자주식회사 기판의 재생 방법

Also Published As

Publication number Publication date
US20080138987A1 (en) 2008-06-12
JP2006179887A (ja) 2006-07-06
EP1662560A3 (en) 2009-07-22
TWI333259B (en) 2010-11-11
EP1662560B1 (en) 2019-06-05
TW200629469A (en) 2006-08-16
EP2048701A2 (en) 2009-04-15
US7951718B2 (en) 2011-05-31
EP1662560A2 (en) 2006-05-31
JP2009283964A (ja) 2009-12-03
EP2048701A3 (en) 2009-04-29
TW200915477A (en) 2009-04-01
US7402520B2 (en) 2008-07-22
JP5455282B2 (ja) 2014-03-26
US20090061545A1 (en) 2009-03-05
US7749908B2 (en) 2010-07-06
US20060115986A1 (en) 2006-06-01

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