TWI340897B - Memory hub architecture having programmable lane widths - Google Patents

Memory hub architecture having programmable lane widths

Info

Publication number
TWI340897B
TWI340897B TW094106980A TW94106980A TWI340897B TW I340897 B TWI340897 B TW I340897B TW 094106980 A TW094106980 A TW 094106980A TW 94106980 A TW94106980 A TW 94106980A TW I340897 B TWI340897 B TW I340897B
Authority
TW
Taiwan
Prior art keywords
programmable
memory hub
hub architecture
lane widths
lane
Prior art date
Application number
TW094106980A
Other languages
English (en)
Other versions
TW200613973A (en
Inventor
Jeffrey R Jobs
Thomas A Stenglein
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW200613973A publication Critical patent/TW200613973A/zh
Application granted granted Critical
Publication of TWI340897B publication Critical patent/TWI340897B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
TW094106980A 2004-03-08 2005-03-08 Memory hub architecture having programmable lane widths TWI340897B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/797,727 US7366864B2 (en) 2004-03-08 2004-03-08 Memory hub architecture having programmable lane widths

Publications (2)

Publication Number Publication Date
TW200613973A TW200613973A (en) 2006-05-01
TWI340897B true TWI340897B (en) 2011-04-21

Family

ID=34987711

Family Applications (2)

Application Number Title Priority Date Filing Date
TW094106980A TWI340897B (en) 2004-03-08 2005-03-08 Memory hub architecture having programmable lane widths
TW100101847A TW201120644A (en) 2004-03-08 2005-03-08 Memory hub architecture having programmable lane widths

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW100101847A TW201120644A (en) 2004-03-08 2005-03-08 Memory hub architecture having programmable lane widths

Country Status (7)

Country Link
US (5) US7366864B2 (zh)
EP (1) EP1730640A4 (zh)
JP (1) JP2007528077A (zh)
KR (1) KR100872007B1 (zh)
CN (1) CN1930554A (zh)
TW (2) TWI340897B (zh)
WO (1) WO2005089126A2 (zh)

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EP1730640A4 (en) 2009-12-09
US8775764B2 (en) 2014-07-08
CN1930554A (zh) 2007-03-14
US20110296077A1 (en) 2011-12-01
WO2005089126A2 (en) 2005-09-29
US8015384B2 (en) 2011-09-06
WO2005089126A3 (en) 2006-07-27
US20140297974A1 (en) 2014-10-02
EP1730640A2 (en) 2006-12-13
TW200613973A (en) 2006-05-01
US7596675B2 (en) 2009-09-29
US9274991B2 (en) 2016-03-01
TW201120644A (en) 2011-06-16
KR20060130724A (ko) 2006-12-19
US20080162861A1 (en) 2008-07-03
KR100872007B1 (ko) 2008-12-05
US20090319750A1 (en) 2009-12-24
US7366864B2 (en) 2008-04-29
JP2007528077A (ja) 2007-10-04
US20050210216A1 (en) 2005-09-22

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