TWI335627B - Microelectronic assemblies having compliancy - Google Patents

Microelectronic assemblies having compliancy Download PDF

Info

Publication number
TWI335627B
TWI335627B TW095106342A TW95106342A TWI335627B TW I335627 B TWI335627 B TW I335627B TW 095106342 A TW095106342 A TW 095106342A TW 95106342 A TW95106342 A TW 95106342A TW I335627 B TWI335627 B TW I335627B
Authority
TW
Taiwan
Prior art keywords
conductive
microelectronic
assembly
compliant
compliant layer
Prior art date
Application number
TW095106342A
Other languages
English (en)
Other versions
TW200636878A (en
Inventor
Belgacem Haba
Original Assignee
Tessera Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera Inc filed Critical Tessera Inc
Publication of TW200636878A publication Critical patent/TW200636878A/zh
Application granted granted Critical
Publication of TWI335627B publication Critical patent/TWI335627B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2896—Testing of IC packages; Test features related to IC packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0236—Shape of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Description

^335627 九、發明說明： 【發明所屬之技術領域】 °更確切地說.，本 片封裝結構’以及 本發明關於晶圓級及半導體晶片封裝 發明關於改良式順應性晶圓及順應性晶 其製造與測試方法。 【先前技術】
微電子裝置微電子裝置例如半導體晶片者典型上 二與其他電子組件連接的輸人及輸“接線一= 其他可比較裝置的輸入及輸出接點通常配置在實質= 痃裝置之表面的柵格狀圖案（一 是 口未i飯％作”區域陣列”）中，屮 在與該裝置前表面之各緣平行 或 面中心上。典型地，例如像晶片這㈣置必須1 接 一例如像一印刷電路板這類基板上，且該裝置 接點必須電氣連接至該電路板的導電性裝置上 、 、，製造及將晶片安裝在—例如一電路板或其他電 化類外部基板上之期間，半導 咳曰千导體曰曰片通常提供於易於處理 口亥日日片的封裝中。例如，許多 ^ ^ , 牛導體日日片耠供於適合表面 女裝的封裝中。該一般型式 用。h U 式的许多封裝已提出多種的應 用最普遍地，這種封裝包括一 片载具"，其且有端子形“主 件’通常稱作"晶 Μ 成作為該介電層上的電鍍或蝕刻 金屬結構。這迪端子业形刹田乂丨1 μ 一 袖的1 /'㈣用例如像沿該晶片载具本身延 伸的溥跡線這類的裝置， 奸及錯由6玄曰日片接點與該等端子岑 跡線間延伸的細⑽或導線連接至該 -表面H # # 1 的接點。在 沒配置在一電路板，以便該封裝 I08989.doc 上功627 上的各端子與該電路板. M ^ ^ 對4的接觸墊對齊。焊接或 材科如供於該等端子及該等接觸墊之門兮 戈連接 埶哕蛐#扁廿 塾之間。该封裝能藉由加 熱-亥總成使其炼化或"重新 θ田加 料,CJ Μ 、人 動该钚錫，或活化該連接材 科，以便水久地連接於定位。 迂按材 許多封裝包括與該封裝端子附接 球形狀，典型直_约0丨^ 此谇塊具有焊 且“甘 1毫米及約〇.8毫米(5及3〇密爾)。— 撼^從其底部表面突出的焊球陣列的封裝通常稱作球形 ^列或BGA”封裝。這型式的封裝相當緊密。稱作凸 塊柵格陣列或"LGA"封#之苴仙壯 .,Λ +6 其他封裝利料錫所形成之薄 私驶”甘 杲二封裝，通常稱作"晶片尺寸 二、、所佔據電路板的面積等於或僅稿大於與該封裝 、。二之裝置面積。此優點在於其將降低該總成之整個尺寸 且容許該基板上多種裝置之間 連的使用，因而限制裝 置間W的傳播，且因此有助於該總成在高速時的操作。 ;包括封裝在内之總成能承受由差別熱膨脹以及該裝置與 该基板收縮所施加的應力。於操作期間，以及於製造期 間’一半導體晶片易膨脹與收縮一與一電路板膨服與收縮 不同的置>當該封裂的端子例如利用焊錫固定至該晶片或 其他裝置時，這些效應將使得該裝置相對於該電路板上的 接觸塾移動。這會施加應力在將該等端子連接至該電路板 ,之接觸墊的焊錫中。如第5,679,977號、第5，148,266號' 第5，148,265號、第5,455,390號及5,5 18,964號美國專利之 某較佳貫施例中揭露，其在此揭露藉為參考，半導體晶片 封裝可具有可相對於該晶片或與該封裝結合之其他裝置移 108989.doc 動的端子。此一務-Γ Μ 2 * 移動可將差叼膨脹及收縮補償至一可估計 程度。 封裝裝置的測4產生另—難以克服的問題。在—些製造 k転中。亥封裝裝置的端子與一測試夹具之間必須達成暫 =連接，且透過這些連接操作該裝置以確保該裝置功能健 ▲ L㊉k些暫時性連接必須達成但不能將該封裝端子 …H式ill具焊接。因此確保所有端子與該測試夾且的導 電元件可靠地連接在一起是重要的。然而，將該封裝壓在 例如一具有平面接觸塾的普通電路板這類的簡單測試夾具 以達成連接相當困難。如罢 ^ 如果邊封裝端子非共平面，或如果 έ亥測試夾具的導電元件非 电d干非八千面，一些端子將不能接觸直 在該測試夾具上的個別接觸塾。例如，在一遍封裂中， 與該等端子附接的焊球直徑 旦仏的差以及該晶片載具的非平面 性會使得一些焊球位於不同高度。 k-問題可透過具有補償非平面性的裝置配置之特殊結 構的測試夾具而減缓1而，這種裝置增加該測試夾具的 成本且在某些情形中將一此 _ —小J罪性引入該測試夾具本 身。這特別是不想要的，因為哕丨 巧β测或夾具本身及具有該測
試夾具的裝置的接合必須比該封F 町及罝本身更為可靠，以便 提供-有意義的測試。再者’想要高頻操作的裝置血型必 須藉由施加高頻信號職。^求在該測試夹具的信號路 位的電氣特徵上產生限制，進 退而使付该測試夾具結構變得 複雜。 此外’當測試晶圓及封裝具有與端子連接的焊球時，焊 J089S9.doc 錫將累積在與該焊球接人. 餘物的累積合％ “、必/、部分上。這些焊錫殘 累積會⑽该測試夾具的壽命及減弱1可靠声 針“述問題進行處理。前述專利中所 -封相對該微電子裝置移動的端子 -移動在測試期間能補償該等端子非平面性的一此尺产 :專利揭露一BGA型的方法，其中該晶片面上的凸塊引線 板上之杯狀插座巾且利用-低熔點材料焊接於 ^中。頒與B_an等人的第4,975，G79號美國專利揭露— 片測„式插座’其中遠測試基板的圓頂形接點配置於圓錐 形導件内。該晶片被塵抵於該基板，以便該焊球進入該圓 錐形導件且與該基板上的圓頂形插銷接合。施加充分的力 以便該圓頂形插銷確實地改變該晶片焊球的形狀。 一 BGA插座的另一範例可在1998年9月8日頒證之共同讓 與的第5,8〇2,699號美國專利中發現，其在此揭露藉為參 考。該'699專利揭露一具有複數個孔的薄片形連接器。各 孔具備在一孔上向内延伸之至少一彈性層疊接點。_ bga 裝·置的凸塊引線進入g玄專孔内’以便該凸塊引線與該等接 點接合。該總成可被測試，且如果發現可接受，該等凸塊 引線可永久地焊接至該等接點。 2001年3月20日頒證之共同讓與的第6,202,297號美國專 利揭露一具有凸塊引線之微電子裝置的連接器以及該連接 器的製造與使用方法。在該，297專利的一實施例中，—介 電性基板具有一從一前表面向上延伸之複數個柱件β該等 I08989.doc ⑶ 5627 =件可配置於—柱件組的㈣中·，其中各柱件組在其間界 疋二隙。一概呈層疊接點從各柱件頂部延伸。為測試一 裝置，s亥裝置的凸塊引線各別插入一個別空隙中，藉此接 。《等接點，當其繼續插人時，該等接點纏繞該等凸塊引 =一！地，6亥等接點的遠端部分朝該基板向下偏移，且 當該凸塊引線插入一空隙時從該空隙中心向外移動。 共同讓與之第6,1 77,636號美國專利揭露一在一微電子裝 置與一支撐基板之間提供互連的方法及裝置。在該，㈣專 1 ,實施例中，-微電子裝置之互連組件的製造方法包 括提供-具有第一與第二表面且將—導電薄片連結至該晶 片載具之第一表面的可挽晶片載具。該導電薄片被選擇性 ^虫刻’以產生複數個實質上堅硬的枝件。一順應層提供 =支揮基板的第二表面上且—例如—半導體晶片的微電 ^裝置與該順應層接合’以便該順應層位於該微電子裝置 從°玄日曰片載具之曝露表面突出的 八：。該等柱件電氣連接微電子袭置。該等柱件形成可接 2-插座或坪接至-基板’作為—例如電路面板之裝置 的犬出封裝端子。當該裝置使用時，因為該 .： 該微電子裝置移動，此—封裝實f 鲛 D目對 貝上D周即該裝置與— 基板間不當匹配的熱膨脹係數。 牙 平面或接近共平面。 再t㈣柱件尖端可共 除上述所有技術發展以外，晶圓與 測試的進—步改良將是吾人想要的。"、裝之製造與 【發明内容】 I08989.doc 在本發明之某些較佳· , α 奴佳貫轭例中，一微電子總成包括一微 電子7L件，例如—丰遒 牛導體日日圓或晶片，其具有一第一表面 ，、可在該第一表面k 兮他♦. 面存取之接點。該總成較佳為包括一位於 ϋ亥Φά電子元件之第一主 一表面的順應層，該順應層較佳地具有 ==元件之接點實質對齊的開口。-介電性純化層 成_土微電子元件之第-表面與該順應層之間。該總 —主 且覆於该順應層上且從該微電子元件之第 一表面突出的導電桎，择 ^ Φ ^ 耜此6亥荨導電柱係與該微電子元件 们接點電乳互連。去 田。Χ電柱的尖端臨接至例如像一測試 電路板或印刷電路板 <導電接觸塾這類的導電塾時，該 寺導電柱的尖端能相 谪 U電子兀件上的接點移動，以 逋應於非平面性。 在某些較佳實施例φ ^ 5亥順應層較佳由一具有一低彈性 奄 …層可由例如聚矽氧、彈性樹脂、 t醯亞fe、熱固性臂人札 # * σ物、氟聚合物及熱塑性聚合物這類 材枓製成。在另—較伟杳 ^ ^ ^ 貫施例中，該順應層可具有一例如 像一平坦頂部表面這類 ^ ΤΙ ^ _ . °P表面，及一延伸於該順應層 之頂。卩表面與該微電子 傾斜表ΜΜ 件的第—表面間的傾斜表面。該 丨只针表面可包括至少一 斜夺面勺4… 特別較佳實施例中，該傾 ，表面匕括一從該微電子 .w 件之第一表面延伸的第一曲面 及一仗该順應層之頂部矣 ® ^ 丨表面延伸的第二曲面。 5亥微電子總成較佳兔& ^ 的接點電冑該等導電柱及該微電子元件 =Γ 長形導電元件。該長形導電元件可包括 例如像銅、金、錦與合金'其愿合物及組合物這類材料括 108989.doc 川 5627 在某些實施例中’該長形導，元件可連接帶或導電跡線。 该長形導電元件較佳地延伸於該順應層上。
在本發明之某些較佳實施例中，該順應層包括複數個位 於該微電子兀件之第一表面上的順應凸塊。該等導電柱之 至少-者可配置在該等順應凸塊之至少一者上方。在其他 較佳實施财，各導電柱配置在該等順應凸塊之—者上 方。在又-其他實施例中，二或多個導電柱可配置在—單 —順應凸塊上方。各導電柱較佳具有—與該順應層僅鄰的 底座及-距離該順應層遠端的尖端。該等導電柱較佳且有 —高於該焊接遮罩厚度的高度，因此該等柱件係該微電子 總成上最高/最頂部的結構。最後，在該微電子總成的測 式期間°亥等導電柱的尖端係與一測試板上之導電接觸塾 接合的第一元件。在某些較佳實施例中，該等導電柱較佳 具有一約50-300微米的高度。在某些較佳實施例中，該等 導電柱之至少―者具有—截頭圓錐形狀，此形狀具有一 :〇〇 _微米直徑的底座及一約4〇 2〇〇微米直徑的尖端。該 等導電柱可由例如銅、銅合金、金及其組合物 料製成》 在本七明之其他較佳實施例中，一微電子總成包括一微 -一件例如一半導體晶圓或晶片，其具有一第一矣面 與：亡該第-表面存取之接點的，及—位於該微電子元件 第表面上的順應層，該順應層具有—與該微電子元件 之第-表面間隔的頂部表面。該總成較佳為另外包括疊覆 於4微電子7L件之頂部表面上且從該微電子元件之第一表 108989.doc 1335627 面突出的導電柱，以及將該等導電柱與該微電子元件之接 點電氣互連的長形導電元件。 1該順應層可包含複數個順應凸塊，其中各導電柱配置在 . 4等導電凸塊之—者的上方。該順應層較佳具有與該微電 元件之接點對齊的開口，該等開口界定從該微電子元件 第表面延伸至该順應層之頂部表面的順應層傾斜表 面。該等導電元件較佳位於該順應層的傾斜表面上。 • 在本發明之又一實施例中，一微電子總成包括一具有— 第一表面與可在該第一表面存取之接點的微電子元件，及 位於該微電子元件之第一表面上的複數個順應凸塊，該等 ' 順應凸塊各別與該微電子元件之其中-接點緊鄰配置。該 總成較佳包括疊覆於該微電子元件上且從該微電子元件之 第表面突出的導電柱，以及將該等導電柱與該微電子元件 之接點電氣互連的導電跡線，藉此該等順應凸塊致使該等 導電柱相對該微電子元件的接點移動。 • 該等順應凸塊較佳具有與該微電子元件之第一表面間隔 的頂部表面，以及延伸於該等順應凸塊之頂部表面與該微 • 電子元件之第一表面間的傾斜表面。該等導電跡線較佳為 延伸於該等順應凸塊之傾斜表面的上方。 本發明之這些及其他較佳實施例將進—步說明如下。 【實施方式】 圖1A-1D說明一用於產生順應微電子總成之製程的截面 側視圖’該總成具有導電柱或插銷與之電氣互連。 圖1A顯示一具有複數個晶粒或晶片之半導體晶圓2 〇。該 108989.doc -12- 1335627 二圓具有一第一面或接點轉面22 1中-或多個接點24 可在該第一面22存取。力士祕姐# ^ M 24 η 纟此所揭露之製程期間，該晶圓可 在任何位置單獨製成個別晶片封 ® , 在其他I父佳實施例 中，该晶圓20可由一單一微電子 ,,, 乃朁換。—介電鈍化層 声積或㈣在該晶_的接點支承㈣。該純 化層可為-通常在半導體晶片之接點支承表面所發現的
Sl02純化層。在另一較佳實施例中，一個別的介電鈍化層 可使用例如一環氧樹脂、聚醯亞胺、可光成像介電質等這 類材料。當使用該個別純化層時’該鈍化層可旋轉建立在 該表平面上之-平面薄片形式或該介電薄片可利用任何眾 所皆知或習於此技者所使用的電子等級的黏著劑疊製在該 表平面。該鈍化層較佳地覆蓋該晶圓的接點支承面“且留 下曝露的接點24 ’則更一例如像一長形連接帶的㈣元件 可在一後續步驟中電鍍其上，如下所述。 參考圖1B，一順應層26沉積或層疊在該鈍化層的曝露表 面（未顯示）上。該順應層可形成及/或具有一在共同讓與之 第 6,211，572 |虎、第 6,284,563 |、第 M65,878 號、第 6,847，101號、第6,847，1〇7號美國專利，以及同在申請中之 美國專利申請案〇9/〇20,647及10/873,883號中揭露的形狀， 其在此揭露藉為參考。[TESSErA案第〇78行]該順應層26 可利用一可凝固液體模印、屏蔽或轉移模塑在一鈍化層 上’當凝固時該可凝固液體黏著至該鈍化層。或者，該順 應層2 6可利用一電子等級的黏著劑，以凝固順應接觸墊形 式點著至該鈍化層表面。該順應層較佳具有一實質平坦的 108989.doc 山 5627 頂部表面28及一位於該晶圓2〇之接點支承面22與該順應層 之頂部表面28之間的逐漸傾斜轉移表面30。該傾斜轉移表 面30可依循該接點之承面26與該實質平坦頂部表面28之間 . 的一曲線或可簡單地以一角度傾斜，使得該傾斜表面3〇相 對该接點支承表面22及該實質平坦表面28處於—不太垂直 的方位。该順應層26可由多種材料形成，例如一低彈性係 數材料。該順應層也可由聚合材料或其他例如像矽、彈性 • 樹脂、聚醯亞胺及其他熱固性聚合物、氟聚合物，及熱塑性 聚合物材料製成。 一電鍍籽晶層（未顯示）可沉積在前述總成上。該籽晶層 - 彳利用一減射操作沉積。冑㉟電鑛基層材料包括纪（用於 -· '，，、電極式電鍵）、鈦、嫣鎳及鉻。然而，在其他較佳實施 例中’主要使用銅籽晶層。 # *考圖1 C，一光阻劑（未顯示）可施加至該順應層26的曝 2頂。卩表面，且接著經曝露及生長以致形成長形導電連接 • ^跡線32，藉以形成導電接觸塾。該導電接觸連接帶較 彳將接近轉電帶32之第—端的晶片接點與接近該導電連 . ❹32H的端子34互連1連接帶可直接地電鐘至 • ^等接點24。較佳的連接帶材料包括銅、金、鎳及合金、 其混合物及組合物。 參考圖1 D，— Ίνί ^ 〇 遮罩層36可沉積或層疊在該總成頂部上， 以便僅有該等端子34被曝露。該遮罩層可為一介電材料。 該焊接遮罩可內合 θ ^ —屏敝、曝露及生長或層疊薄片、一 阻材料，或可句人 3 —對.二甲苯環氧樹脂、聚醯亞胺樹脂' 108989.doc ll聚合物等，這些材料可配翼或層疊在該總成上。 參考圖1D，導電柱或插銷38形成於各導電端子“上。該 導電柱或插銷可被電錢或沉積，以便其在半導體晶圓20^ 接點支承面22上方突出。在某些較佳實施例中，各導電柱 3 8車乂佳連接至導電跡線32的端子端…該等柱件尺寸可在 ^有效範圍内改變。在某些較佳實施例中，該等柱具有一 又P同於力50-300微米之順應層26的頂部表面28。各柱 具有緊鄰該順應層之底座4〇及一距離該順應層遠端的尖 立而42。該等導電柱38可由任何導電材料形成，但想要的 話，、其可從例如像銅、銅合金、金及其組合物的金屬材料 製成。例如，該等導雪知：3 β ιθ + 寻导電柱38可由具有—提供在該等柱件38 表面的金層44的銅形成。 在某些實施例中，傳統例如電鑛製程可形成該等導電跡 線且該等導電柱可㈣共同讓與之第6，177,636號美國專利 中所揭露方法形成’其在此揭露藉為參考。在又一較佳實 施例中’成等導電柱可以任何適合方式將該等導電柱連接 至該等導電跡線3 2的端早护，於 而作為個別元件或組裝成該微 電子總成。在又一較佳管姑点,丨士 ,、, 往賞施例中，該總成可藉由沉積一籽 晶層、電鐘具有與該微電子元件之接點連接的第-端及配 置在該順應層上方的第二端的導電跡線、電鍍位於該順應 層上方且與該等導電跡線接觸的導電柱，及移除該籽晶 層。該總成也可將該等導電柱以無電極式電鑛形成。該等 導電柱可利用銅或錄㈣電鐘該等柱件形成。 參考圖2’在本發明其他較佳實施例中，一微電子總成 108989.doc ⑴ 5627
包括一具有晶片接點124之锋點支承面122的半導體晶片 120。-順應層126之-或多個凸塊形成於該半導體晶片 12〇之接電支承面122上方。在某些較佳實施例中，一或多 個順應凸塊126可包括-實質平坦㈣部表面128及一在該 半導體晶片！20之頂部表面128與該接點支承面122之間過 渡的傾斜表面13〇。一或多個導電連接帶132形成於該總成 上方°各導電連接帶132具有—與該接點124電氣互連的第 一端及一位於該順應凸塊126之實質上平坦頂部表面128上 的第二端子端134。-遮罩層136可提供於該半導體次總成 之頂部上。該遮罩層136包括開口⑺。該等導電跡線132 的端子端134透過該等開口 137曝露…或多個導電柱138 形成在邊次總成上。各導電柱138較佳與該導電跡線Η〗的 端子端134電氣互連。該等導電柱可利用一金層144覆蓋。 參考圖3 A，圖1D的微電子總成可利用一例如一印刷電 路板這類具有導電墊52的基板5〇測試。圖3A及3B所示之 微電子總成為求清蜥而簡化。該微電子總成包括具有一第 -面22的晶圓20及位於該晶圓2〇之第一面22上的順應層 26導電柱38從該順應層26的頂部表面28突出。該等導電 柱3 8與該晶圓2〇上的接點呈電氣互連。 參考圖3A及3B，為測試該微電子總成，該等導電柱38 的尖端42與該電路化基板5〇的導電㈣並列配置。如圖邛 所Γ 2等導餘的尖端壓抵於該等導電墊。該順應層％ 吏亥等V电柱的尖端相對於該晶圓上的接點移動，以調節 β等柱件與該等導電墊間的非平面性，以及不當的熱匹 108989.doc 1335627 配。如果該微電子總成的測第成功，該總成可例如利用焊 接或另一可熔接或導電材料永久地附接至一例如像一印刷 電路板的基板。 參考圖4A，圖2的微電子總成可利用一例如一測試板這 類具有導電墊1 52的基板1 50測試。圖4 A及4B中所示之微 電子總成的表示法為說明起見已加以簡化。該微電子總成 包括具有一第一面122的晶圓120及疊覆於該晶圓12〇之第 一面122上的順應凸塊126。導電柱138從該順應凸塊126的 頂部表面128突出。該等導電柱138藉由導電跡線132與該 晶圓120上的接點124電氣互連。該等導電跡線較佳位於該 等順應凸塊上。該等導電跡線較佳與該等順應凸塊接觸。 在某些較佳實施例中，料導電跡線與該等順應凸塊接觸 且位於該等順應凸塊之傾斜邊緣的上方。該等導電柱的尖 端較佳為該導電柱的最高部分，以便料尖端為該總成^ 第一部分，以便接合該測試板上的導電墊。該等導電柱可 為任何高度’只要該高度高於形成在該順應層或順應凸塊 上方：焊接遮罩’及/或只要該等柱件的尖端界定該總成 mu最m作期間’該等導電柱的尖端可直 接與-測試板上的導電墊接合，而不需例如焊接或 結件/橋接件等額外的材料。 一 參考圖4A及4B ’為測試該微電子總成，該等導電柱I% 的尖端142與該電路基板15〇 蟄152並列配置。如圖 斤二’該等導電柱】38的尖端壓抵於該等導電塾152，以 形成该微電子總成與該基板} 间的電乳互連。該等順 108989.doc 1335627 應凸塊〗26使該等導電柱〗38相對於該晶圓i2〇上之接點i24 移動，以調節該測試基板上之該等柱件】38與接觸墊〗“間 的非平面性，以及不當的熱匹配。如果該微電子總成的測 試成功’該總成可利用坪接或另一可熔接或導電材料永久 地附接至一例如像一印刷電路板的基板。 參考圖5’在本發明之某㈣佳實施射，該等導電柱 238可大致呈截頭圓錐形狀’藉此該底座24〇及各柱件238 的尖端242實質上呈圓形。在這些特別較佳實施例中’該 等柱件的底座240典型具有觀_微米的直徑，然而該 等尖端242典型具有約4〇摘微米的直徑。該等導電柱的 Μ表面可選擇性以—例如像金、侧、金/餓或金/㈣ 類间度導電層電鑛，或者以—例如餓之防磨導電塗層電 在該等柱件焊接或插置一基板時確保達成-良好的 在本發明之某些較佳實施例中，該等柱件可具有 “員斜移動的形狀’當該尖端與該接觸墊接合時，使各柱 端沿—相反接觸塾抹拭。此傾斜移動提升可靠的電 汽插们如肅年U月1G日所提出標題為"具抹拭動作的 =鎖柵格陣列，，同在申請中且共同讓與的美國專利” 等二，η6號中的詳細討論’其在此揭露藉為參考，二 具備提升此一抹拭動作且另外易於該等才主件與接 良好電=性。具有其他形狀的導電柱及提升抹拭及/或 為"1掠::：的設計係在2004年11月10曰所提出標題 』勒移動隔離的微插銷栅格陣列”同 '08989.doc 1335627 讓與的美國專利申請案10/985，119號以及在2〇〇4年〗2月μ 日所提出標題為”微電子封裝及其方法”同在申請中的美國 專利申請案H/01M39號中的詳細討論，其在此揭露藉 參考。 在本發明之某些較佳實施例中，一種例如第4,8〇4，132號 及第5,083,697號美國專利中所揭露的粒子塗層可提供在— ^電子封裝的-或多個導電部分上，以便加強微電子元件 ^間電氣互連的形成’以及有助於微電子封裝的測試。該 分子塗層較佳提供在例如像導電端子或導電柱之尖端這類 的導電部分上。在一特別較佳實施例中，該分子塗層係一 金屬化菱形結晶塗層’其利用標準光阻技術選擇性地電鍍 至—微電子元件的導電部分。在操作中’一具有菱形結晶 塗層可壓在一相反接觸塾上’以便穿透該接觸墊之外表面 所呈現的氧化層。除傳統的抹拭動作以外，該菱形結晶塗 層透過氧化層的穿透有助於可靠電氣互連的形成。 泫4柱件也可藉由一例如在2 0 0 4年1 〇月6日所提出標題 為”具裝置高度修正之電路形成"同在申請中且共同讓與的 吳國㈣申請案_9,465號中所揭露的製程製造其在 此揭露藉為參考。 雖然=發明不受任何特別操作定理所限制，但是相信本 文:揭路提供導電柱在—順應材料上將提供一順應晶圓級 或晶片封裝，传盆f岡誌T A u 八p不s的熱匹配以及確保適當電氣互 成。在操作令’導電插銷或柱件的使用直接地將該 等導電柱的尖端鄭彡立热_ , ；/則成板上的接點，使得該微電子 108989.doc 1335627 總成及/或晶圓接香消丨q · 雖-本幸：不使用1試插座。 …'本案如供一在此所說明之微電子 Μ ϋ m ^ ^ ^ μ & -τ , 〜成及日日圓的特别 在順序可改變且仍在本發明範圍内。 /、二較佳貫施例中，本文所揭露 曰士 路〈結構可用以製诰一 /、 一順應層之測試板及從該順應層突出之導電柱。— 晶圓或晶粒上的接點可鄰接於該等導電柱的 ^裸 試該晶圓或晶粒。 測 雖然本發明已參考特別實施例加以說明，但必須瞭解， 这些貫施例僅作本發明原理及應用的說明。可以瞭解的 疋’终多修改可從說明實施例得到且其他配置可設置，作 不能偏離本發明之文料求項㈣義之料及_。— 本發明具有微電子工業上之實用性。 【圖式簡單說明】 圖以係一具有一或多個接點之微電子元件的截面圖。 之微電子元件在—順應層形成在該微電子 元件之接點支承表面上之後的截面圖。 圖1 C·係圖1B所示之微雷早-合她士、士 倣％千·人總成在長形導電跡線形成 在該順應層上之後的截面圖。 圖1D係圖1(：所示之微電子次總成在導電柱或插鎖形成 在圖1 C所示之順應層上之後的截面圖。 圖2顯示-根據本發明另—較佳實施例之微電子總成的 截面圖。 圖3A及3B顯不一測試圖1D之微電子總成的方法 圖4A及4B顯示一測試圖2之微電子總成的方法。 108989.doc -20· 1335627 圖5顯示一根據本發明另一較佳實施例之微電子總成的 截面圖。 【主要元件符號說明】
20 晶圓 22、 122 接點支承面 24 接點 26 順應層 28、 128 頂部表面 30 傾斜轉移表面 32、 132 導電連接帶或跡線 34 端子 36 遮罩層 38 ' 138 、 238 導電柱 40 ' 240 底座 42 ' 142 、 242 尖端 44、 144 金層 50、 150 基板 52、 152 導電墊 120 半導體晶片 124 晶片接點 126 順應凸塊 130 傾斜表面 134 第二端子端 137 開口 108989.doc 21

Claims (1)

1335627 公告本I 第095106342號專利申請案 中文申凊專利範圍替換本(99年6月） 十、申請專利範圍： 1' 一種微電子總成，包含： -微電子元件，其具有一第一表面及可在該第一表面 存取之接點； 一順應層’其疊覆於該微電子元件之該第—表面上； ‘電跡線’其位於該順應層H部表面，該等跡線 與該等接點連接； =電柱’其疊覆於該順應層上且從該等導電跡線突出 而m離’其中該等導電柱與該微電子元件㈣等接點 性連接， ‘ …其中該順應層具有—平坦頂部表面及—傾斜表面，且 及等導電柱在該頂部表面±突出5G•微米的—高度。 2.如請求項丨之總成，其 又 T $ 4導$柱具有界定該總成上 之最尚點的尖端。 3 ·如請求項1之總成，其中哕順旛恩θ 士 中該順應層具有與該微電子元件 之5亥等接點對齊的開〇。 4·=項3之總成’其中該等導電跡線通過該順應層中 =:以將該等導電柱與該微電子元件之該等接點電 5·如請求項1之總成，其中該微電子元件係-半導雕曰 圓。 卞V to日日 6·=請求項i之總成，其中該微電子元件係_半導體晶 7·如請求们之總成，尚包含一配置在該微電子元件之第 I08989-990628.doc 1335627 表面與該順應層之間的介電鈍化層。 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 0月求項1之總成，其中該順應層包一 、 係數的材料。 ，、有-低彈性 如：求項1之總成，其中該順應層包含一介電材料。 如明求項1之總成’其中該順應層包含一從矽 2聚酸亞胺、熱固性聚合物、氣聚合物、熱塑性聚人 物等该組材料中所選出之材料β σ ，請求们之總成’其中該順應層的該傾斜表面延伸於 二順應層之該頂部表面與該微電子元件之該第—表面 如：求項11之總成’其中該傾斜表面包括至少一曲面。 ^求項12之總成，其中該至少—曲面包括—從該微電 子元件之第一表面延伸的曲面。 月长員12之U，其中該至少一曲面包括一從該順應 層之頂部表面延伸的曲面。 如。月求項1之總成’其中該等導電跡線包含從銅、金及 鎳等該組材料所選出的材料之至少之一者。 如1求項1之總成，其中該順應層包含複數個位於該微 電子7L件之第一表面上的順應凸塊，及其中該等導電柱 之至少一者配置在該等順應凸塊之至少一者上方。 如》月求項16之總成’其巾t亥等導電柱配置在該等順應凸 塊上方。 如印求項1之總成，其中各該等導電柱具有一與該順應 g緊郴之底座及一遠離該順應層的尖端。 108989-990628.doc 1·9. 20. 21. 22. 23. 24. 25. 如請求項18之總成’其中該等導電柱之至少—者具有〜 戴頭圓錐形狀，此形狀具有一1〇〇__微米直徑的該底： 及一 40-200微米直徑的該尖端。 —点 如請求項1之總成，其中該等導電柱包含-導電材料。 如請求们中該料電柱包含從銅、鋼a 金、金及其組合物等該組材料中所選出之材料。 —種微電子總成，包含： 一微電子元件’其具有-第—表面及可在該第 存取之接點； 表面 -順應層’其疊覆於該微電子元件之該第一表面上 該順應層具有-與該微電子元件之第—表面間隔的_ 表面； | 導電柱’其疊覆於該順應層之頂部表面上且從該微電 子元件之第一表面突出； 电 兩長形導電元件，其位於該等導電柱下方，及將該等導 電柱與該微電子元件之該等接點電氣互連； 士其中該順應層具有一平坦頂部表面及一傾斜表面，及 该等導電柱在該頂部表面上突出50·300微米的一高度。 如請求項22之總成，其中該微電子元件係一半導體晶 圓。 如請求項22之總成’其中該微電子元件係一半導體晶 片。 如請求項22之總成，其中該順應層包含複數個順應凸塊 且各該導電柱配置在該等凸塊之一者的上方。 108989-990628.doc 1335627 26. 27. 28. 29. 士明求項22之總成，其中該順應層具有與該微電子元件 之5亥等接點對齊的開口，該等開口界定該順應層的傾斜 表面，此傾斜表面從該微電子元件之第一表面延伸至該 順應層的頂部表面，其中該等長形導電元件位於該順應 層的傾斜表面上。 一種微電子總成，包含： 微電子元件，其具有一第一表面及可在該第一表面 存取之接點； 複數個順應凸塊’其疊覆於該微電子元件之該第一表 面上’各該順應凸塊配置於緊鄰該微電子元件之該等接 點； 經飯刻的導電柱’其疊覆於該微電子元件上且從該微 電子元件的第一表面突出； 導電跡線’其將該等導電柱與該微電子元件之該等接 點電氣互連，其中該等順應凸塊致使該等導電柱相對於 該微電子元件之該等接點移動， 其中該等複數個順應凸塊的至少之一者具有—平±旦τ 頁 部表面及一傾斜表面，及該等導電柱之一者在該頂部表 面上突出50-300微米的一高度。 如請求項27之總成，其中該等順應凸塊具有與該微電子 元件之第一表面間隔的頂部表面及在該等順應凸塊 部表面與該微電子元件之第一表面間延伸的傾斜表面。 如呀求項2 8之總成’其中該等導電跡線延伸於該等顺鹿 凸塊的傾斜表面上。 108989-990628.doc 3,0 •一種微電子總成，包含： . —微電子元件，其具有一第一表面及可在該第— 存取之接點； 面 一順應層，且右· __故 * ^ ^ 八’、有第一表面，其面向該微電子开 之該第一表面，及一黛-矣 夂弟一表面’其面向遠離該微電子_ 件的該第—表面；導電跡線，其沿著該順應層的該^ 表面延伸，該等跡線與該等接點連接； _導電柱’其疊覆於該順應層上方，在該順應層的該第 :表面上突出至少5〇微米的一高度，及從該等導電跡線 突出而遠離，其中該等導電柱與該微電子元件的 技 點電性連接。 3l·—種微電子總成，包含： 一微電子元件，其具有-第-表面及可在該第-表面 存取之接點； -順應層’具有一第一表面面向該微電子元件的該第 表面，及一第二表面面向遠離該微電子元件的該第一 表面； 導電柱，其疊覆於該順應層之頂部表面上，在該順應 層的該第二表面上突出至少5〇微米的一高度，且從該微 電子元件之該第一表面突出而遠離； 長形導電兀件，其位於該等導電柱下方，且將該等導 電柱與該微電子元件之該等接點電性連接。 3 2 · —種微電子總成，包含： 面及可在該第一表面 一微電子元件’其具有—第一表 108989-990628.doc 1335627 存取之接點； 複數個順應凸塊，其每一者具有一第一表面面向該微 電子元件的該第一表面，及一第二表面面向遠離該微電 子元件的該第一表面； 經蝕刻的導電柱，其疊覆並在該等順應凸塊的該等第 二表面上突出至少50微米的一高度，該等導電柱從該等 微電子元件的該第一表面突出而遠離； 導電跡線，其將該等導電柱及該微電子元件的該等接 點電性連接，其中該等順應凸塊使該等導電柱能夠相對 於該微電子元件的該等接點移動。 108989-990628.doc
TW095106342A 2005-02-25 2006-02-24 Microelectronic assemblies having compliancy TWI335627B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US65648005P 2005-02-25 2005-02-25

Publications (2)

Publication Number Publication Date
TW200636878A TW200636878A (en) 2006-10-16
TWI335627B true TWI335627B (en) 2011-01-01

Family

ID=36570325

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095106342A TWI335627B (en) 2005-02-25 2006-02-24 Microelectronic assemblies having compliancy

Country Status (7)

Country Link
US (2) US7999379B2 (zh)
EP (1) EP1851798B1 (zh)
JP (2) JP5593018B2 (zh)
KR (2) KR101267651B1 (zh)
CN (1) CN101128931B (zh)
TW (1) TWI335627B (zh)
WO (1) WO2006091793A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7999379B2 (en) 2005-02-25 2011-08-16 Tessera, Inc. Microelectronic assemblies having compliancy
US7749886B2 (en) * 2006-12-20 2010-07-06 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
DE102008042107A1 (de) * 2008-09-15 2010-03-18 Robert Bosch Gmbh Elektronisches Bauteil sowie Verfahren zu seiner Herstellung
JP6006523B2 (ja) * 2012-04-27 2016-10-12 新光電気工業株式会社 接続構造体、配線基板ユニット、電子回路部品ユニット、及び電子装置
US9437911B1 (en) * 2015-05-21 2016-09-06 Harris Corporation Compliant high speed interconnects
US20160343646A1 (en) * 2015-05-21 2016-11-24 Qualcomm Incorporated High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) package
KR101678162B1 (ko) * 2015-07-01 2016-11-21 서울대학교산학협력단 유연성 소자용 접속 구조물 및 이의 제조 방법
US9704818B1 (en) * 2016-07-06 2017-07-11 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US10103114B2 (en) 2016-09-21 2018-10-16 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US11749616B2 (en) 2017-10-05 2023-09-05 Texas Instruments Incorporated Industrial chip scale package for microelectronic device
TWI645527B (zh) * 2018-03-06 2018-12-21 矽品精密工業股份有限公司 電子封裝件及其製法

Family Cites Families (142)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001870A (en) 1972-08-18 1977-01-04 Hitachi, Ltd. Isolating protective film for semiconductor devices and method for making the same
GB1487945A (en) 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
JPS5321771A (en) 1976-08-11 1978-02-28 Sharp Kk Electronic parts mounting structure
US4300153A (en) 1977-09-22 1981-11-10 Sharp Kabushiki Kaisha Flat shaped semiconductor encapsulation
US4284563A (en) 1978-02-08 1981-08-18 Research Corporation 9,10,11,12,12-Pentachloro 4,6-dioxa-5-thia-1-aza-tricyclo[7.2.1.02,8 ]d
JPS5519850A (en) 1978-07-31 1980-02-12 Hitachi Ltd Semiconductor
US4381602A (en) 1980-12-29 1983-05-03 Honeywell Information Systems Inc. Method of mounting an I.C. chip on a substrate
US4396936A (en) 1980-12-29 1983-08-02 Honeywell Information Systems, Inc. Integrated circuit chip package with improved cooling means
JPS601846A (ja) 1983-06-18 1985-01-08 Toshiba Corp 多層配線構造の半導体装置とその製造方法
US5310699A (en) 1984-08-28 1994-05-10 Sharp Kabushiki Kaisha Method of manufacturing a bump electrode
US4642889A (en) 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor
US4671849A (en) 1985-05-06 1987-06-09 International Business Machines Corporation Method for control of etch profile
US6043563A (en) 1997-05-06 2000-03-28 Formfactor, Inc. Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
US4902606A (en) 1985-12-20 1990-02-20 Hughes Aircraft Company Compressive pedestal for microminiature connections
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
US5302550A (en) 1985-12-24 1994-04-12 Mitsubishi Denki Kabushiki Kaisha Method of bonding a microelectronic device
US4977441A (en) 1985-12-25 1990-12-11 Hitachi, Ltd. Semiconductor device and tape carrier
US4885126A (en) 1986-10-17 1989-12-05 Polonio John D Interconnection mechanisms for electronic components
US4813129A (en) 1987-06-19 1989-03-21 Hewlett-Packard Company Interconnect structure for PC boards and integrated circuits
JPH01129431A (ja) 1987-11-16 1989-05-22 Sharp Corp 半導体チップ実装方式
US4783594A (en) 1987-11-20 1988-11-08 Santa Barbara Research Center Reticular detector array
JPH0715087B2 (ja) 1988-07-21 1995-02-22 リンテック株式会社 粘接着テープおよびその使用方法
US5001542A (en) 1988-12-05 1991-03-19 Hitachi Chemical Company Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips
US4962985A (en) 1989-10-02 1990-10-16 At&T Bell Laboratories Protective coatings for optical devices comprising Langmuir-Blodgett films
US5082811A (en) 1990-02-28 1992-01-21 E. I. Du Pont De Nemours And Company Ceramic dielectric compositions and method for enhancing dielectric properties
US5656862A (en) 1990-03-14 1997-08-12 International Business Machines Corporation Solder interconnection structure
US5070297A (en) 1990-06-04 1991-12-03 Texas Instruments Incorporated Full wafer integrated circuit testing device
US5187020A (en) 1990-07-31 1993-02-16 Texas Instruments Incorporated Compliant contact pad
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5072520A (en) 1990-10-23 1991-12-17 Rogers Corporation Method of manufacturing an interconnect device having coplanar contact bumps
US5140404A (en) 1990-10-24 1992-08-18 Micron Technology, Inc. Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
US5180311A (en) 1991-01-22 1993-01-19 Hughes Aircraft Company Resilient interconnection bridge
JP2593965B2 (ja) 1991-01-29 1997-03-26 三菱電機株式会社 半導体装置
US5265329A (en) 1991-06-12 1993-11-30 Amp Incorporated Fiber-filled elastomeric connector attachment method and product
US5225966A (en) 1991-07-24 1993-07-06 At&T Bell Laboratories Conductive adhesive film techniques
US5316788A (en) 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5194930A (en) 1991-09-16 1993-03-16 International Business Machines Dielectric composition and solder interconnection structure for its use
JP2927081B2 (ja) 1991-10-30 1999-07-28 株式会社デンソー 樹脂封止型半導体装置
JPH05175280A (ja) 1991-12-20 1993-07-13 Rohm Co Ltd 半導体装置の実装構造および実装方法
US5203076A (en) 1991-12-23 1993-04-20 Motorola, Inc. Vacuum infiltration of underfill material for flip-chip devices
US5249101A (en) 1992-07-06 1993-09-28 International Business Machines Corporation Chip carrier with protective coating for circuitized surface
WO1994003036A1 (en) 1992-07-24 1994-02-03 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US5371404A (en) 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5414298A (en) 1993-03-26 1995-05-09 Tessera, Inc. Semiconductor chip assemblies and components with pressure contact
JP3269171B2 (ja) 1993-04-08 2002-03-25 セイコーエプソン株式会社 半導体装置およびそれを有した時計
US5355283A (en) 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5600103A (en) * 1993-04-16 1997-02-04 Kabushiki Kaisha Toshiba Circuit devices and fabrication method of the same
JP3445641B2 (ja) 1993-07-30 2003-09-08 株式会社デンソー 半導体装置
US6326678B1 (en) 1993-09-03 2001-12-04 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US5477611A (en) 1993-09-20 1995-12-26 Tessera, Inc. Method of forming interface between die and chip carrier
JP3214186B2 (ja) 1993-10-07 2001-10-02 三菱電機株式会社 半導体装置の製造方法
JPH07115096A (ja) 1993-10-18 1995-05-02 Fujitsu Ltd バンプ電極
US5772451A (en) 1993-11-16 1998-06-30 Form Factor, Inc. Sockets for electronic components and methods of connecting to electronic components
US5431571A (en) 1993-11-22 1995-07-11 W. L. Gore & Associates, Inc. Electrical conductive polymer matrix
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
US5508228A (en) 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
US5431328A (en) 1994-05-06 1995-07-11 Industrial Technology Research Institute Composite bump flip chip bonding
US5393697A (en) 1994-05-06 1995-02-28 Industrial Technology Research Institute Composite bump structure and methods of fabrication
US6359335B1 (en) 1994-05-19 2002-03-19 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
US5989936A (en) * 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US5518964A (en) * 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US6870272B2 (en) 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
US5929517A (en) 1994-12-29 1999-07-27 Tessera, Inc. Compliant integrated circuit package and method of fabricating the same
US6826827B1 (en) * 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
US5707902A (en) 1995-02-13 1998-01-13 Industrial Technology Research Institute Composite bump structure and methods of fabrication
US5734547A (en) 1995-02-13 1998-03-31 Iversen; Arthur H. Power switchgear
US5801446A (en) 1995-03-28 1998-09-01 Tessera, Inc. Microelectronic connections with solid core joining units
JPH0964233A (ja) * 1995-06-15 1997-03-07 Ngk Spark Plug Co Ltd セラミック基板、その製造方法およびセラミック基板と樹脂製基板との接合体
US5874781A (en) 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5777379A (en) 1995-08-18 1998-07-07 Tessera, Inc. Semiconductor assemblies with reinforced peripheral regions
US5874782A (en) 1995-08-24 1999-02-23 International Business Machines Corporation Wafer with elevated contact structures
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6284563B1 (en) 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
US5749997A (en) 1995-12-27 1998-05-12 Industrial Technology Research Institute Composite bump tape automated bonding method and bonded structure
US5789271A (en) 1996-03-18 1998-08-04 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice
US6086386A (en) 1996-05-24 2000-07-11 Tessera, Inc. Flexible connectors for microelectronic elements
US6030856A (en) 1996-06-10 2000-02-29 Tessera, Inc. Bondable compliant pads for packaging of a semiconductor chip and method therefor
US5790377A (en) 1996-09-12 1998-08-04 Packard Hughes Interconnect Company Integral copper column with solder bump flip chip
US6255738B1 (en) 1996-09-30 2001-07-03 Tessera, Inc. Encapsulant for microelectronic devices
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6130116A (en) 1996-12-13 2000-10-10 Tessera, Inc. Method of encapsulating a microelectronic assembly utilizing a barrier
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
DE69830883T2 (de) 1997-03-10 2006-04-20 Seiko Epson Corp. Halbleiterbauelement und mit diesem Bauelement bestückte Leiterplatte
JP3968788B2 (ja) * 1997-03-21 2007-08-29 セイコーエプソン株式会社 半導体装置及びフィルムキャリアテープの製造方法
US6313402B1 (en) 1997-10-29 2001-11-06 Packard Hughes Interconnect Company Stress relief bend useful in an integrated circuit redistribution patch
US5937758A (en) 1997-11-26 1999-08-17 Motorola, Inc. Micro-contact printing stamp
JP3458056B2 (ja) * 1998-01-08 2003-10-20 松下電器産業株式会社 半導体装置およびその実装体
US5956235A (en) 1998-02-12 1999-09-21 International Business Machines Corporation Method and apparatus for flexibly connecting electronic devices
US6337445B1 (en) 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US6184576B1 (en) 1998-09-21 2001-02-06 Advantest Corp. Packaging and interconnection of contact structure
JP4024958B2 (ja) * 1999-03-15 2007-12-19 株式会社ルネサステクノロジ 半導体装置および半導体実装構造体
US6197613B1 (en) 1999-03-23 2001-03-06 Industrial Technology Research Institute Wafer level packaging method and devices formed
WO2000059033A1 (en) 1999-03-25 2000-10-05 Seiko Epson Corporation Wiring board, connection board, semiconductor device, method of manufacture thereof, circuit board, and electronic device
US6537854B1 (en) 1999-05-24 2003-03-25 Industrial Technology Research Institute Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed
JP2003502866A (ja) 1999-06-17 2003-01-21 インフィネオン テクノロジーズ アクチエンゲゼルシャフト 軟質ボンディング部を有する電子部品およびこのような部品を製造するための方法
US6277669B1 (en) 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
US6230400B1 (en) 1999-09-17 2001-05-15 George Tzanavaras Method for forming interconnects
JP2001144204A (ja) * 1999-11-16 2001-05-25 Nec Corp 半導体装置及びその製造方法
US6555908B1 (en) * 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
DE10014300A1 (de) 2000-03-23 2001-10-04 Infineon Technologies Ag Halbleiterbauelement und Verfahren zu dessen Herstellung
DE10016132A1 (de) * 2000-03-31 2001-10-18 Infineon Technologies Ag Elektronisches Bauelement mit flexiblen Kontaktierungsstellen und Verfahren zu dessen Herstellung
JP3596864B2 (ja) 2000-05-25 2004-12-02 シャープ株式会社 半導体装置
JP3440070B2 (ja) * 2000-07-13 2003-08-25 沖電気工業株式会社 ウェハー及びウェハーの製造方法
US6767818B1 (en) 2000-08-07 2004-07-27 Industrial Technology Research Institute Method for forming electrically conductive bumps and devices formed
US6660626B1 (en) 2000-08-22 2003-12-09 Charles W. C. Lin Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
US6710456B1 (en) 2000-08-31 2004-03-23 Micron Technology, Inc. Composite interposer for BGA packages
JP4174174B2 (ja) * 2000-09-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置およびその製造方法並びに半導体装置実装構造体
TW574752B (en) 2000-12-25 2004-02-01 Hitachi Ltd Semiconductor module
US6518675B2 (en) 2000-12-29 2003-02-11 Samsung Electronics Co., Ltd. Wafer level package and method for manufacturing the same
US6433427B1 (en) 2001-01-16 2002-08-13 Industrial Technology Research Institute Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
JP4465891B2 (ja) * 2001-02-07 2010-05-26 パナソニック株式会社 半導体装置
US20020121702A1 (en) 2001-03-01 2002-09-05 Siemens Dematic Electronics Assembly Systems, Inc. Method and structure of in-situ wafer scale polymer stud grid array contact formation
US6643739B2 (en) 2001-03-13 2003-11-04 Koninklijke Philips Electronics N.V. Cache way prediction based on instruction base register
US7148566B2 (en) 2001-03-26 2006-12-12 International Business Machines Corporation Method and structure for an organic package with improved BGA life
US20050097727A1 (en) 2001-03-28 2005-05-12 Tomoo Iijima Multi-layer wiring board, method for producing multi-layer wiring board, polishing machine for multi-layer wiring board, and metal sheet for producing wiring board
US20020151164A1 (en) 2001-04-12 2002-10-17 Jiang Hunt Hang Structure and method for depositing solder bumps on a wafer
JP3983996B2 (ja) * 2001-04-23 2007-09-26 株式会社ルネサステクノロジ 半導体集積回路装置
US6767819B2 (en) 2001-09-12 2004-07-27 Dow Corning Corporation Apparatus with compliant electrical terminals, and methods for forming same
TW517360B (en) 2001-12-19 2003-01-11 Ind Tech Res Inst Enhanced type wafer level package structure and its manufacture method
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US6638870B2 (en) 2002-01-10 2003-10-28 Infineon Technologies Ag Forming a structure on a wafer
US6940177B2 (en) 2002-05-16 2005-09-06 Dow Corning Corporation Semiconductor package and method of preparing same
DE10223738B4 (de) 2002-05-28 2007-09-27 Qimonda Ag Verfahren zur Verbindung integrierter Schaltungen
US7329563B2 (en) 2002-09-03 2008-02-12 Industrial Technology Research Institute Method for fabrication of wafer level package incorporating dual compliant layers
JP4091443B2 (ja) 2003-01-14 2008-05-28 シャープ株式会社 テレビジョン受信機及び電子番組表表示装置
DE10308095B3 (de) * 2003-02-24 2004-10-14 Infineon Technologies Ag Elektronisches Bauteil mit mindestens einem Halbleiterchip auf einem Schaltungsträger und Verfahren zur Herstellung desselben
WO2004077525A2 (en) 2003-02-25 2004-09-10 Tessera, Inc. Ball grid array with bumps
JP2004273592A (ja) 2003-03-06 2004-09-30 Seiko Epson Corp 半導体装置及びその製造方法
US7358608B2 (en) * 2003-06-13 2008-04-15 Oki Electric Industry Co., Ltd. Semiconductor device having chip size package with improved strength
TWI223363B (en) 2003-11-06 2004-11-01 Ind Tech Res Inst Bonding structure with compliant bumps
US7294929B2 (en) 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure
US7317249B2 (en) 2004-12-23 2008-01-08 Tessera, Inc. Microelectronic package having stacked semiconductor devices and a process for its fabrication
US7999379B2 (en) 2005-02-25 2011-08-16 Tessera, Inc. Microelectronic assemblies having compliancy

Also Published As

Publication number Publication date
TW200636878A (en) 2006-10-16
EP1851798A1 (en) 2007-11-07
US20110266668A1 (en) 2011-11-03
US7999379B2 (en) 2011-08-16
KR101267651B1 (ko) 2013-05-23
CN101128931B (zh) 2010-05-19
KR101357765B1 (ko) 2014-02-11
US20060194365A1 (en) 2006-08-31
KR20120137441A (ko) 2012-12-20
JP2013138214A (ja) 2013-07-11
EP1851798B1 (en) 2016-08-03
WO2006091793A1 (en) 2006-08-31
CN101128931A (zh) 2008-02-20
JP2008532291A (ja) 2008-08-14
WO2006091793A8 (en) 2007-10-04
KR20070106628A (ko) 2007-11-02
JP5593018B2 (ja) 2014-09-17

Similar Documents

Publication Publication Date Title
TWI335627B (en) Microelectronic assemblies having compliancy
KR100252457B1 (ko) 캔틸레버 요소및 희생기층을 사용하는 상호 접속요소의 제작방법
JP3006885B2 (ja) 相互接続のためのコンタクト構造、介在体、半導体アセンブリおよび方法
JP4540577B2 (ja) プローブカード・アセンブリ及びキット、及びそれらを用いる方法
US7200930B2 (en) Probe for semiconductor devices
JP5606695B2 (ja) 接続端子付き基板
EP0792463B1 (en) Mounting spring elements on semiconductor devices
TW201209939A (en) Stackable molded microelectronic packages
TW200534493A (en) Microelectronic packages and methods therefor
TW201101443A (en) Substrate having leads
US6369600B2 (en) Test carrier for testing semiconductor components including interconnect with support members for preventing component flexure
US7084656B1 (en) Probe for semiconductor devices
US7163885B2 (en) Method of migrating and fixing particles in a solution to bumps on a chip
KR100278342B1 (ko) 탐침 카드 조립체에서 탐침 요소의 배향을 변경하는 방법
JP2005353668A (ja) 構造体とその製造方法及び接合方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees