TWI322474B - Methods of forming nmos/pmos transistors with source/drains including strained materials and devices so formed - Google Patents
Methods of forming nmos/pmos transistors with source/drains including strained materials and devices so formed Download PDFInfo
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- TWI322474B TWI322474B TW095131113A TW95131113A TWI322474B TW I322474 B TWI322474 B TW I322474B TW 095131113 A TW095131113 A TW 095131113A TW 95131113 A TW95131113 A TW 95131113A TW I322474 B TWI322474 B TW I322474B
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- Prior art keywords
- forming
- nmos
- source
- layer
- transistor
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- 238000000034 method Methods 0.000 title claims description 62
- 239000000463 material Substances 0.000 title description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 35
- 229910052799 carbon Inorganic materials 0.000 claims description 35
- 239000013078 crystal Substances 0.000 claims description 31
- 239000007789 gas Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 18
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 17
- 229910052732 germanium Inorganic materials 0.000 claims description 16
- 230000006835 compression Effects 0.000 claims description 13
- 238000007906 compression Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 125000004429 atom Chemical group 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 125000004432 carbon atom Chemical group C* 0.000 claims description 5
- 241000238631 Hexapoda Species 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 229910000078 germane Inorganic materials 0.000 claims 1
- 238000009958 sewing Methods 0.000 claims 1
- 229910052727 yttrium Inorganic materials 0.000 claims 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 8
- 239000007943 implant Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 150000004767 nitrides Chemical group 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical group [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 1
- 241000282326 Felis catus Species 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical group [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052776 Thorium Inorganic materials 0.000 description 1
- XEFQLINVKFYRCS-UHFFFAOYSA-N Triclosan Chemical compound OC1=CC(Cl)=CC=C1OC1=CC=C(Cl)C=C1Cl XEFQLINVKFYRCS-UHFFFAOYSA-N 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002309 gasification Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229960003500 triclosan Drugs 0.000 description 1
Classifications
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Description
21647pif 九、發明說明: 【發明所屬之技術領域】 本,㈤是關於錢體電財縣結構的方法,且更具 一。之疋關於在積體電路中形成nm〇s/pm〇s電晶體結 構的方法。 【先前技術】 正在載子移動率改良之領域中之互補金氧半導體 (CMOS)結構之領域中進行研究。經調查用於此等改良 =所述領域巾之若干者包含將高介f常數(high_K)閘極 介電材料用於金屬閘電極、鰭式場效電晶體(FinFET) CMOS電晶體結構之使用、及在cM〇s電晶體之通道中應 力材料之形成以及襯墊之使用以誘發應力。 如在(例如)2004 年 12 月 13-15 日 IEDM Technical
Digest. IEEE International 第 217-220 頁之 Electron Devices Meeting,2004.中的 Komoda 等人之“Mobility Improvement for 45 nm Node by Combination of Optimized Stress Control and Channel Orientation Design,,,中討論的,一在 CMOS 結 構中改良載子移動率之方法包含使用矽鍺、通道定向、襯 墊層。 亦在(例如)尸rac. /五213-216 ( 2004 ) Pidin 等人 之 A Novel Strain Enhanced CMOS Architecture Using Selectively High Tensile and High Compressive Silicon Nitride Films,,,及美國專利第 6,885,084 號、第 6,621,131 號 及弟6,861,318號中討論上文所列之各種方法。 21647pif 【發明内容】 根據本發明之實施例可提供形成具有包含應力材料之 源極/汲極的NMOS/PMOS電晶體的方法以及以此方法形 成的元件。根據此等實施例,一種形成積體電路丨之方法包 含:平行於其<100>晶體定向在基板上選擇性地形成NMOS 及PMOS電晶體之活性通道區域(active channel region); 及選擇性地形成NMOS電晶體之其中具有碳(C )雜質的源 極/没極區域。在根據本發明之某些實施例中,方法更包含 在NMOS電晶體上形成拉伸層以在其活性區域中提供拉伸 應變。 在根據本發明之某些實施例中,形成拉伸層包含在 NMOS電晶體上形成siN層使得SiN層中之N-H鍵結與Si-H 鍵結之比為約1至5。在根據本發明之某些實施例中,形成 SiN層包含:在約50至約1〇〇〇 w之功率及約400攝氏度至約 500攝氏度之溫度下使用以約至約sccm之速率提供 之SiH4氣體及以約1至約5 slm之速率提供iNH3氣體,來 將SiN層形成為約5〇埃至約2〇〇〇埃之厚度。 根據本發明之某些實施例,選擇性地形成源極/沒極區 域包含在源極/汲極區域中磊晶成長c摻雜矽以提供NM〇s 電晶體之源極/汲極區域以便用C原子取代源極/汲極區域 中的約1 /〇至約2%之Si原子。在根據本發明之某些實施例 中,選擇性地形成源極/汲極區域包含用C植入NM〇s電晶 體之源極/汲極區域。 在根據本發明之某些實施例中,磊晶成長包含在小於 21647pif 約650攝氏度之溫度T使用化學氣相沈積(cv⑴法來在 f極/汲極區域中^成長碳摻_。在根據本發明之某些 貫知例中,蠢晶成長C摻雜石夕包含使用減壓化學氣相沈積 (RPCVD)或超高真空化學氣相沈積(uhvcvd)法來在 源極/汲極區域中磊晶成長c摻雜矽。 、在根據本發明之某些實施例巾,使用來在源 極/及極區域中屋晶成長C摻雜♦包含在約職職之壓力 下提供約刚至約200 sccm之速率之石夕氣及約5至約5〇 seem之速率之C氣以及小於約1〇〇〇 sccmi速率之選擇性 儀刻氣體。在㈣本發明m闕巾,選擇性地形成 NMOS電晶體之其中具有c雜質的源極/汲極區域更包含僅 开/成刪08電aa體之其中具有碳雜質的源極/汲極區域。 在根據本發明之某些實施例中,方法更包含形成 PMOS電晶體之其中具有鍺(Ge)雜質的源極/汲極區域。 在根據本發明之某些貫施例巾,在難⑽電晶體上形成拉 伸層更包含僅在NMOS電晶體上形成拉伸層且避免在 PMOS電晶體上形成拉伸層。 在根據本發明之某些實施例中,電晶體上形 成拉伸層包括僅在NMOS電晶體上形成拉伸層包括,其中 方法更包含僅在PMOS電晶體上形成壓縮應變層。在根據 本發明之某些實施例中,形成壓縮應變層更包含抵消與 PMOS電晶體上之拉伸層相關聯之應力。 在根據本發明之某些實施例中,CMOS積體電路1包 έ ·平行於其<1〇〇>晶體定向在基板上的nm〇s&pM〇s電 1322474 21647pif 晶體之活性通道區域;&NM〇S電晶體之其中具有(c)雜 質的源極/汲極區域。 在根據本發明之某些實施例中,電路更包$NM〇s, 晶體上之拉伸層以在其活性區域中提供拉伸應變。在根據 本發明之某些實施例中,拉伸層為]^]^〇5;電晶體上 層’其中N-H鍵結與Si-H鍵結之比為約丨至5。在根據本發 明之某些貫施例中,SiN層具有約50埃至約2〇〇〇埃之厚度。 在根據本發明之某些實施例中,源極/汲極區域為c摻 雜磊晶矽,其中用C原子取代源極/汲極區域中之約1%至約 2%之Si原子。在根據本發明之某些實施例中,電路更包含 PMOS電晶體之包含其中之鍺(Ge )雜質的源極/汲極區域。 在根據本發明之某些實施例中,拉伸層僅在>1]^〇8電 晶體上。在根據本發明之某些實施例中,電路更包含僅在 PMOS電晶體上的壓縮應變層。 【實施方式】 參看隨附圖式在下文中更全面地描述本發明,其中展 示了本發明之實施例。然而,本發明可以許多不同形式來 實施且不應被解釋為限制於本文所述之實施例。相反,提 供此等實施例使得本揭示案將為徹底且完整的,且將向熟 "白此項技藝者王面傳達本發明之範嘴。在諸圖中,層及區 域之大小及相對大小可為了清楚起見而誇大。 應瞭解的是當構件或層被稱作“在另一構件或層上,,、 “連接至”或“耦接至,,另一構件或層時,其可直接在另—構、 件或層上、連接至或耦接至另一構件或層或可存在介入構 9 21647pif 件或層。相反’當構件被稱作“直接在另一構件或層上,,、‘‘直 接連接至”或‘‘直接耦接至”另一構件或層時,不存在介入構 件或層。相同數字在全文中指相同構件。如本文所使用, 術語“及/或”包含相關所列項目中的一或多個的任何及所 有乡且合。 應瞭解的是儘管術語第一、第二、第三等在本文中用 以描述各種構件、組件、區域、層及/或區,但此等構件、 組件、區域、層及/或區應不受此等術語限制。此等術語僅 用以使一個構件、組件、區域、層及/或區與另一區域、層 或區區分。因此,下文論述之第一構件、組件、區域 或區可稱為第二構件、組件、區域、層或區而不背離本^ 明之教示。 空間相關術S吾’諸如“在 夕丁,,、“ — ......<卜、在......下方’、“下 面的、在......之上、上面的”及其類似物在本文中用於 描述之方便起見’以便描述如圖式中所說明之—個構件或 :語欲包含除㈣所崎之定向之外元件在使用= 以二:!如,若翻轉圖式中之元件,則既而 ^述為在其他㈣4雜之下Ί其他構件或 ==將定構件或特徵之上 性術5吾在......下方可包含在上面及右下. 可另外定向(旋轉90度或在其他面的方位。元件 使用空間相關描述符來解釋。°处)且因此在本文中 本文中所使用之*顿為達成描述特殊實施例之目的 2l647pif 而不欲限制本發日月。如本文所用,單數形式及 ,包含f數形式’除非本文另外清楚指示。亦將更瞭解 ,疋術,吾包括’’在本說明書中使用時指定了所述特徵'、'敕 數:步驟、操作、構件及/或組件的存在,但不排除一或; 固,、他特徵、整數 '步驟、操作 組 电 的存在或加入。 乂/、^。 參看橫截面圖在本文中描述本發明之實施例,所述橫 面圖為本發明之理想實施例(及中間結構)的示意圖。 ^此^將預期作為(例如)製造技術及/或公差之結果的圖 :、之形狀的變化。因此,本發明之實施例不應被解釋為限 二於本文中所述之區域之特殊形狀,而包含由(例如)製 起的开)狀之偏差。例如,圖示為矩形的經植入區域將 通常在其邊緣處具有圓形或彎曲的特徵及/或植入濃度的 梯度而非自經植入至未植入區域的二態改變。同樣,藉由 形成的内埋區域可導致在内埋區域與表面之間的^域 、的某些植入,經由所述區域發生植入。因此,圖式中所 、a區域貝貝上疋示意性的且其形狀不欲說明元件之區域 之實際形狀且不欲限制本發明之範疇。 ,除非另外界定,否則本文中所使用之所有術語(包含 =啣及科學術語)具有與本發明所屬技術之一般熟習此項 藝者普遍理解之意義相同的意義。更應瞭解的是,除非 文特別界定,否則諸如常用字典中所界定的彼等術語應 釋為具有與相關技術之内容中的意義相一致的意義而不 〜以理想化或過度正式之意義解釋。 21647pif
21647pif 驅動電流 PMOS 電 E 如下文更詳細描述的,各種方法可用於形成 NMOS/PMOS電晶體以便提高其中之載子之總移動率。例 如’在根據本發明之某些實施例中,PMOS及NMOS電晶 體在晶圓上形成,使得待用作通道之活性區域對準於晶圓 之<100>平面,其可將PMOS電晶體之驅動電流提高約1〇〇/0 至約20%°另外’碳摻雜磊晶層可用於NMOS及PMOS之源 極/沒極以允許NM0S電晶體之驅動電流提高約2〇%至約 30% ’而亦將卩]^〇8電晶體之驅動電流降低約1%至約2%。 另外,拉伸層可形成KNM〇s&PM〇s電晶體上以進一步 提向NMOS電晶體之驅動電流,而亦降低1>]^[〇3電晶體之 因此,如本發明之發明者所瞭解的,NM〇S& 长 日日體之开>成中上述之構件可經組合用於總驅動電 二之提问其疋藉由(利用<100〉通道定向)提供pM〇s 2曰日體之效犯之顯著提高以及由源極/汲極區域中包含碳 払雜磊晶層而引起的NM〇s電晶體之驅動雪洎夕接宜。坆
〜W丨工/ π性眭场用碳植 入而非在源極/汲極區域中成長碳
,拉伸層僅在 在根據本發明之其他實施例中, 碳摻雜磊晶層僅形成 1322474 21647pif 於與NMOS電晶體相關聯的源極/汲極區域中。在根據本發 明之其他貫施例中,碳摻雜磊晶層成長於與]^]^〇5電晶體 相關聯的源極/汲極區域中,而鍺摻雜磊晶層成長於與 PMOS電晶體相關聯的源極/沒極區域中。如本發明之發明 者所瞭解的,在與NMOS電晶體相關聯的源極/汲極區域中 鍺的包含可取代在彼結構中另外存在的矽原子之一部分且 藉此在PMOS電晶體之相關通道中產生拉伸應力以提高其 驅動電流。在根據本發明之其他實施例中,壓縮層在pM〇s 電晶體上形成。 圖2-11為說明形成根據本發明之某些實施例之 NMOS/PMOS電晶體的方法的橫截面圖。根據圖2,淺槽隔 離區域20形成於分別用以形成nm〇S及PMOS電晶體之基 板30、40的不同區中。更具體言之,NM〇s&pMOS電晶 體可形成於NMOS區30及PMOS區40中,其個別通道對準 於如圖1中所說明之晶圓之<1〇〇>平面。處區域3〇 以在其NMOS活性區域32中形成p型井。類似地,n型井形 成於PMOS£域40中以在其中提供pm;〇s活性區域42。兩個 活性區經形成具有平行於晶圓丨024 〇〇>平面的定向。 根據圖3,NMOS閘極結構形成於NMOS區域30中,且 PMOS閘極結構形成於PMOS區域40中。特定言之,NMOS 閘極結構包括閘極介電層110,所述閘極介電層Π0可由 Si02、SiON、Si3N4、HF02、ZR02、AL203、TA205 或 其他類似材料形成。NMOS閘極結構亦包括閘電極120,其 可由多晶矽或其他適當材料形成。NMOS閘極結構亦包括 13 21647pif =極120上的封蓋層m,其可由_、si〇N或其他類似 材料形成。PMOS閘極結構包括閘極介電層21〇、閘電極 220、及封蓋層230,其皆可由相同於參考舰〇§區域扣之 閘極結構上述之材料的材料(或類似材料)形成。 根據圖4 ’第-鮮層52_絲覆蓋pM〇s區域扣且 暴露NMOS區域30。使用NM0S閘極結構作為植入遮罩, 雜質被植入NMOS區域30中以形顧型輕推雜區域162。將 瞭解植入NMOS區域3G中的雜質可包括砂或用以形成_ 區域的其他適當摻雜劑。f —遮罩層52可既而自pM〇s區 域40移除。 根據圖5,第二遮罩層54經形成以覆蓋]^皿〇3區域3〇 且暴露PMOS區域40。使用PM0S閘極結構作為遮罩,植入 執行於;PMOS區域40中以形成?型輕摻雜區域262。將瞭解 可使用蝴或其他P型摻雜劑。 根據圖6,氧化層142沈積於NMOS區域30上且沈積於 PMOS區域40上’接著氮化層144沈積於其上。回鞋法可用 以在NMOS閘極結構上形成隔片14〇,其14〇包含在]^1〇§ 閘極結構之側壁上的氧化層142及氮化層144。此外,回蝕 法亦形成側壁隔片240,其包含在PM0S閘極結構之側壁上 的氧化層242及氮化層244。 根據圖7,藉由選擇性地姓刻nm〇S區域30及PMOS區 域40之暴露活性區域32、42,溝槽150及250分別形成於 NMOS區域及PMOS區域40中。在根據本發明之某些實施 例中,溝槽150及250具有約3〇〇埃至約1000埃之深度。在根 厶厶/Η 21647pif =發明之某些貫施例巾,溝彻q及⑽可使用乾式或化 子亂相敍刻絲形成。化學氣她刻法可包括在約5托至約 托之壓力及約_t:至糊叱之溫度下,以触〇2至約 1.0私準Α升/为鉍(SLM)提供HC1且以約20 SLM提供Η2。
,據圖8,溝槽15〇、25()制選擇性蟲晶成長技術用碳 二亦猫日日層來填充。例如,碳摻雜磊晶層可使用、減 壓CVD(RPCVD)或超高真空CVD(UHVCVD)來形成。 在根據本發明之某些實施例巾,鄕雜晶層藉由同時提 供石夕源氣、碳源氣及選擇性勤丨氣體來形成。例如,石夕氣 可為二氯石夕烧(DCS)、三氯魏(Tcs)、六氣石夕院⑽幻、 SIH4或SI2H6。碳氣可為SIH3CH3、cm或㈣斗。選擇性 餘刻氣體可為HCL或CL2。亦可使用上述氣體之替代氣體。
RPCVD法可使用以約⑽至約細標準立方公分/分鐘 (seem)的速率提供之DCS及以約5至約5〇 sccm提供之 SIH3CH3以及以小於約1〇〇〇 sccm提供2HCL來執行,且在 約10至約20托之壓力τ且在不大於6贼之溫度下執行。如 本發明之發明者所瞭解的,磊晶成長之過程在大於65〇它之 溫度下執行,碳原子可進入矽原子之間的間隙位置(而非 取代矽原子)以便不提供足夠的拉伸應力至NMOS電晶_ 中之通道區域146。 因此,在根據本發明之某些實施例令,碳摻雜磊晶層 使用選擇性磊晶成長形成於NMOS/PMOS電晶體之源極/ 汲極區域,使得碳原子取代以此方法形成之碳摻雜磊晶層 中之約2%之矽原子的最大量。在根據本發明之某些實施例 15 21647pif I,碳摻雜蠢晶源極/沒極層165、265上升高於基板之鄰接 ^面,其可進-步增加通道上的拉伸應力以提供增加的載 子移動率。 在本發明之其他實施例中’碳摻雜源極/沒極區域可藉 由將圖6中所示之閘極結構用作植入遮罩來將碳植入石^ 板中而提供。因此,可避免—提供祕/汲極區域的溝槽 150、250之形成及碳摻雜磊晶層之後續成長。 根據圖9 ’遮罩層56經形成以覆蓋PM〇s區域4〇且暴露 NMOS區域30。使用N型摻雜劑來執行植入以在1^]^〇8電晶 體之源極級極區域中形成N型高摻雜區域丨64。在根據本發 明之某些實施例中,As用作N型摻雜劑。可使用其他類^ 之摻雜劑。可既而移除遮罩層56。 ^根據圖10,遮罩層58經形成以覆蓋NMOS區域30且暴 路PMOS區域40。使用P型摻雜劑來執行植入以將pM〇s區 域40中之閘極結構及側壁隔片用作植入遮罩來形成p型高 摻雜源極/汲極區域。在根據本發明之某些實施例中,B用 作P型摻雜劑。然而,可使用其他類型之摻雜劑。既而使 用快速向熱退火或雷射退火法來熱處理]^]^〇§及1)厘〇§區 域30、40。亦可使用其他類型之熱處理。 根據圖11,拉伸層3〇〇形成在包含sNM〇s區域3〇及 PMOS區域40中之NMOS及PMOS電晶體之上。在根據本發 明之某些實施例中,拉伸層3〇〇可由、SiON、LPCVD 氧化物、ALD氧化物或SOG氧化物形成以具有約50埃至約 2000埃之厚度,以便提供NMOS電晶體結構1〇〇及PMOS電 1322474 21647pif 晶體結構200。 在根據本發明之某些貫施例中’利用以約10至約100 seem之速率提供之SIH4氣體及以約10至約1〇〇sccm之速率 k供之NH3氣體以及以約1至約5 SLM提供之N2來使用 PECVD法’使用在約400°C至約50(TC之溫度下執行之約5〇 至約1000瓦特之RF功率,拉伸層可由SiN形成。 因此,拉伸層300可經形成,使得siN層内之N-H鍵結 • 與SI-H鍵結之比可用以調整層提供至下伏之NM〇s/pM〇s
電晶體之應力類型。例如’在根據本發明之某些實施例中, N-H鍵結與SI-H鍵結之比為約丨至約5以提供拉伸應力至位 於SiN層之下的通道。在根據本發明之其他實施例中, 鍵結與SI-H鍵結之比可為約5至約2〇以在對應通道中提供 壓鈿應力。因此,在根據本發明之某些實施例中,調整N_H 鍵結與SI-H鍵結之比以提供約以那之比,以便提供拉伸 應力至其下之通道。 在根據本發明之其他實施例中,NMOS區域30中之 • 丽⑽電曰曰體可如參考圖1-10上述而形成以提供NMOS及 PMOS電晶體。然而,拉伸層3〇〇可僅在醒〇§電晶體上而 不在PMOS電晶體上形成,以便藉此避免拉伸層3〇〇對 PMOS^晶體之潛在負面影響,如圖μ中所說明。 如上述的’在根據本發明之某些實施例中,NMOS及 P M 0 s二晶體之通道之定向可經形成平行於晶圓之< 1 〇 〇〉 ^面以提供PMOS電晶體之電流驅動之增加。此外,NM〇s 及PMOS電晶體之碳摻雜源極/汲極區域使用選擇性蟲晶成 17 1322474 21647pif 長來形成以便提高相關聯之NM0S電晶體之電流驅動。此 外,拉伸層可形成於NMOS及PMOS電晶體之上以提供驅 動電流之進一步增加至其下2NM〇s電晶體。如本發明之 發=者所瞭解的,與PMOS電晶體相關聯之源極/沒極區域 中碳摻雜磊晶層以及形成於PM〇S電晶體之上之拉伸層之 使用可將PMOS電晶體之驅動電流降低約1 %至約2%。 如本發明之發明者進一步瞭解且參考圖M11述的, 用以形成NMOS電晶體之源極/汲極區域之碳摻雜磊晶層 可將其驅動電流提高約20%至約30%。此外,形成kNM〇s 電晶體之上之拉伸層亦可提高驅動電流。 圖12-14為§兑明根據本發明之某些實施例之形成 NMOS/PMOS電晶體的方法的橫截面圖。特定言之,如圖 12中所示,遮罩62經形成以覆蓋PM0S區域4〇且暴露 NMOS區域30以促進與NMOS電晶體相關聯之源極/汲極區 域之形成。根據圖12 ’溝槽150形成於與其中之NMOS電晶 體相關聯之NMOS區域30中。如圖13中所示,碳摻雜蠢晶 層16 5形成於溝槽15 0中以僅為NM 0 S電晶體提供源極/汲 極區域。如圖14中所示,高摻雜N+源極/汲極區域164經形 成用於NMOS電晶體且高摻雜p+源極/汲極區域264經形成 用於PMOS電晶體。在根據本發明之某些實施例中,拉伸 應力層300形成於NMOS及PMOS電晶體之上,其可提高 NMOS電晶體中之驅動電流。 因此,如本發明之發明者所瞭解的,避免在pM〇s電 晶體中之碳摻雜磊晶源極/汲極區域之形成可有助於避免 21647pif PM〇Stasa體中之驅動電流之降低。 在根據本發明之其他實關中,使用如圖⑽所說明 之I擇性蠢晶成長,錯推雜羞 體之源極/汲極區域中。 層6可形成射娜電晶 如本發日狀發财猶_,鍺摻轉㈣極/汲極區 彡t可允許錯原子取代㈣子中之若干者以提供
取韻原子取代蟲晶層中奴比增加,_8\二= 壓縮應力可增加,以進-步提高PM〇s電晶體之驅動電流。 在如圖17中所說a月之根據本發明之其他實施例中,壓 細層可形成於PMOS區域4〇之PMOS電晶體上。特定言之, 拉伸層300可自PMOS區域40移除且壓縮層31〇形成於
NMOS區域30及PMOS區域40之上。藉由(例如)植入N或 Ge雜質至NMOS區域30之壓縮層31〇&中,可處理^|^〇8區 域30中之壓縮層31〇a以移除下wNMOS電晶體上之壓縮效 應,藉此易於抵消由層310a產生的NMOS電晶體上之應 力。進一步根據圖17,壓縮層31〇之處理可不施加於pM〇s 區域40上之壓縮層310之部分使得壓縮層31〇之壓縮效應維 持於PMOS區域40中壓縮層310之下之PMOS電晶體上。 如上述的’各種方法可用於形成NMOS/PMOS電晶體 以便提高其中之載子之總移動率。例如,在根據本發明之 某些實施例中,PMOS及NMOS電晶體在晶圓上形成,使 得待用作通道之活性區域對準於晶圓之<1〇〇>平面,其可 將PMOS電晶體之驅動電流提高約1〇%至約20%。另外,碳 19 1322474 21647pif 摻雜磊晶層可用於NMOS及PMOS電晶體之源極/汲極以允 許NMOS電晶體之驅動電流提高約2〇%至約30%,而亦將 PMOS電晶體之驅動電流降低約1%至約另外,拉伸層 了 t成於NMOS及PMOS電晶體上以進一步提高NMOS電 晶體之驅動電流,而亦降低PMOS電晶體之驅動電流。因 , 此,如本發明之發明者所瞭解的,NMOS及PMOS電晶體 之形成中上述之構件可經組合用於總驅動電流之提高,其 ••是藉由(利用<1〇〇>通道定向)提供?]^〇8電晶體之效能之 顯著提高以及由源極/汲極區域中包含碳摻雜磊晶層而引 起的NMQS電晶體之轉電流之提高。此外,碳摻雜蟲晶 源=/汲極區域及拉伸層對PM〇s電晶體之負面影響相對於 由奴摻雜磊晶汲極區域提供的!^^^電晶體之提高是小量 的,藉此提供包含NMOS及PM0S電晶體之元件之载子 動率的總提高。 &在圖式以及說明書中,已揭露本發明之實施例,且儘 官使用了特定術語’但僅以通用以及描述性意義使用術語 於限制之目的,本發明之範疇在以下申請專利範 【圖式簡單說明】 ,圖1為展示其中之各種平面定向之晶圓的示意圖。 圖2-12為說明根據本發明之某些實施例之形 NMOS/PMOS電晶體的方法的橫截面圖。 圖13_15為說明根據本發明之某些實施 NMOS/PMOS電晶體的方法的橫截面圖。 4 20 1322474 21647pif 圖16為說明在根據本發明之某些實施例之 NMOS/PMOS電晶體形成的法中提供的中間結構的橫截面 圖。 圖17為說明在根據本發明之某些實施例之 NMOS/PMOS電晶體形成的法中提供的中間結構的橫截面 圖。 【主要元件符號說明】 1 :積體電路 10 .晶圓 20 :淺槽隔離區域 30 : NMOS 區域 32 : NMOS活性區域 40 : PMOS 區域 42:PMOS活性區域 52 :遮罩層 54 :遮罩層 56 :遮罩層 58 :遮罩層 62 :遮罩 100 : NMOS電晶體結構 Π0 :閘極介電層 120 :閘電極 130 :封蓋層 140 :隔片 21 1322474 21647pif 142 :氧化層 144 :氣化層 146 :通道區域 150 :溝槽 160: N型摻雜區域 162 : N型輕摻雜區域 164 : N型高摻雜區域 165 :磊晶源極/汲極層 200 : PMOS電晶體結構 210 :閘極介電層 220 :閘電極 230 :封蓋層 240 :隔片 242 :氧化物 244 :氮化物 246 :通道區域 250 :溝槽 260: P型摻雜區域 262 : P型低摻雜區域 264 : P型高摻雜區域 265 :磊晶源極/汲極層 266 :鍺摻雜磊晶層 300 :拉伸層 310 :壓縮層 22 1322474 21647pif 310a :壓縮層
Claims (1)
1322474 21647pif 十、申請專利範圍: 一種形成積體電路之方法,其包括: 在基板上平行於其<1〇〇>晶體定向以選擇性地形成 NMOS及PMOS電晶體之活性通道區域;以及 選擇性地形成所述]^4〇5;電晶體中具有碳(c)雜質 的源極/汲極區域。 2. 如申請專利範圍第1項所述之形成積體電路之方 法,其更包括: 在所述NMOS電晶體上形成拉伸層以在其活性區域 中提供拉伸應變。 3. 如申請專利範圍第2項所述之形成積體電路之方 法’其中形成拉伸層包括·· 在所述NMOS電晶體上形成SiN層使得所述siN層 中之N-H鍵結與Si-H鍵結之比約為1至5。 4. 如申請專利範圍第3項所述之形成積體電路之方 法’其中形成SiN層包括: 在約50至約1000 w之功率及約4〇〇攝氏度至約5〇〇 攝氏度之溫度下使用以約10至約1〇〇 sCCm之速率提供之 SiH4氣體及以约1〇至約1〇〇 sccm之速率提供之ΜΗ]氣 體以及以約1至約5slm之速率提供之N2氣體,來將所= SiN層形成為具有約5〇埃至約2〇〇〇埃之厚度。 、5.如申請專利範圍第1項所述之形成積體電路之 法’其中選擇性地形成源極/汲極區域包括: 在所述源極/汲極區域中磊晶成長C摻雜矽以提供 24 1322474 21647pif 述NMOS電晶體之源極/沒極區域,以便用c原子取代所 述源極/沒極區域中約1%至約2%的Si原子。〜 、6.如申叫專利範圍第1項所述之形成積體電路之方 法’·其中選擇性地形成源極/汲極區域包括: 用C植入所述]^]^〇8電晶體之所述源極/汲極區域。 、7.如申明專利範圍第5項所述之形成積體電路之方 法’其♦蟲晶成長包括: 在小於、約650攝氏溫度之溫度下使用CVD法在所述 源極/汲極皞域中磊晶成長所述碳摻雜矽。 8.如申請專·圍第7項所叙形缝體電路之方 法’其中蟲晶成長所述c #雜石夕包括使用RpcvD或 UH V C VD法來在崎源極/ &極區域巾“成長所述c推 雜矽。 、9·如中請專職圍第7項所述之形成積體電路之方 法’其中使用RPCVD法在所述源極/沒極區域中蟲晶成長 所述C摻雜矽包括: 在約10至約20把之壓力下,提供約1〇〇至約2〇〇 _ 之速率之石夕氣'、及約5至約5〇 sccm之速率之c氣以及小 於約1000 seem之速率之選擇性蝕刻氣體。 / 10.如申請專職圍第2項所述之形成積體電路之方 法,其中選擇性地形成所述NM〇s電晶體中具有 源極/汲極區域更包括: " 僅形成所述NM0S電晶體中具有所述碳 源極/汲極區域。 ' 25 1322474 21647pif 11.如申請專利範圍第10 法,其更包括: 項所述之形成積體電路之方 電晶體中具有绪(Ge)雜質的所述源 12. 如申請專利範圍第2項所述之形成積體 法,其中在所述NMOS電晶體上形成拉伸#包括之方
僅在所述NM〇S電晶體上形成所述拉伸層且避免在 所述PMOS電晶體上形成所述拉伸層。 13. 如申請專職圍第2韻述之形成積體電路足方 法,其中在所述NMQS電晶體上形餘伸層包括僅在 NMOS電晶體上形成所述拉伸層,該方法更包括:
形成所述PMOS 極/汲極區域。 僅在所述PMOS電晶體上形成壓縮應變層。 14.如申請專利範圍第2項所述之形成積體電路之方 法,其中在所述NMOS電晶體上形成拉伸層包括僅在所述 NMOS電晶體上形成所述拉伸層,該方法更包括: 在所述NMOS及所述PMOS電晶體上形成所述壓縮 層;以及 將氮(N)或鍺(Ge)植入所述NMOS電晶-體上之所 述壓縮層中。 15.—種形成積體電路之方法,其包括: 在基板上平行於其<100晶體定向以選擇性地形成 NMOS及PMOS電晶體;活性通道區域;以及 用碳(C)原子取代所述NMOS電晶體之源極/汲極區 域中約1%以上之石夕(Si)原子。 26 21647pif 16·如申請專利範圍第15項所述之形成積體 法,其更包括: 万 在所述源極/沒極區域中蟲晶成長碳(c)推雜石夕 供所述NMOS電晶體之源極/;及極區域,以便用c原子取 代所述源極/汲極區域中約1%至約2%的si原子。 、17.如中請專利範圍第15項所述之形成積體電路之方 法’其中用C原子取代時包減晶成長具有c雜 或用C雜質植入Si。 18.—種形成積體電路之方法,其包括: 在基板上平行於其d 〇 〇 >晶體定向以選擇性 NMOS及PMOS電晶體之活性通道區域; 在與所述NMOS及所述PM0S電晶體之所述活性通 道區域相關聯之源極/祕區域巾選擇性地蠢晶成長碳 掺雜矽;以及 在所述NMOS及所述PM〇s電晶體上形成拉伸層。 19.如申請專利範圍第18項所述之形成積體電路之方 法,其中形成拉伸層包括: 形成SiN層使得所述SiN層中之N_H鍵結與^_Η鍵 結之比為約1至5/? ' 20·如申請專利範·圍第19,項所述之形成積體電路之方 法,其中形成SiN層包括: 在約50至約1〇〇〇 W之功率及約4〇〇攝氏溫度至約 500攝氏溫度之溫度下使用以約1〇至約1〇〇 sccm之速率 板供之SiH4氣體及以約1至約5 sim之速率提供之 1322474 21647pif 氣體,來將所述SiN層形成為具有約5〇埃至約2〇〇〇埃之 厚度。 21. —種形成積體電路之方法,其包括: 在基板上平行於其< 1 〇 〇 >晶體定向以選擇性地形成 NMOS及PMOS電晶體之活性通道區域; 在僅與所述NMOS電晶體之所述活性通道區域相關 聯之源極/汲極區域中選擇性地磊晶成長碳(c)摻雜矽; 以及 ’’ y 在所述NMOS及所述PMOS電晶體上形成拉伸層。 22. —種形成積體電路之方法,其包括: 在基板上平行於其< 10 0 >晶體定向以選擇性地形成 NMOS及PMOS電晶體之活性通道區域; 在與所述NMOS電晶體之所述活性通道區域相關聯 之源極/汲極區域中選擇性地磊晶成長碳(C)摻雜石夕; 在與所述PMOS電晶體之所述活性通道區域相關聯 之源極/汲極區域中選擇性地磊晶成長鍺(Ge)摻雜石夕;以 及 在所述NMOS及所述PMOS電晶體上形成拉伸層。 23. —種形成積體電路之方法,其包括: 在基板上平行於其<1 〇〇>晶體定向以選擇性地形成 NMOS及PMOS電晶體之活性通道區域; 將碳(C)植入與所述NMOS及所述PMOS電晶體之 所述活性通道區域相關聯、之源極/波極區域中;以及 在所述NMOS及所述PMOS電晶體上形成拉伸層。 28 1322474 2l647pif 24. —種形成積體電路之方法,其包括: 在基板上平^亍於其< 1 〇〇>晶體疋向以選擇性地形成 NMOS及PMOS電晶體之活性通道區域; 在與所述NMOS及所述PMOS電晶體之所述活性通 道區域相關聯之源極/汲極區域中選擇性地磊晶成長碳(c) 摻雜矽;以及 僅在所述NMOS電晶體上形成拉伸層。 25. —種形成積體電路之方法,其包括: 籲 在基板上平行於其 <〗〇〇>晶體定向以選擇性地形成 NMOS及PMOS電晶體之活性通道區域; 在與所述NMOS及所述PM0S電晶體之所述活性通 道區域相關聯之源極/汲極區域中選擇性地磊晶成長碳(c) 摻雜矽; 在所述NMOS電晶體上形成拉伸層;以及 在所述PMOS電晶體上形成壓縮層。 、 26.如巾請專職圍第25項所述之形成積體電路之方 # *,其中在所述NM0S電晶體上形成拉伸層以及在所述 PMOS電晶體上形成壓縮層包括: 在所述NMOS及所述PM0S電晶體上形成所述拉伸 層; 自所述PMOS電晶體移除所述拉伸層; 在所述PMOS及所述NM0S電晶體上形成所述 層;以及 將氮(N)或錯(Ge)植入所述刚沉電晶體上之所 29 1322474 2l647pif 述魘縮層中。 27. —種CMOS積體電路,其包括: 基板上平仃於其<1〇〇>晶體定向之NM〇s及pM〇s電 晶體之活性通道區域;以及 所述NM0S電晶财具有碳(C)雜質的源極/汲極區 域。 28. 如申明專利$巳圍帛27項所述之CM〇s積體電路, 更包括: 所述NMOS電晶體上之拉伸層,其用以在其所述活性 區域中提供拉伸應變。 29>t 16® f 28 CMOS » 其中所述拉伸層包括: 所述NM0S電晶體上的SiN層,其中所述SiN層中 之N-H鍵結與Si-H鍵結之比為約1至5。 30. 如申請專利範圍第29項所述之CMOS積體電路, 其中所述SiN層具有約50埃至約2〇〇〇埃之厚度。 31. 如申請專利範圍第27項所述之CMOS積體電路, 其中所述源極/汲極區域包括C摻雜磊晶矽,其中用c原 子取代所述源極/汲極區域中之約1%至約2%之Si原子。 32. 如申請專利範圍第27項所述之CMOS積體電路’ 更包括: 所述PM0S電晶體中包含鍺(Ge)雜質的源極/汲極 區域。 33·如申請專利範圍第28項所述之CMOS積體電路, 30 1322474 2l647pif 其中所述拉伸層僅在所述NMOS電晶體上。 34. 如申請專利範圍第30項所述之CMOS積體電路, 更包枯: 僅在所述PMOS電晶體上的壓縮應變層。 35. 如申請專利範圍第27項所述之CMOS積體電路, 其中所述C雜質僅在所述NMOS電晶體之所述源極/汲極 區域中。 36. 如申請專利範圍第27項所述之CMOS積體電路, 其中所述NMOS電晶體之所述源極/汲極區域包括蠢晶石夕 中之C雜質’所述電路更包括: 所述PMOS電晶體之源極/汲極區域,其包括磊晶矽 中之C雜質;以及 在所述NMOS及所述PMOS電晶體上的拉伸層。 31
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