TWI294655B - - Google Patents

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TWI294655B
TWI294655B TW091109776A TW91109776A TWI294655B TW I294655 B TWI294655 B TW I294655B TW 091109776 A TW091109776 A TW 091109776A TW 91109776 A TW91109776 A TW 91109776A TW I294655 B TWI294655 B TW I294655B
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electrode
substrate
wafer
semiconductor device
chip
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Sony Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

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Description

1294655 A7 B7 五、發明説明（1 ) [發明的技術領域] 本發明係關於適合使用於多晶片模組之半導體篆置及其 製造方法。 [先前技藝] 近年來，已知有將CSP( Chip Size Package :晶片尺寸封裝 體）構造之元件晶片多數片安裝於基板上，或將多數元件 晶片以倒裝片接合方式安裝於插入式基板上，而構成所謂 多晶片模組之半導體裝置之技術。例如，日本特開2〇⑼ 164635號公報中曾揭示過有關將元件晶片以倒裝片接人方 式安裝於插入式基板上之技術。 [發明所欲解決之問題] 然而’在使用插入式基板構成多晶片模組之半導體裝置 100中，如圖5之剖面圖所示，係呈現將形成於各元件晶片 10、10之凸塊l〇a連接於插入式基板1上之連接電極2之狀 態。在此種連接狀態下，有關各元件晶片1〇間之配線雖可 達成微細化，但為了將半導體裝置100連接至未予圖示之 女裝基板’卻需使用形成於插入式基板1之周邊部之連接 端子τ。 為此’在插入式基板1上，連接端子τ之數愈增加，愈必 須擴張插入式基板面積’以設置該連接端子τ，因而造成 阻礙多晶片模組小型化之重要因素。 因此，本發明係為解決上述問題精心研發而成，其目的 在於提供可增進使用插入式基板之多晶片模組小型化之半 導體裝置及其製造方法。 -4- 本紙張尺度適财關家鮮(CNS) Α4規格(21GX 297公釐) -- 1294655 A7 --------- Β7 五、發明説明~) - [解決問題之手段] 為達成上述目的，本案發明之特徵係在將多數元件晶片 以倒裝片接合方式安裝於插入式基板上而構成多晶片模組 半導體装置中’设置貫通前述插入式基板之埋入電極， 使其一端側連接於以倒裝片接合方式安裝前述元件晶片之 連接電極，並在他端侧形成凸塊電極。 本案之另一發明之特徵係在將多數元件晶片以倒裝片接 η方式安裝於插入式基板上而構成多晶片模組之半導體裝 置之製造方法中，包含：第一步驟，其係將導體充填於穿 广又在構成前述插入式基板之母材之晶圓之接觸孔中而形成 埋入電極者；第二步驟，其係在其前述晶圓表面形成配 線，該配線包含連接於此埋入電極之一端侧之連接電極與 以倒裝片接合方式安裝前述元件晶片之連接電極者；第三 V驟，其係在此第二步驟所形成之連接電極上，以倒裝片 接合方式安裝前述多數元件晶片後，切削研磨前述晶圓之 背面側，直到前述埋入電極之他端露出為止，以形成前述 插入式基板者；及第四步驟，其係在藉此第三步驟而使他 端露出之埋入電極上設置凸塊電極者。 在本發明中，由於設置貫通插入式基板之埋入電極，使 其一端側連接於以倒裝片接合方式安裝前述元件晶片之連 接電極，並在他端侧形成凸塊電極，故可由插入式基板之 背面侧引出連接於安裝基板之電極，因此可實現多晶片模 組之小型化。 [發明之實施形態] 本紙張尺度適用中國國家標準((^]^8) Α4規格(210X297公釐) 1294655 A7 __B7 五、發明説明（3 ) 以下，參照圖式說明有關本發明之一實施形態。圖i係 表示依據該一實施形態所構成之半導體裝置1〇〇之構造之 剖面圖。在此圖中，在與前述以往例（參照圖5)共通之部 分附以同一符號，並省略其說明。 圖1所示之半導體裝置100與圖5所示之以往例不同之處 在於·採行設有貫通插入式基板1之埋入電極4，使其一端 側連接於以倒裝片接合方式安裝元件晶片1〇之連接電極 2，並經由設於他端側之凸塊電極5連接至未予圖示之安裝 基板之構造。採行此種構造時，由於不需要有形成於插入 式基板1之周邊部之連接端子T，故可使多晶片模組小型 化。 其次’參照圖2〜圖4說明有關上述構造所構成之半導體 裝置100之製造步驟。在依據本實施形態之製造步驟中， 首先如圖2(A)所示’在構成插入式基板1之母材，例如珍 基板形成之晶圓W表面侧，施行光阻膜R之圖案化處理， 以便在對應於後述接觸孔CH之處形成開口。其次，以此 光阻膜R為掩罩，對晶圓W施以蝕刻處理，藉以如圖2(B) 所示，形成深50〜100 μηι之接觸孔CH。接觸孔CH形成後， 除去光阻膜R，然後即可在晶、圓W表面上形成膜厚3〜4 μπι 之氧化膜3。 其次’如圖3(A)所示’例如用無電解電鑛方法，將銅、 金或此等之合金等良導體充填於接觸孔CH中而形成埋人 電極4。以此方式形成埋入電極4後，在氧化膜3或埋入電 極4上形成多數連接電極2 (參照圖3(B))。此後，如圖4(Α) -6 - 本紙張尺度適用中國國家標準((^^8) Α4規格(210 X 297公"" 1294655 A7 B7 五、發明説明（4 ) 所示，施行將各元件晶片10、10之凸塊l〇a連接於形成在 晶圓W上之連接電極2之倒裝片接合方式安裝。 倒裝片接合方式安裝後，如圖4(B)所示，利用背面研磨 動作切削研磨晶圓W之背面侧，直到埋入電極4之底面侧 露出為止，藉以形成薄膜化之插入式基板1。而後如圖 4(C)所示，在露出此插入式基板1背面侧之埋入電極4之端 面設置凸塊電極5後，將插入式基板丨切割而成各個晶片 時，即可形成圖1所示構造之多晶片模組之半導體裝置 100 〇 如以上所述，本發明由於採用設有貫通插入式基板J之 埋入電極4，使其一端側連接於以倒裝片接合方式安裝元 件晶片10之連接電極2，並經由設於他端侧之凸塊電極5連 接至未予圖示之女裝基板之構造。即，由於可由插入式基 板1之背面侧引出連接於安裝基板之電極，故可使多晶片 模組小型化。 [發明之功效] 根據本案之發明，由於設置貫通插入式基板之埋入電 極，使其-端側連接於以㈣片#合方式安裝前述元件晶 片之連接電極，並在他端侧形成凸塊電極。因&，可由插 入式基板之背面侧引出彡接於安裝基板之電極，故可使多 晶片模組小型化。 根據本案之發明’由於係將導體充填於穿設在構成插入 式基板之母材之晶圓之接觸孔中而形成埋入電極後，切削 研磨晶圓之背面侧，直到此埋入電極之他端露出為止，以 __ -7- t ϊϋ#^(〇Ν8) W(21〇X297^) ----- 1294655 A7
形成插入式基板，因此，由插入式基板之背面侧可容易形 成連接於女裝基板之電極，故對製造成本之降低大有助 益。 [圖式之簡單說明] 圖1係表示依據本發明一實施形態所構成之半導體裝置 100之構造之剖面圖。 圖2係表示半導體裝置1〇〇之製造步驟之說明圖。 圖3係表示半導體裝置1〇〇之製造步驟之說明圖。 圖4係表示半導體裝置10〇之製造步驟之說明圖。 圖5係表示以往例之說明圖β [元件符號之說明] 1…插入式基板、2…連接電極、3…氧化膜、4…埋入 電極、5…凸塊電極、1〇…元件晶片、i〇a…凸塊、τ…連 接端子、W…晶圓、CH…接觸孔、1 〇 〇…半導體裝置。 本紙張尺度適用中國國冢標準(CNS) A4規格(210X297公釐)

Claims (1)

1294655 A8 B8 C8 D8 六、申請專利範圍 1. 一種半導體裝置之製造方法，其特徵在於將多數元件 晶片以倒裝片接合方式安裝於插入式基板上而構成多 晶片模組，其包含： 第一步驟，其係將導體充填於穿設在構成前述插入 式基板之母材之晶圓之接觸孔中而形成埋入電極者； 第二步驟，其係在前述晶圓表面形成配線，該配線 包含連接於此埋入電極之一端側之連接電極與以倒裝 片接合方式安裝前述元件晶片之連接電極者； 第三步驟，其係在此第二步驟所形成之連接電極 上，以倒裝片接合方式安裝前述多數元件晶片後，切 削研磨前述晶圓之背面側，直到前述埋入電極之他端 路出為止’以形成前述插入式基板者；及 第四步驟，其係在藉此第三步驟而使他端露出之埋 入電極上設置凸塊電極者。 2·如申請專利範圍第1項之半導體裝置之製造方法，其令 上述插入式基板係由矽基板所形成者。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
TW091109776A 2001-05-14 2002-05-10 TWI294655B (zh)

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JP2001143045A JP3788268B2 (ja) 2001-05-14 2001-05-14 半導体装置の製造方法

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KR100825658B1 (ko) 2008-04-29
KR20040030610A (ko) 2004-04-09
JP3788268B2 (ja) 2006-06-21
US7064005B2 (en) 2006-06-20
WO2002101831A1 (fr) 2002-12-19
US20040115919A1 (en) 2004-06-17
JP2002343924A (ja) 2002-11-29

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