TWI286821B - Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same - Google Patents

Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same Download PDF

Info

Publication number
TWI286821B
TWI286821B TW092106464A TW92106464A TWI286821B TW I286821 B TWI286821 B TW I286821B TW 092106464 A TW092106464 A TW 092106464A TW 92106464 A TW92106464 A TW 92106464A TW I286821 B TWI286821 B TW I286821B
Authority
TW
Taiwan
Prior art keywords
thickness
substrate
buried oxide
layer
transistor
Prior art date
Application number
TW092106464A
Other languages
English (en)
Chinese (zh)
Other versions
TW200307346A (en
Inventor
Mark B Fuselier
Derick J Wristers
Andy C Wei
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200307346A publication Critical patent/TW200307346A/zh
Application granted granted Critical
Publication of TWI286821B publication Critical patent/TWI286821B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733Multi-gate TFTs
    • H10D30/6734Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW092106464A 2002-03-28 2003-03-24 Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same TWI286821B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/109,096 US6737332B1 (en) 2002-03-28 2002-03-28 Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same

Publications (2)

Publication Number Publication Date
TW200307346A TW200307346A (en) 2003-12-01
TWI286821B true TWI286821B (en) 2007-09-11

Family

ID=28673615

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092106464A TWI286821B (en) 2002-03-28 2003-03-24 Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same

Country Status (8)

Country Link
US (2) US6737332B1 (enExample)
EP (1) EP1490900A1 (enExample)
JP (1) JP2005522034A (enExample)
KR (1) KR20040102052A (enExample)
CN (1) CN1310306C (enExample)
AU (1) AU2002357862A1 (enExample)
TW (1) TWI286821B (enExample)
WO (1) WO2003083934A1 (enExample)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289552A (ja) * 2001-03-28 2002-10-04 Nippon Steel Corp Simox基板の製造方法およびsimox基板
US6946358B2 (en) * 2003-05-30 2005-09-20 International Business Machines Corporation Method of fabricating shallow trench isolation by ultra-thin SIMOX processing
US7935613B2 (en) 2003-12-16 2011-05-03 International Business Machines Corporation Three-dimensional silicon on oxide device isolation
EP1583143B1 (en) * 2004-03-29 2011-10-05 Imec Method of fabricating self-aligned source and drain contacts in a Double gate FET with controlled manufacturing of a thin Si or non-Si channel
US8450806B2 (en) * 2004-03-31 2013-05-28 International Business Machines Corporation Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US7382023B2 (en) * 2004-04-28 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fully depleted SOI multiple threshold voltage application
US7129138B1 (en) * 2005-04-14 2006-10-31 International Business Machines Corporation Methods of implementing and enhanced silicon-on-insulator (SOI) box structures
JP2006310661A (ja) * 2005-04-28 2006-11-09 Toshiba Corp 半導体基板および製造方法
JP4797495B2 (ja) * 2005-08-02 2011-10-19 セイコーエプソン株式会社 半導体装置の製造方法
US20070099372A1 (en) * 2005-10-31 2007-05-03 Sailesh Chittipeddi Device having active regions of different depths
KR100724199B1 (ko) * 2005-12-28 2007-05-31 동부일렉트로닉스 주식회사 에스오아이 소자의 섀로우 트렌치 분리막 형성 방법
US8278731B2 (en) * 2007-11-20 2012-10-02 Denso Corporation Semiconductor device having SOI substrate and method for manufacturing the same
KR101024763B1 (ko) * 2008-07-29 2011-03-24 주식회사 하이닉스반도체 반도체 소자의 리페어 방법
US8074897B2 (en) 2008-10-09 2011-12-13 Rain Bird Corporation Sprinkler with variable arc and flow rate
US8278167B2 (en) 2008-12-18 2012-10-02 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US8695900B2 (en) * 2009-05-29 2014-04-15 Rain Bird Corporation Sprinkler with variable arc and flow rate and method
US8925837B2 (en) * 2009-05-29 2015-01-06 Rain Bird Corporation Sprinkler with variable arc and flow rate and method
JP2011082443A (ja) * 2009-10-09 2011-04-21 Sumco Corp エピタキシャルウェーハおよびその製造方法
US9504209B2 (en) 2010-04-09 2016-11-29 Rain Bird Corporation Irrigation sprinkler nozzle
US8421156B2 (en) * 2010-06-25 2013-04-16 International Business Machines Corporation FET with self-aligned back gate
CN102148183B (zh) * 2011-03-10 2015-04-29 上海华虹宏力半导体制造有限公司 具有阶梯型氧化埋层的soi的形成方法
US8507989B2 (en) 2011-05-16 2013-08-13 International Business Machine Corporation Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance
CN102244080A (zh) * 2011-06-28 2011-11-16 上海宏力半导体制造有限公司 绝缘体上的硅衬底结构及器件
CN102244029A (zh) * 2011-06-28 2011-11-16 上海宏力半导体制造有限公司 绝缘体上的硅衬底制作工艺及绝缘体上的硅器件制作工艺
CN102339784B (zh) * 2011-09-28 2015-02-04 上海华虹宏力半导体制造有限公司 具有阶梯型氧化埋层的soi结构的制作方法
CN102354678B (zh) * 2011-09-28 2015-03-18 上海华虹宏力半导体制造有限公司 具有阶梯型氧化埋层的soi结构
US8940569B2 (en) * 2012-10-15 2015-01-27 International Business Machines Corporation Dual-gate bio/chem sensor
CN103311301B (zh) * 2013-05-09 2016-06-29 北京大学 一种抑制辐射引起背栅泄漏电流的soi器件及其制备方法
US10128269B2 (en) 2013-11-08 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods for a semiconductor structure having multiple semiconductor-device layers
CN105097711B (zh) * 2014-05-04 2018-03-30 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN108352357B (zh) * 2015-10-23 2023-02-17 应用材料公司 用于先进cmp及凹槽流的间隙填充膜改性
US10204909B2 (en) * 2015-12-22 2019-02-12 Varian Semiconductor Equipment Associates, Inc. Non-uniform gate oxide thickness for DRAM device
US10322423B2 (en) 2016-11-22 2019-06-18 Rain Bird Corporation Rotary nozzle
US11154877B2 (en) 2017-03-29 2021-10-26 Rain Bird Corporation Rotary strip nozzles
CN107634101A (zh) * 2017-09-21 2018-01-26 中国工程物理研究院电子工程研究所 具有三段式埋氧层的半导体场效应晶体管及其制造方法
US11059056B2 (en) 2019-02-28 2021-07-13 Rain Bird Corporation Rotary strip nozzles and deflectors
US11406999B2 (en) 2019-05-10 2022-08-09 Rain Bird Corporation Irrigation nozzle with one or more grit vents
US11247219B2 (en) 2019-11-22 2022-02-15 Rain Bird Corporation Reduced precipitation rate nozzle

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2797870B2 (ja) * 1991-12-28 1998-09-17 日産自動車株式会社 車両のドア構造
DE69332960T2 (de) * 1992-01-28 2004-05-13 Canon K.K. Halbleiteranordnung
JP2796012B2 (ja) * 1992-05-06 1998-09-10 株式会社東芝 半導体装置及びその製造方法
JP2739018B2 (ja) * 1992-10-21 1998-04-08 三菱電機株式会社 誘電体分離半導体装置及びその製造方法
JPH0778994A (ja) * 1993-09-07 1995-03-20 Hitachi Ltd Mos型半導体装置及びその製造方法
JP2842505B2 (ja) * 1994-02-03 1999-01-06 日本電気株式会社 薄膜トランジスタとその製造方法
JP3254889B2 (ja) * 1994-03-25 2002-02-12 ソニー株式会社 Mos型半導体記憶装置及びその製造方法
JP3427114B2 (ja) * 1994-06-03 2003-07-14 コマツ電子金属株式会社 半導体デバイス製造方法
JPH07335907A (ja) * 1994-06-14 1995-12-22 Sony Corp Soi基板に形成したcmosトランジスタおよびそのsoi基板の製造方法
JPH08153880A (ja) * 1994-09-29 1996-06-11 Toshiba Corp 半導体装置及びその製造方法
KR970052022A (ko) * 1995-12-30 1997-07-29 김주용 에스 오 아이 기판 제조방법
US6043166A (en) 1996-12-03 2000-03-28 International Business Machines Corporation Silicon-on-insulator substrates using low dose implantation
US6392277B1 (en) * 1997-11-21 2002-05-21 Hitachi, Ltd. Semiconductor device
US6069054A (en) * 1997-12-23 2000-05-30 Integrated Device Technology, Inc. Method for forming isolation regions subsequent to gate formation and structure thereof
AU2993600A (en) 1999-02-12 2000-08-29 Ibis Technology Corporation Patterned silicon-on-insulator devices
US5950094A (en) 1999-02-18 1999-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating fully dielectric isolated silicon (FDIS)
US6180487B1 (en) * 1999-10-25 2001-01-30 Advanced Micro Devices, Inc. Selective thinning of barrier oxide through masked SIMOX implant
US6326247B1 (en) * 2000-06-09 2001-12-04 Advanced Micro Devices, Inc. Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer
US6441436B1 (en) * 2000-11-29 2002-08-27 United Microelectronics Corp. SOI device and method of fabrication
US6515333B1 (en) * 2001-04-27 2003-02-04 Advanced Micro Devices, Inc. Removal of heat from SOI device
US6531375B1 (en) * 2001-09-18 2003-03-11 International Business Machines Corporation Method of forming a body contact using BOX modification

Also Published As

Publication number Publication date
KR20040102052A (ko) 2004-12-03
US6737332B1 (en) 2004-05-18
JP2005522034A (ja) 2005-07-21
WO2003083934A1 (en) 2003-10-09
CN1623226A (zh) 2005-06-01
AU2002357862A1 (en) 2003-10-13
US20040219761A1 (en) 2004-11-04
CN1310306C (zh) 2007-04-11
TW200307346A (en) 2003-12-01
EP1490900A1 (en) 2004-12-29

Similar Documents

Publication Publication Date Title
TWI286821B (en) Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same
CN102456579B (zh) 具有局部的极薄绝缘体上硅沟道区的半导体器件
TWI431760B (zh) 包括具有用於產生拉伸及壓縮應變之嵌入si/ge材料之nmos及pmos電晶體之半導體裝置
TWI390666B (zh) 絕緣體上半導體裝置之製造方法
TWI485854B (zh) 於三維電晶體中基於應變隔離材料之應變工程
US7678635B2 (en) Method of producing a transistor
US7419879B2 (en) Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same
US8115271B2 (en) Reducing device performance drift caused by large spacings between active regions
JP2010502015A (ja) 相補型シリコン・オン・インシュレータ(soi)接合型電界効果トランジスタ、及びその製造方法
JPS6318867B2 (enExample)
US20070187774A1 (en) Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure
CN101385133B (zh) 形成具有不对称电介质区域的半导体器件的方法及其结构
JP2000332237A (ja) 半導体装置の製造方法
CN100367462C (zh) 在体硅衬底具有增强自对准介电区域的soi半导体器件的制造方法
CN111986996B (zh) 改善自热效应的soi器件及其制备方法
CN101981674A (zh) 包括缩减高度的金属栅极堆栈的半导体器件及形成该半导体器件的方法
TW574746B (en) Method for manufacturing MOSFET with recessed channel
US8435861B2 (en) Method of manufacturing a semiconductor device having different kinds of insulating films with different thicknesses
JP2008042059A (ja) 半導体装置及びその製造方法
US9911832B2 (en) Method to improve gate dielectric quality for FinFET
TWI240414B (en) A double-gate field effect transistor (DGFET) structure and method of forming such a structure
US6228729B1 (en) MOS transistors having raised source and drain and interconnects
US7915128B2 (en) High voltage semiconductor devices
JPH09135029A (ja) Mis型半導体装置及びその製造方法
JPH04715A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees