KR20040102052A - 다중-두께 매립 산화물층 위에 형성된 반도체 디바이스 및그 제조 방법 - Google Patents

다중-두께 매립 산화물층 위에 형성된 반도체 디바이스 및그 제조 방법 Download PDF

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Publication number
KR20040102052A
KR20040102052A KR10-2004-7015051A KR20047015051A KR20040102052A KR 20040102052 A KR20040102052 A KR 20040102052A KR 20047015051 A KR20047015051 A KR 20047015051A KR 20040102052 A KR20040102052 A KR 20040102052A
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KR
South Korea
Prior art keywords
substrate
thickness
semiconductor device
buried oxide
oxide layer
Prior art date
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Ceased
Application number
KR10-2004-7015051A
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English (en)
Korean (ko)
Inventor
푸셀리어마크비.
리스터즈데릭제이.
웨이앤디씨.
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20040102052A publication Critical patent/KR20040102052A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR10-2004-7015051A 2002-03-28 2002-12-17 다중-두께 매립 산화물층 위에 형성된 반도체 디바이스 및그 제조 방법 Ceased KR20040102052A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/109,096 US6737332B1 (en) 2002-03-28 2002-03-28 Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same
US10/109,096 2002-03-28
PCT/US2002/040213 WO2003083934A1 (en) 2002-03-28 2002-12-17 Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same

Publications (1)

Publication Number Publication Date
KR20040102052A true KR20040102052A (ko) 2004-12-03

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Application Number Title Priority Date Filing Date
KR10-2004-7015051A Ceased KR20040102052A (ko) 2002-03-28 2002-12-17 다중-두께 매립 산화물층 위에 형성된 반도체 디바이스 및그 제조 방법

Country Status (8)

Country Link
US (2) US6737332B1 (enExample)
EP (1) EP1490900A1 (enExample)
JP (1) JP2005522034A (enExample)
KR (1) KR20040102052A (enExample)
CN (1) CN1310306C (enExample)
AU (1) AU2002357862A1 (enExample)
TW (1) TWI286821B (enExample)
WO (1) WO2003083934A1 (enExample)

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KR100724199B1 (ko) * 2005-12-28 2007-05-31 동부일렉트로닉스 주식회사 에스오아이 소자의 섀로우 트렌치 분리막 형성 방법
WO2010080277A1 (en) * 2008-12-18 2010-07-15 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US7785936B2 (en) 2008-07-29 2010-08-31 Hynix Semiconductor Inc. Method for repair of semiconductor device
KR20150053703A (ko) * 2013-11-08 2015-05-18 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 다수의 반도체 디바이스층을 갖는 반도체 구조체를 위한 시스템 및 방법
KR20180061389A (ko) * 2015-10-23 2018-06-07 어플라이드 머티어리얼스, 인코포레이티드 진보된 cmp 및 리세스 플로우를 위한 갭필 필름 수정

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US7382023B2 (en) * 2004-04-28 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fully depleted SOI multiple threshold voltage application
US7129138B1 (en) * 2005-04-14 2006-10-31 International Business Machines Corporation Methods of implementing and enhanced silicon-on-insulator (SOI) box structures
JP2006310661A (ja) * 2005-04-28 2006-11-09 Toshiba Corp 半導体基板および製造方法
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CN105097711B (zh) * 2014-05-04 2018-03-30 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724199B1 (ko) * 2005-12-28 2007-05-31 동부일렉트로닉스 주식회사 에스오아이 소자의 섀로우 트렌치 분리막 형성 방법
US7785936B2 (en) 2008-07-29 2010-08-31 Hynix Semiconductor Inc. Method for repair of semiconductor device
KR101024763B1 (ko) * 2008-07-29 2011-03-24 주식회사 하이닉스반도체 반도체 소자의 리페어 방법
WO2010080277A1 (en) * 2008-12-18 2010-07-15 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US8278167B2 (en) 2008-12-18 2012-10-02 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US8704286B2 (en) 2008-12-18 2014-04-22 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US9129848B2 (en) 2008-12-18 2015-09-08 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
KR20150053703A (ko) * 2013-11-08 2015-05-18 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 다수의 반도체 디바이스층을 갖는 반도체 구조체를 위한 시스템 및 방법
US10128269B2 (en) 2013-11-08 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods for a semiconductor structure having multiple semiconductor-device layers
US10734411B2 (en) 2013-11-08 2020-08-04 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for a semiconductor structure having multiple semiconductor-device layers
US12087777B2 (en) 2013-11-08 2024-09-10 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for a semiconductor structure having multiple semiconductor-device layers
KR20180061389A (ko) * 2015-10-23 2018-06-07 어플라이드 머티어리얼스, 인코포레이티드 진보된 cmp 및 리세스 플로우를 위한 갭필 필름 수정

Also Published As

Publication number Publication date
EP1490900A1 (en) 2004-12-29
US6737332B1 (en) 2004-05-18
CN1623226A (zh) 2005-06-01
WO2003083934A1 (en) 2003-10-09
CN1310306C (zh) 2007-04-11
JP2005522034A (ja) 2005-07-21
TW200307346A (en) 2003-12-01
TWI286821B (en) 2007-09-11
AU2002357862A1 (en) 2003-10-13
US20040219761A1 (en) 2004-11-04

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