JP2005522034A - 複数の厚みを持つ埋め込み酸化膜上に形成される半導体装置およびその製造方法 - Google Patents
複数の厚みを持つ埋め込み酸化膜上に形成される半導体装置およびその製造方法 Download PDFInfo
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Abstract
Description
本発明は様々な変形および代替の形態をとりうるが、その特定の実施形態を例示のために図面に示し、本明細書において詳細に説明する。しかしながら、特定の実施形態についての本明細書中の説明は、開示された特定の形態に本発明を限定しようとするものではなく、むしろ反対に、添付の特許請求の範囲に規定される本発明の精神および範囲の範疇に入る、すべての変形物、均等物および代替物を含むことを意図している、ことを理解してもらいたい。
Claims (16)
- バルク基板(12)と、
前記バルク基板(12)上に形成される複数の厚みを持つ埋め込み酸化膜(20)と、
前記複数の厚みを持つ埋め込み酸化膜(20)上に形成される活性層とを含む半導体デバイスであって、
前記半導体デバイスは前記複数の厚みを持つ埋め込み酸化膜(20)上の活性層(21)に形成される半導体デバイス。 - 前記半導体デバイスはトランジスタである、請求項1記載の半導体デバイス。
- 前記活性層はシリコンを含んで構成される、請求項1記載の半導体デバイス。
- 前記埋め込み酸化膜は二酸化シリコンを含んで構成される、請求項1記載の半導体デバイス。
- 前記複数の厚みを持つ埋め込み酸化膜(20)は、2つの第2部分(20A)の間に位置する第1部分(20B)を含み、前記第1部分(20B)はある厚みを有し、前記第2部分(20A)のそれぞれはある厚みを有し、前記第1部分(20B)の前記厚みは前記第2部分(20A)前記厚みよりも薄い、請求項1記載の半導体デバイス。
- 前記半導体デバイスはチャネル領域(23)を持つトランジスタであって、前記チャネル領域23の少なくとも一部は、前記埋め込み酸化膜(20)の残りの部分の厚みよりも薄い厚さを持つ前記埋め込み酸化膜(20)の部分の上方に位置している、請求項1記載の半導体デバイス。
- 前記半導体デバイスはゲート電極(16)を持つトランジスタであって、前記複数の厚みを持つ埋め込み酸化膜(20)は2つの第2部分(20A)の間に位置する第1部分(20B)を含み、前記第1部分(20B)はある厚みを有し、前記第2部分(20A)のそれぞれはある厚みを有し、前記第1部分(20B)の前記厚みは前記第2部分(20A)厚みよりも薄く、前記第1部分20Bは少なくとも部分的に前記ゲート電極(16)の下方に位置している、請求項1記載の半導体デバイス。
- 前記半導体デバイスはゲート電極(16)を持つトランジスタであって、前記複数の厚みを持つ埋め込み酸化膜(20)は2つの第2部分(20A)の間に位置する第1部分(20B)を含み、前記第1部分(20B)はある厚みを有し、前記第2部分(20A)のそれぞれはある厚みを有し、前記第1部分(20B)の前記厚みは前記第2部分(20A)厚みよりも薄く、前記第1部分20Bは前記ゲート電極(16)に対して実質的に位置合わせされている、請求項1記載の半導体デバイス。
- シリコン基板(40)に第1酸素イオン注入プロセス(42)を実行するステップと、
前記第1酸素イオン注入プロセス(42)の後で、前記基板(40)上にマスキング層(44)を形成するステップと、
前記マスキング層(44)を介して、前記基板(40)に第2酸素イオン注入プロセス(46)を実行するステップと、
前記基板(40)に複数の厚みを持つ埋め込み酸化膜(20)を形成するために、前記基板(40)において少なくとも1つの加熱処理を実行するステップとを含む、半導体デバイスを形成する方法。 - 前記第1酸素イオン注入プロセス(42)を、約10−40keVの範囲のエネルギーレベルにおいて、約1017−1018イオン/cm2の範囲の酸素ドーパント薬量を用いて実行する、請求項9記載の方法。
- 前記第2酸素イオン注入プロセス(46)を、約30−150keVの範囲のエネルギーレベルにおいて、約1017−1018イオン/cm2の範囲の酸素ドーパント薬量を用いて実行する、請求項9記載の方法。
- 基板(40)上にマスキング層(44)を形成するステップと、
前記マスキング層(44)を介して前記基板(40)に第1酸素イオン注入プロセス(46)を実行するステップと、
前記マスキング層(44)を取り除くステップと、
前記マスキング層(44)を取り除いた後に前記基板(40)に第2酸素イオン注入プロセス(42)を実行するステップと、
前記基板(40)に複数の厚みを持つ埋め込み酸化膜(20)を形成するために前記基板(40)において少なくとも1つの加熱処理を実行するステップとを含む、半導体デバイスを形成する方法。 - 前記第2酸素イオン注入プロセス(42)を、約10−40keVの範囲のエネルギーレベルにおいて、約1017−1018イオン/cm2の範囲の酸素ドーパント薬量を用いて実行する、請求項12記載の方法。
- 前記第1酸素イオン注入プロセス(46)を、約10−40keVの範囲のエネルギーレベルにおいて、約1017−1018イオン/cm2の範囲の酸素ドーパント濃度を用いて実行する、請求項12記載の方法。
- 第1基板(50)上に二酸化シリコン層(52)を形成するステップと、
前記二酸化シリコン層(52)の一部の上にマスキング層(54)を形成するステップと、
前記マスキング層(54)のそれぞれの側面に近接して、前記基板(50)に凹部(55)をエッチングするための少なくとも1つのエッチングプロセスを実行するステップと、
前記マスキング層(54)を取り除くステップと、
少なくとも前記凹部(55)に二酸化シリコンを形成するための酸化プロセスまたはデポジションプロセスのいずれか一方を実行するステップと、
少なくとも前記凹部(55)に形成された前記二酸化シリコンに、少なくとも1つの化学機械研磨処理を実行するステップと、
少なくとも前記凹部(55)に形成された前記二酸化シリコンに第2基板(58)を貼り付けるステップと、
前記第2基板(58)の一部を取り除くステップとを含む、方法。 - 前記マスキング層(54)のそれぞれの側面に近接して、前記基板(50)に凹部(55)をエッチングするための少なくとも1つのエッチングプロセスを実行するステップは、前記マスキング層(54)のそれぞれの側面に近接して前記基板(50)に、約10−50nmの範囲の深さを持つ凹部(55)をエッチングするための少なくとも1つのエッチングプロセスを実行するステップを含む、請求項15記載の方法。
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US10/109,096 US6737332B1 (en) | 2002-03-28 | 2002-03-28 | Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same |
PCT/US2002/040213 WO2003083934A1 (en) | 2002-03-28 | 2002-12-17 | Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same |
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JP (1) | JP2005522034A (ja) |
KR (1) | KR20040102052A (ja) |
CN (1) | CN1310306C (ja) |
AU (1) | AU2002357862A1 (ja) |
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JP2007042782A (ja) * | 2005-08-02 | 2007-02-15 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
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JP2002289552A (ja) * | 2001-03-28 | 2002-10-04 | Nippon Steel Corp | Simox基板の製造方法およびsimox基板 |
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Also Published As
Publication number | Publication date |
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WO2003083934A1 (en) | 2003-10-09 |
EP1490900A1 (en) | 2004-12-29 |
TWI286821B (en) | 2007-09-11 |
CN1310306C (zh) | 2007-04-11 |
CN1623226A (zh) | 2005-06-01 |
TW200307346A (en) | 2003-12-01 |
US20040219761A1 (en) | 2004-11-04 |
US6737332B1 (en) | 2004-05-18 |
AU2002357862A1 (en) | 2003-10-13 |
KR20040102052A (ko) | 2004-12-03 |
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