JP2008060497A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】第1半導体面11とこの面につながる面であり、かつ該第1半導体面に対して傾斜を有する第2半導体面12を有する半導体領域10と、第1、第2半導体面11、12上にゲート絶縁膜21を介して第1、第2半導体面11、12境界上に設けられたゲート電極22と、ゲート絶縁膜21を挟んでゲート電極22と第1半導体面11内でオーバーラップするように半導体領域10に形成されたソース不純物領域23と、少なくとも第2半導体面12直下の半導体領域10に設けられたドレイン不純物領域24と、ドレイン不純物領域24と半導体領域10との接合界面Jdが、ソース不純物領域23と半導体領域10との接合界面Jsより、第1、第2半導体面11、12の境界Bに近い状態に形成されている。
【選択図】図1
Description
Claims (12)
- 第1半導体面と、該第1半導体面につながる面であり、かつ該第1半導体面に対して傾斜を有する第2半導体面とを有する半導体領域と、
前記第1半導体面上と前記第2半導体面上に形成されたゲート絶縁膜と、
前記第1半導体面と前記第2半導体面の境界上を含む前記ゲート絶縁膜上に設けられたゲート電極と、
前記ゲート絶縁膜を挟んで前記ゲート電極と前記第1半導体面内でオーバーラップするように前記半導体領域に形成されたソース不純物領域と、
少なくとも前記第2半導体面の直下の前記半導体領域に形成されたドレイン不純物領域と、
前記ドレイン不純物領域と前記半導体領域との接合界面が、前記ソース不純物領域と前記半導体領域との接合界面より、前記第1半導体面と前記第2半導体面との境界に近い状態に形成されている
ことを特徴とする半導体装置。 - 前記ドレイン不純物領域が、前記第1半導体面より上方にせり上げられた半導体層を有している
ことを特徴とする請求項1記載の半導体装置。 - 前記半導体層が前記第1半導体面に形成されたエピタキシャル成長層である
ことを特徴とする請求項2記載の半導体装置。 - 前記ドレイン不純物領域が、前記ゲート絶縁膜を挟んで前記ゲート電極と前記第2半導体面内でオーバーラップする
ことを特徴とする請求項1に記載の半導体装置。 - 半導体基板上にダミーゲート絶縁膜を介してダミーゲートを形成する工程と、
前記ダミーゲートの両側の前記半導体基板にソース・ドレイン不純物領域を形成する工程と、
前記ダミーゲートの両側の前記半導体基板上にエクステンション領域を形成する工程と、
前記ダミーゲート直下のソース側にソース不純物領域のオーバラップ領域を形成する工程と、
前記ダミーゲートを除去し、該除去領域に露出した前記ダミーゲート絶縁膜を除去する工程と、
前記除去領域に露出した前記半導体基板にリセス形状を形成する工程と、
前記リセス形状を形成した前記半導体基板上にゲート絶縁膜とゲート電極とを順次形成する工程と
を備えたことを特徴とする半導体装置の製造方法。 - 前記オーバラップ領域を形成する工程は、前記エクステンション領域を形成した後に行われる
ことを特徴とする請求項3記載の半導体装置の製造方法。 - 前記オーバラップ領域を形成する工程は、前記ダミーゲートを形成した直後に行われる
ことを特徴とする請求項3記載の半導体装置の製造方法。 - 前記オーバラップ領域を形成する工程は、前記ダミーゲートの側壁にスペーサー絶縁膜を形成した後に行われる
ことを特徴とする請求項3記載の半導体装置の製造方法。 - 前記エクステンション領域を前記半導体基板と異なる格子定数を有するエピタキシャル成長層で形成し、
前記エピタキシャル成長層によって前記ゲート電極直下の前記半導体基板に圧縮応力または引張応力を生じさせる
ことを特徴とする請求項3記載の半導体装置の製造方法。 - 絶縁ゲート型電界効果トランジスタをセルの選択トランジスタに用いたスタティックランダムアクセスメモリからなる半導体装置であって、
前記絶縁ゲート型電界効果トランジスタは、
第1半導体面と、該第1半導体面につながる面であり、かつ該第1半導体面に対して傾斜を有する第2半導体面とを有する半導体領域と、
前記第1半導体面上と前記第2半導体面上に形成されたゲート絶縁膜と、
前記第1半導体面と前記第2半導体面の境界上を含む前記ゲート絶縁膜上に設けられたゲート電極と、
前記ゲート絶縁膜を挟んで前記ゲート電極と前記第1半導体面内でオーバーラップするように前記半導体領域に形成されたソース不純物領域と、
少なくとも前記第2半導体面の直下の前記半導体領域に設けられたドレイン不純物領域とを備え、
前記ドレイン不純物領域と前記半導体領域との接合界面が、前記ソース不純物領域と前記半導体領域との接合界面より、前記第1半導体面と前記第2半導体面との境界に近い状態に形成されていて、
前記ソース不純物領域側をビット線につなぎ、
前記ドレイン不純物領域側をセルトランジスタのゲート電極につないだ
ことを特徴とする半導体装置。 - 前記スタティックランダムアクセスメモリのプルアップトランジスタのドレイン不純物領域側を電源線につないだ
ことを特徴とする請求項10記載の半導体装置。 - 前記スタティックランダムアクセスメモリのプルアップトランジスタのソース不純物領域側を電源線につないだ
ことを特徴とする請求項10記載の半導体装置。
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TW096131114A TWI360227B (en) | 2006-09-04 | 2007-08-22 | Semiconductor device and method of manufacturing s |
US11/846,802 US7605424B2 (en) | 2006-09-04 | 2007-08-29 | Semiconductor device and method of manufacturing semiconductor device |
KR1020070089432A KR101398497B1 (ko) | 2006-09-04 | 2007-09-04 | 반도체 장치 및 반도체 장치의 제조 방법 |
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JP5944266B2 (ja) | 2012-08-10 | 2016-07-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
WO2017171752A1 (en) * | 2016-03-30 | 2017-10-05 | Intel Corporation | Transistors including retracted raised source/drain to reduce parasitic capacitances |
KR102277610B1 (ko) * | 2017-06-29 | 2021-07-14 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
CN110970500B (zh) * | 2018-09-28 | 2024-06-07 | 长鑫存储技术有限公司 | 晶体管及其形成方法、半导体器件 |
JP7319617B2 (ja) | 2020-05-21 | 2023-08-02 | 株式会社東芝 | 半導体装置 |
KR102379156B1 (ko) * | 2020-09-03 | 2022-03-25 | 현대모비스 주식회사 | 전력 반도체 소자 및 그 제조 방법 |
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JP4631833B2 (ja) | 2011-02-16 |
KR20080021569A (ko) | 2008-03-07 |
TW200818507A (en) | 2008-04-16 |
US20080054352A1 (en) | 2008-03-06 |
US7605424B2 (en) | 2009-10-20 |
TWI360227B (en) | 2012-03-11 |
KR101398497B1 (ko) | 2014-05-23 |
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