TWI277196B - Semiconductor integrated circuit apparatus - Google Patents

Semiconductor integrated circuit apparatus Download PDF

Info

Publication number
TWI277196B
TWI277196B TW092101497A TW92101497A TWI277196B TW I277196 B TWI277196 B TW I277196B TW 092101497 A TW092101497 A TW 092101497A TW 92101497 A TW92101497 A TW 92101497A TW I277196 B TWI277196 B TW I277196B
Authority
TW
Taiwan
Prior art keywords
wiring
power supply
address signal
potential side
side power
Prior art date
Application number
TW092101497A
Other languages
English (en)
Chinese (zh)
Other versions
TW200305271A (en
Inventor
Toshima Toyoshima
Atsuhiro Hayashi
Takemi Negishi
Takashi Uehara
Original Assignee
Hitachi Ltd
Hitachi Ulsi Sys Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Ulsi Sys Co Ltd filed Critical Hitachi Ltd
Publication of TW200305271A publication Critical patent/TW200305271A/zh
Application granted granted Critical
Publication of TWI277196B publication Critical patent/TWI277196B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Static Random-Access Memory (AREA)
TW092101497A 2002-02-12 2003-01-23 Semiconductor integrated circuit apparatus TWI277196B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002034651A JP2003243538A (ja) 2002-02-12 2002-02-12 半導体集積回路装置

Publications (2)

Publication Number Publication Date
TW200305271A TW200305271A (en) 2003-10-16
TWI277196B true TWI277196B (en) 2007-03-21

Family

ID=27654923

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092101497A TWI277196B (en) 2002-02-12 2003-01-23 Semiconductor integrated circuit apparatus

Country Status (5)

Country Link
US (1) US6835971B2 (enExample)
JP (1) JP2003243538A (enExample)
KR (1) KR20030068436A (enExample)
CN (1) CN100334724C (enExample)
TW (1) TWI277196B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003264256A (ja) * 2002-03-08 2003-09-19 Hitachi Ltd 半導体装置
DE102004015654A1 (de) * 2003-04-02 2004-10-21 Luk Lamellen Und Kupplungsbau Beteiligungs Kg Endstufe zum Ansteuern einer elektrischen Maschine
US7423343B2 (en) * 2003-08-05 2008-09-09 Semiconductor Energy Laboratory Co., Ltd. Wiring board, manufacturing method thereof, semiconductor device and manufacturing method thereof
JP4904670B2 (ja) * 2004-06-02 2012-03-28 富士通セミコンダクター株式会社 半導体装置
TWI425604B (zh) * 2004-07-26 2014-02-01 倫巴士公司 半導體裝置
JP4674850B2 (ja) * 2005-02-25 2011-04-20 ルネサスエレクトロニクス株式会社 半導体装置
US7313775B2 (en) * 2005-04-06 2007-12-25 Lsi Corporation Integrated circuit with relocatable processor hardmac
JP5038616B2 (ja) 2005-11-14 2012-10-03 ルネサスエレクトロニクス株式会社 半導体集積回路
JP2007207301A (ja) * 2006-01-31 2007-08-16 Ricoh Co Ltd 半導体記憶装置
JP2010192013A (ja) * 2009-02-16 2010-09-02 Panasonic Corp 半導体集積回路
TWI439704B (zh) * 2011-04-22 2014-06-01 國立交通大學 凸塊接點之電阻測量結構及包含其之封裝基板
CN102931167A (zh) * 2012-10-25 2013-02-13 上海新储集成电路有限公司 一种在堆叠芯片之间传输驱动大电流信号的方法
JP2020145231A (ja) * 2019-03-04 2020-09-10 キオクシア株式会社 半導体装置およびその製造方法
TWI822006B (zh) * 2022-04-22 2023-11-11 創意電子股份有限公司 捕獲電阻電壓降的分析器以及其分析方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3285919B2 (ja) 1992-02-05 2002-05-27 株式会社東芝 半導体装置
JP3362545B2 (ja) 1995-03-09 2003-01-07 ソニー株式会社 半導体装置の製造方法
US5547740A (en) * 1995-03-23 1996-08-20 Delco Electronics Corporation Solderable contacts for flip chip integrated circuit devices
JP2780674B2 (ja) * 1995-06-20 1998-07-30 日本電気株式会社 不揮発性半導体記憶装置
US5654860A (en) * 1995-08-16 1997-08-05 Micron Technology, Inc. Well resistor for ESD protection of CMOS circuits
JPH10149699A (ja) * 1996-11-18 1998-06-02 Mitsubishi Electric Corp 半導体回路装置
US5946236A (en) * 1997-03-31 1999-08-31 Sanyo Electric Co., Ltd. Non-volatile semiconductor memory device and method for writing information therein
JP3389856B2 (ja) * 1998-03-24 2003-03-24 日本電気株式会社 半導体装置
JP3727191B2 (ja) * 1999-02-18 2005-12-14 松下電器産業株式会社 半導体記憶装置
JP2002539611A (ja) * 1999-03-09 2002-11-19 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 不揮発性メモリを有する半導体装置
US6483176B2 (en) * 1999-12-22 2002-11-19 Kabushiki Kaisha Toshiba Semiconductor with multilayer wiring structure that offer high speed performance
JP4058234B2 (ja) * 1999-12-22 2008-03-05 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
US20030151100A1 (en) 2003-08-14
CN1438703A (zh) 2003-08-27
JP2003243538A (ja) 2003-08-29
KR20030068436A (ko) 2003-08-21
TW200305271A (en) 2003-10-16
CN100334724C (zh) 2007-08-29
US6835971B2 (en) 2004-12-28

Similar Documents

Publication Publication Date Title
US7320482B2 (en) Semiconductor integrated circuit device
TWI277196B (en) Semiconductor integrated circuit apparatus
CN110998825B (zh) 利用外部端子进行写入
US20100230780A1 (en) Semiconductor device
US8806411B2 (en) Semiconductor device based on power gating in multilevel wiring structure
US6828842B2 (en) Semiconductor integrated circuit device
JPH10163429A (ja) 半導体装置
US7292493B1 (en) Semiconductor device with electrically broken fuse and its manufacture method
US9362908B2 (en) Semiconductor apparatus including output buffer
US6897496B2 (en) Semiconductor device, a method of manufacturing the same and storage media
JP2915312B2 (ja) 半導体集積回路装置
JP4450380B2 (ja) メモリを内蔵した半導体集積回路
JP3294590B2 (ja) 半導体装置
JPH04318392A (ja) 半導体集積回路装置
JPWO2000065650A1 (ja) 半導体装置およびその製造方法
JP3524531B2 (ja) 半導体装置
JPH10209371A (ja) Ｉｃメモリ
US20250226024A1 (en) Semiconductor device
JP3786660B2 (ja) 半導体装置
JP2023100547A (ja) 半導体装置及び半導体記憶装置
JP2003110030A (ja) 半導体装置
JP2007027314A (ja) 半導体集積回路装置
JPH11288591A (ja) 半導体装置
WO2014112476A1 (ja) 半導体記憶装置
JPH11288586A (ja) 半導体装置

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees