TWI265590B - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor deviceInfo
- Publication number
- TWI265590B TWI265590B TW092135531A TW92135531A TWI265590B TW I265590 B TWI265590 B TW I265590B TW 092135531 A TW092135531 A TW 092135531A TW 92135531 A TW92135531 A TW 92135531A TW I265590 B TWI265590 B TW I265590B
- Authority
- TW
- Taiwan
- Prior art keywords
- interval
- silicon oxide
- film
- oxide film
- implant angle
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 3
- 239000007943 implant Substances 0.000 abstract 3
- 239000012535 impurity Substances 0.000 abstract 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003143438A JP4578785B2 (ja) | 2003-05-21 | 2003-05-21 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200426978A TW200426978A (en) | 2004-12-01 |
| TWI265590B true TWI265590B (en) | 2006-11-01 |
Family
ID=33447507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092135531A TWI265590B (en) | 2003-05-21 | 2003-12-16 | Method of manufacturing semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| US (4) | US6998319B2 (zh) |
| JP (1) | JP4578785B2 (zh) |
| KR (1) | KR100533553B1 (zh) |
| CN (2) | CN1324687C (zh) |
| DE (1) | DE102004009597A1 (zh) |
| TW (1) | TWI265590B (zh) |
Families Citing this family (58)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100414872B1 (ko) * | 2001-08-29 | 2004-01-13 | 주식회사 하이닉스반도체 | 반도체소자 및 그 제조 방법 |
| US7151040B2 (en) * | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
| US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
| US7115525B2 (en) | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
| US7655387B2 (en) * | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
| US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
| US7253118B2 (en) | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
| US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
| US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
| US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
| US7429536B2 (en) | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
| US7560390B2 (en) | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
| US7396781B2 (en) * | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
| US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
| US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
| US7413981B2 (en) | 2005-07-29 | 2008-08-19 | Micron Technology, Inc. | Pitch doubled circuit layout |
| US8123968B2 (en) | 2005-08-25 | 2012-02-28 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
| US7816262B2 (en) | 2005-08-30 | 2010-10-19 | Micron Technology, Inc. | Method and algorithm for random half pitched interconnect layout with constant spacing |
| US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
| US7829262B2 (en) | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
| US7322138B2 (en) * | 2005-08-31 | 2008-01-29 | Southern Imperial, Inc. | Shelf edge sign holder |
| US7776744B2 (en) | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
| US7557032B2 (en) | 2005-09-01 | 2009-07-07 | Micron Technology, Inc. | Silicided recessed silicon |
| US7687342B2 (en) | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
| US7759197B2 (en) * | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
| US7572572B2 (en) | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
| US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
| US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
| US7842558B2 (en) | 2006-03-02 | 2010-11-30 | Micron Technology, Inc. | Masking process for simultaneously patterning separate regions |
| US7476933B2 (en) | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
| US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
| US8003310B2 (en) * | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
| US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
| US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
| US7723009B2 (en) | 2006-06-02 | 2010-05-25 | Micron Technology, Inc. | Topography based patterning |
| US7611980B2 (en) | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
| US7666578B2 (en) | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
| US8129289B2 (en) | 2006-10-05 | 2012-03-06 | Micron Technology, Inc. | Method to deposit conformal low temperature SiO2 |
| JP5264237B2 (ja) * | 2007-05-15 | 2013-08-14 | キヤノン株式会社 | ナノ構造体およびナノ構造体の製造方法 |
| US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
| US8563229B2 (en) | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
| CN101373326B (zh) * | 2007-08-24 | 2012-01-18 | 南亚科技股份有限公司 | 光掩模 |
| US7737039B2 (en) | 2007-11-01 | 2010-06-15 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
| US7659208B2 (en) | 2007-12-06 | 2010-02-09 | Micron Technology, Inc | Method for forming high density patterns |
| US7790531B2 (en) | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
| JP2009158622A (ja) | 2007-12-25 | 2009-07-16 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
| US8030218B2 (en) | 2008-03-21 | 2011-10-04 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
| US8076208B2 (en) | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
| US8492282B2 (en) | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
| JP5591016B2 (ja) * | 2010-08-09 | 2014-09-17 | ルネサスエレクトロニクス株式会社 | 半導体装置、及び半導体装置の製造方法 |
| CN102832133B (zh) * | 2012-08-29 | 2014-12-03 | 北京大学 | 在体硅上制备独立双栅FinFET的方法 |
| US9515172B2 (en) | 2014-01-28 | 2016-12-06 | Samsung Electronics Co., Ltd. | Semiconductor devices having isolation insulating layers and methods of manufacturing the same |
| KR102115552B1 (ko) * | 2014-01-28 | 2020-05-27 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| US9461045B1 (en) | 2015-06-25 | 2016-10-04 | Micron Technology, Inc. | Semiconductor devices |
| CN108665924B (zh) * | 2018-05-09 | 2021-03-02 | 上海交通大学 | 阵列化硅基可编程光存储芯片 |
| US10734489B2 (en) * | 2018-07-31 | 2020-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming semiconductor device structure with metal silicide layer |
| US11710642B2 (en) | 2021-03-23 | 2023-07-25 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
| CN113078057B (zh) * | 2021-03-23 | 2022-09-23 | 长鑫存储技术有限公司 | 半导体结构及其制作方法 |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4597824A (en) * | 1983-11-11 | 1986-07-01 | Kabushiki Kaisha Toshiba | Method of producing semiconductor device |
| US4845047A (en) * | 1987-06-25 | 1989-07-04 | Texas Instruments Incorporated | Threshold adjustment method for an IGFET |
| US5364810A (en) * | 1992-07-28 | 1994-11-15 | Motorola, Inc. | Methods of forming a vertical field-effect transistor and a semiconductor memory cell |
| JPH0778988A (ja) * | 1993-09-09 | 1995-03-20 | Nec Corp | 半導体装置の製造方法 |
| JPH07122741A (ja) * | 1993-10-21 | 1995-05-12 | Hitachi Ltd | 半導体装置の製造方法 |
| US5643822A (en) | 1995-01-10 | 1997-07-01 | International Business Machines Corporation | Method for forming trench-isolated FET devices |
| JPH09237829A (ja) | 1996-03-01 | 1997-09-09 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| JPH09307102A (ja) * | 1996-05-15 | 1997-11-28 | Denso Corp | 半導体装置 |
| US5677217A (en) * | 1996-08-01 | 1997-10-14 | Vanguard International Semiconductor Corporation | Method for fabricating a mosfet device, with local channel doping and a titanium silicide gate |
| JPH1065153A (ja) | 1996-08-15 | 1998-03-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| JP3638778B2 (ja) * | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
| US6040208A (en) * | 1997-08-29 | 2000-03-21 | Micron Technology, Inc. | Angled ion implantation for selective doping |
| JP2000114469A (ja) * | 1998-10-08 | 2000-04-21 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| US6162693A (en) * | 1999-09-02 | 2000-12-19 | Micron Technology, Inc. | Channel implant through gate polysilicon |
| JP2002009173A (ja) * | 2000-06-26 | 2002-01-11 | Toshiba Corp | 半導体装置の製造方法 |
| KR100327348B1 (en) * | 2000-07-26 | 2002-03-06 | Samsung Electronics Co Ltd | Semiconductor capable of decreasing junction leakage current and narrow width effect and fabricating method thereof |
| JP2002083941A (ja) * | 2000-09-06 | 2002-03-22 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| JP4832629B2 (ja) * | 2000-10-04 | 2011-12-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP4039854B2 (ja) | 2000-12-28 | 2008-01-30 | 三洋電機株式会社 | 半導体装置の製造方法 |
| JP2002299475A (ja) * | 2001-03-30 | 2002-10-11 | Toshiba Corp | 半導体装置及びその製造方法 |
| JP2004063527A (ja) * | 2002-07-25 | 2004-02-26 | Elpida Memory Inc | 半導体記憶装置およびその製造方法 |
| JP2004207457A (ja) * | 2002-12-25 | 2004-07-22 | Renesas Technology Corp | 半導体装置及び半導体装置の製造方法 |
-
2003
- 2003-05-21 JP JP2003143438A patent/JP4578785B2/ja not_active Expired - Fee Related
- 2003-12-09 US US10/730,099 patent/US6998319B2/en not_active Expired - Fee Related
- 2003-12-16 TW TW092135531A patent/TWI265590B/zh not_active IP Right Cessation
- 2003-12-18 KR KR10-2003-0093271A patent/KR100533553B1/ko not_active IP Right Cessation
-
2004
- 2004-02-27 CN CNB2004100082351A patent/CN1324687C/zh not_active Expired - Fee Related
- 2004-02-27 DE DE102004009597A patent/DE102004009597A1/de not_active Withdrawn
- 2004-02-27 CN CN200710104006.3A patent/CN101055842B/zh not_active Expired - Fee Related
-
2005
- 2005-12-02 US US11/292,360 patent/US7244655B2/en not_active Expired - Lifetime
-
2007
- 2007-06-25 US US11/767,734 patent/US7691713B2/en not_active Expired - Fee Related
-
2010
- 2010-04-05 US US12/754,097 patent/US20100190306A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US7691713B2 (en) | 2010-04-06 |
| KR100533553B1 (ko) | 2005-12-06 |
| CN1324687C (zh) | 2007-07-04 |
| US20040235255A1 (en) | 2004-11-25 |
| JP2004349393A (ja) | 2004-12-09 |
| CN101055842B (zh) | 2014-09-17 |
| US20070243687A1 (en) | 2007-10-18 |
| US7244655B2 (en) | 2007-07-17 |
| US20060079061A1 (en) | 2006-04-13 |
| US6998319B2 (en) | 2006-02-14 |
| TW200426978A (en) | 2004-12-01 |
| CN1574296A (zh) | 2005-02-02 |
| JP4578785B2 (ja) | 2010-11-10 |
| DE102004009597A1 (de) | 2004-12-30 |
| CN101055842A (zh) | 2007-10-17 |
| KR20040100830A (ko) | 2004-12-02 |
| US20100190306A1 (en) | 2010-07-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |