TWI262650B - Flip-flop - Google Patents

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Publication number
TWI262650B
TWI262650B TW094109343A TW94109343A TWI262650B TW I262650 B TWI262650 B TW I262650B TW 094109343 A TW094109343 A TW 094109343A TW 94109343 A TW94109343 A TW 94109343A TW I262650 B TWI262650 B TW I262650B
Authority
TW
Taiwan
Prior art keywords
data
clock signal
latch circuit
output
input
Prior art date
Application number
TW094109343A
Other languages
English (en)
Chinese (zh)
Other versions
TW200614670A (en
Inventor
Masashi Hirano
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of TW200614670A publication Critical patent/TW200614670A/zh
Application granted granted Critical
Publication of TWI262650B publication Critical patent/TWI262650B/zh

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the primary-secondary type

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
TW094109343A 2004-04-07 2005-03-25 Flip-flop TWI262650B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004113439A JP2005303464A (ja) 2004-04-07 2004-04-07 フリップフロップ

Publications (2)

Publication Number Publication Date
TW200614670A TW200614670A (en) 2006-05-01
TWI262650B true TWI262650B (en) 2006-09-21

Family

ID=35061941

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094109343A TWI262650B (en) 2004-04-07 2005-03-25 Flip-flop

Country Status (4)

Country Link
US (1) US7353441B2 (enExample)
JP (1) JP2005303464A (enExample)
CN (1) CN1681209A (enExample)
TW (1) TWI262650B (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3964423B2 (ja) * 2004-10-22 2007-08-22 シャープ株式会社 コンテンツデータ作成装置、コンテンツデータ作成方法、コンテンツデータ作成用プログラム、および、コンテンツデータ表示装置
US7650549B2 (en) * 2005-07-01 2010-01-19 Texas Instruments Incorporated Digital design component with scan clock generation
US7725792B2 (en) * 2006-03-01 2010-05-25 Qualcomm Incorporated Dual-path, multimode sequential storage element
US7484149B2 (en) * 2006-03-14 2009-01-27 International Business Machines Corporation Negative edge flip-flops for muxscan and edge clock compatible LSSD
US20090315601A1 (en) * 2006-08-03 2009-12-24 Freescale Semiconductor, Inc. Device and method for timing error management
WO2008015495A1 (en) 2006-08-03 2008-02-07 Freescale Semiconductor, Inc. Device and method for power management
EP2234272A3 (en) * 2009-03-23 2015-09-30 Oticon A/S Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor
FR2961043B1 (fr) * 2010-06-04 2012-07-20 St Microelectronics Sa Registre a double front et son controle a partir d'une horloge
JP5569176B2 (ja) * 2010-06-22 2014-08-13 富士通セミコンダクター株式会社 半導体集積回路
DE102011004310B3 (de) 2011-02-17 2012-04-26 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Schieberegister und Einer-Aus-Vielen-Schieberegister
US8667349B2 (en) * 2011-08-11 2014-03-04 Taiwan Semiconductor Manufacturing Co., Ltd. Scan flip-flop circuit having fast setup time
US9911470B2 (en) * 2011-12-15 2018-03-06 Nvidia Corporation Fast-bypass memory circuit
US9244123B1 (en) 2014-11-25 2016-01-26 Freescale Semiconductor, Inc. Synchronous circuit, method of designing a synchronous circuit, and method of validating a synchronous circuit
US9680450B2 (en) * 2015-02-19 2017-06-13 Advanced Micro Devices, Inc. Flip-flop circuit with latch bypass
US11092649B2 (en) 2019-03-12 2021-08-17 Samsung Electronics Co., Ltd. Method for reducing power consumption in scannable flip-flops without additional circuitry
CN113726326B (zh) * 2021-07-28 2023-11-07 南京航空航天大学 容忍单粒子双点翻转的锁存器结构

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2567530B2 (ja) 1991-07-30 1996-12-25 ストーリッジ・テクノロジー・パートナーズ Ｃｍｏｓ論理回路
JPH0575401A (ja) 1991-09-11 1993-03-26 Toshiba Corp スキヤンセル用フリツプフロツプ回路
JP2522140B2 (ja) 1992-11-18 1996-08-07 日本電気株式会社 論理回路
JPH0795013A (ja) 1993-04-30 1995-04-07 Kawasaki Steel Corp エッジトリガ型フリップフロップ
JP3183260B2 (ja) * 1998-06-17 2001-07-09 日本電気株式会社 スキャンフリップフロップ回路
US6300809B1 (en) * 2000-07-14 2001-10-09 International Business Machines Corporation Double-edge-triggered flip-flop providing two data transitions per clock cycle
US6525565B2 (en) * 2001-01-12 2003-02-25 Xilinx, Inc. Double data rate flip-flop
DE10219119A1 (de) 2002-04-29 2003-11-13 Infineon Technologies Ag Über ein Taktsignal geteuertes Flipflop, Verfahren zum Durchschalten eines Signals durch ein Flipflop, Verwendung eines Flipflops sowie eine Takt-Sperrschaltung
US7082560B2 (en) * 2002-05-24 2006-07-25 Sun Microsystems, Inc. Scan capable dual edge-triggered state element for application of combinational and sequential scan test patterns
US7132854B1 (en) * 2004-09-23 2006-11-07 Cypress Semiconductor Corporation Data path configurable for multiple clocking arrangements

Also Published As

Publication number Publication date
US20050229059A1 (en) 2005-10-13
TW200614670A (en) 2006-05-01
US7353441B2 (en) 2008-04-01
CN1681209A (zh) 2005-10-12
JP2005303464A (ja) 2005-10-27

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MM4A Annulment or lapse of patent due to non-payment of fees