TWI249198B - Methods for manufacturing contact plugs of semiconductor device - Google Patents
Methods for manufacturing contact plugs of semiconductor device Download PDFInfo
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- TWI249198B TWI249198B TW092117815A TW92117815A TWI249198B TW I249198 B TWI249198 B TW I249198B TW 092117815 A TW092117815 A TW 092117815A TW 92117815 A TW92117815 A TW 92117815A TW I249198 B TWI249198 B TW I249198B
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- interlayer insulating
- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 61
- 239000002002 slurry Substances 0.000 claims abstract description 37
- 239000011229 interlayer Substances 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000007800 oxidant agent Substances 0.000 claims abstract description 15
- 230000002378 acidificating effect Effects 0.000 claims abstract description 11
- 238000005498 polishing Methods 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 13
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 10
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 7
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 2
- KHIWWQKSHDUIBK-UHFFFAOYSA-N periodic acid Chemical compound OI(=O)(=O)=O KHIWWQKSHDUIBK-UHFFFAOYSA-N 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 150000001768 cations Chemical class 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 229910052733 gallium Inorganic materials 0.000 claims 1
- 229910052902 vermiculite Inorganic materials 0.000 claims 1
- 235000019354 vermiculite Nutrition 0.000 claims 1
- 239000010455 vermiculite Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000006731 degradation reaction Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 78
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000002474 experimental method Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000002144 chemical decomposition reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004313 glare Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- MVFCKEFYUDZOCX-UHFFFAOYSA-N iron(2+);dinitrate Chemical compound [Fe+2].[O-][N+]([O-])=O.[O-][N+]([O-])=O MVFCKEFYUDZOCX-UHFFFAOYSA-N 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 125000003544 oxime group Chemical group 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012549 training Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Description
1249198 玖、發明說明: 【發明所屬之技術領域】 本發明係揭示製造半導體裝置接觸塞柱之方法。更明確言 之,所揭示之方法可形成安定著陸塞柱多晶矽(Lpp),其方 式是進行中間層絕緣薄膜與多晶矽層之化學機械拋光 製程,其係為一種塞柱材料,利用含有氧化劑之酸性漿液 ’使氧化物薄膜與多晶矽層之盤形化現象降至最低。 【先前技術】 為提供小、高容量及高度整合之半導體裝置,故在形成半 導體裝置之電晶體、位元線及電容器之後,必須進行接觸 塞柱之形成製程,其可電連接至各裝置,意即電晶體、位 元線及電容器。 一般而言,當進行接觸塞柱之形成製程時,必須進行平面 化I程,其方式是利用單一聚液,同時拋光多層,以形成· 具有高縱橫比之接觸塞柱。 但是’當僅使用單一漿液拋光多層狀薄膜時,各層係在差 異拋光速度下被拋光,意即具有不同拋光選擇比,階層差 異係在諸層中產生。結果,難以應用各種後續製程以進行 精製。 特定言之,階層差異係更強烈地產生於中間層絕緣薄膜上 ’在比其他層較高拋光速度下被拋光。因此,在抛光製程 中產生之各層副產物,及漿液之磨料殘留物,係被充填在 中間層絕緣薄膜之上方部份中。結果,在塞柱裝置之間產 生缺陷,譬如電橋。 86356 1249198 圖 法 要地說”造半導體裝置接觸塞柱之習用方 在=a,一個界定活性區域之,溝型裝置隔離薄膜_ 土上形成。並使字元線導電層(未示出)與硬罩蓋 :(,“出),意即氮化物薄膜,在基材U之單元區域上形 “及連續地蚀刻。結果,形成字元線圖樣Μ,其中硬罩 盖圖樣14係於字元線導電層圖樣13上形成。 參考圖ib,隔體15係於字元線圖樣16之側面上形成。中間 層絕緣薄膜17係於所形成結構之整個表面上形成。 參考圖lc,中間層絕緣薄膜17係使用著陸塞柱接觸罩蓋( 未示出)選擇性地㈣,以形成供塞柱用之接點空穴(未示 出卜 /在多晶碎層(未示出)被沉積於所形成結構之整個表面上之 後’其包括供塞柱用之接點空穴(未示出),係使用中时 絕緣薄膜17作為㈣障壁薄模,進㈣光製程,以沉積多 晶矽層18在供塞柱用之接點空穴處。 參考圖Id , CMP製程係利用一般鹼性CMp漿液,對多晶矽 層18整個表面上之氧化物薄膜,及中間層絕緣薄膜I?進行 ,直到使硬罩蓋圖樣14曝露為止,以形成塞柱多晶矽19。 於上述CMP製程中使用之鹼性漿液,係為氧化物薄膜用之 一般CMP漿液,具有pH範圍從8至12,包含磨料,譬如膠態 或煙霧狀Si02* Al2〇3。 一般而言,必須使用在多層之間具有類似拋光速度之漿液 ,以移除多層薄膜。但是,由於習用拋光製程係使用氧化 86356 1249198 物薄膜用之驗性赞、冷;佳γ ,,, 戒'夜進仃,故中間層絕緣薄膜 之拋光選擇比係高於 腰/、夕^夕層 選擇比係高於多晶矽厣,,^ 膜爻拋先 据光速度。彳層〜果’中間層絕緣薄膜具有最高 當進行CMP製程以形成著陸塞柱多晶碎’直到由氮化物薄 膜形成(❹蓋絕料料露為止時,嚴重盤形化作用仔 在中間層絕緣薄膜與多^層上產生。在具有較高抱光選 擇比(中間層絕緣薄膜上之盤形化作用20b,係比在多晶矽 層上之盤形化作用2〇a,更嚴重地產生。 中間層絕緣薄膜之盤形化作用,需要其他氧化物薄膜之另 -個沉積製程,以防止薄膜之表面形態在後續製程中被轉 變。由於CMP製程所造成之拋光殘留物,係被充填在中間層 絕緣薄膜之上方料中,此係由於盤形化作用叫與训所^ 、'不,產生著陸基柱多晶矽之缺陷22,因為殘留物未在· 後續洗淨製程中被移除(參閱圖23與21:)。此等缺陷會在後續 接觸氣私中,於接觸塞柱之間形成電橋,於是使裝置之良 率、特徵及可靠性降級。因此,難以具體化表現裝置之高 整合。 【發明内容】 本發明係揭示一種製造半導體裝置接觸塞柱之方法,其中 薄膜之盤形化現象,係利用對各層具有類似選擇性之氧化 物薄膜用CMP漿液,而被降至最低。 較佳具體實施例之詳述 本發明係揭示一種製造半導體裝置接觸塞柱之方法。 86356 1249198 所揭不用於製造半導體裝置接觸塞柱之方法,係包括. 形成字元線圖樣,其具有字元線導電性材料與硬翁 物薄膜之連續堆叠結構,在半導體基材上; 4化 形成氮化物薄摸隔體於字元線圖樣之側面上; 形成平面化中間層絕緣薄膜於字元線圖樣上; I虫刻該中間層絕緣薄膜,直到基材外露為止,以形成接點 空穴; " 形成多晶碎層於中間層絕緣薄膜之表面上,其中係形成接 點空穴;及 在多晶石夕層與中間層絕緣薄膜上,使用氧化物㈣用之酸
性CMP漿液,進行化學機械挺光(CMP)製程,該漿液具有pH 範圍從2至7 ,含有氧化劑,直到硬罩蓋氮化物薄膜外露為 止。 琢氧化劑包括過氧化氫(H2〇2)、過碘酸(H2I06)、硝酸鐵· [Fe(N3〇9)]或其組合。較佳係使用咏〇2作為此氧化劑。氧化 劑之存在1範圍係從1至4〇體積% ,更佳為2〇至3〇體積% , 以CMP漿液為基準。 此具有pH範圍從2至5之酸性漿液,係包含磨料,選自包 括碎石(si〇2)、氧化鈽(Ce〇2)、氧化锆(Zr〇2)、氧化鋁(Al2〇3) 及其組合。磨料之存在量範圍係從1〇至5〇重量%,更佳為25 至35重量%,以CMP漿液為基準。 一般而言,習用上’係使用具有pH範圍從1〇至13之鹼性 漿液,作為氧化物薄膜用之漿液。由於鹼性漿液包含許多〇H-基團,故盤形化現象係在氧化物薄膜上產生,此係由於其 86356 1249198 在CMP製程期間化學分解所致。 但疋’本發明供氧化物薄膜用之酸性漿液,可防止氧化物 薄膜之化學分解,因其包含比ΟΗΓ基團更多之H+基團。 由於本發明氧化物薄膜用之酸性漿液,對於多晶矽層比對 於氧化物薄膜,具有較低拋光選擇比,故所揭示之酸性漿 液包含氧化劑,以改良對多晶物質之拋光選擇比。 多晶碎層較佳係使用選自包括h摻雜非晶質矽薄膜、摻 雜多晶碎薄膜、P-摻雜磊晶矽薄膜及其組合之一形成。 所揭示之製造方法將參照附圖詳細描述。 圖3a至3d係概要地說明所揭示之方法,根據此揭示内容製 造半導體裝置之接觸塞柱。 參考圖3a ’ 一個界定活性區域之壕溝型裝置隔離薄膜%係 在矽基材31上形成。且字元線導電層(未示出)與硬罩蓋膜( 未示出),意即氮化物薄膜,係於基材31之單元區域上形成· 及連續I虫刻。結果’形成字元線圖樣36,其中硬罩蓋圖 樣34係於字元線導電層圖樣33上形成。 硬罩蓋膜較佳係由氣化物薄膜所組成,而字元線導電層係 由SiON或有機底ARC層所組成。 參考圖3b,隔體35係於字元線圖樣36之側面上形成。平面 化中間層絕緣薄膜37係於所形成結、構之整個表面上形成。 絕緣薄膜隔體較佳係使用氮化物薄膜形成,而中間層絕緣 薄膜係由具有優越流動性之絕緣材料所組成,譬如bpsg (刪 磷矽酸鹽玻璃)或HDP (高密度電漿)氧化物薄膜。 參考圖3c ’中間層絕緣薄膜37係使用著陸塞柱揆觸罩蓋( 86356 -10- Ϊ249198 未不出)選擇性地蝕刻,以形成供塞柱用之接點空穴(未示 出卜 在多晶碎層(未示出)被沉積在所形成結構之整個表面上之 後,其包括供塞柱用之接點空穴(未示出),係使用中間層 絕緣薄膜37作為蝕刻障壁薄膜,進行拋光製程,以沉積多 晶矽層38,在供塞柱用之接點空穴(未示出)處。 多晶矽層較佳係由Ρ-掺雜非晶質矽薄膜、ρ_摻雜多晶矽薄 膜' Ρ-接雜磊晶碎薄膜或其組合所組成。 此處,供塞柱用之接點空穴,較佳係使用”τ'型著陸塞柱 多晶矽(參閱圖4a)形成。而在圖3c之SEM照片中,顯示塞柱 之多晶矽係在接觸區域上形成(參閱圖4b)。 參考圖3d , CMP製程係利用所揭示供氧化物薄膜用之CMp 衆液,在多晶矽層38與中間層絕緣薄膜37之整個表面上進 行,直到硬罩蓋圖樣34外露為止。結果,形成塞柱多晶矽%。一 應明瞭的是,可形成具有很少受到傷害部份之接觸塞柱, 因為根據所揭示之製造方法,盤形化作用幾乎不會在所形 成塞柱多晶矽之橫截面上產生(參閱圖5a與5b)。 【實施方式】 所揭示供氧化物薄膜用之酸性CMP漿液,將參考下文實例 更詳細地描述,其並不意欲成為限制。 A·所揭示漿液之製備 製備膏例1. 於含有30重量% 作為磨料之94重量%供氧化物薄膜用 之酸性CMP漿液中,添加6重量%4〇2,並攪拌。然後,將 86356 -11 - 1249198 所形成之混合物進一步攪拌約30分鐘,直到混合物完全混 合且安定化為止。因此,製成所揭示之漿液。 B·使用所揭示漿液在諸層中之拋光速度之比較 比較實例1. 使碎層沉積在中間層絕緣薄膜之整個表面上,包括供塞柱 用之接點玄K。然後,在矽層與中間層絕緣薄膜上,使用 未具有氧化劑之習用鹼性CMP聚液,進行CMP製程,直到硬 罩蓋氮化物薄膜外露為止。 CMP製程係藉執道系統之CMp設備,在頭壓為3网且檯桌 轉數為600 rpm下進行。 此處,經抛光氧化物薄膜與經拋光多晶矽層之厚度,在第 一次實驗中,個別為2609A與1821人,而在第二次實驗中,為 2620A與1342A。氧化物薄膜/多晶矽層顯示具有拋光選擇比 在第一次實驗中為1.43,而在第二次實驗中為ι·95,平均為1.69· 。因此’明瞭氧化物薄膜比多晶矽層更迅速地被拋光(參閱 圖6)。 實例1. 使碎層沉積在甲間層絕緣薄膜之整個表面上,包括供塞柱 用之接點艺穴。然後,在矽層與中間層絕緣薄膜上,使用 所揭示之得自製備實例1之CMP漿液,進行CMP製程,直到 硬罩蓋氮化物薄膜外露為止。 此CMP製程之條件係與比較實例1相同。 結果,經拋光之氧化物薄膜與多晶矽層之厚度,在第一次
貫驗中’個別為1437A與5292A,而在第二次實驗中,為1429A 86356 -12 - 1249198 與5684人。氧化物薄膜/多晶矽層顯示具有拋光選擇比,在 第一次實驗中為0.25,而在第二次實驗中為0.27,平均為0.26 。因此,明瞭多晶矽層係比氧化物薄膜更迅速地被拋光(參 閱圖6)。 正如實驗結果所証實,當CMP製程在氧化物薄膜與多晶矽 層上,使用所揭示之含有氧化劑之酸性CMP漿液進行時,多 晶矽層比氧化物薄膜具有較快速之拋光速度,達兩倍或更 大。因此,多晶矽層可容易地被拋光。 如前文所討論者,其中盤形化現象係在中間層絕緣薄膜與 多晶矽層上被降至最低之接觸塞柱,可經由CMP製程,使用 所揭示之含有氧化劑之酸性CMP漿液形成,因為中間層絕緣 薄膜與多晶碎層,在用於形成塞柱多晶石夕之製程中,與使 用未具有氧化劑之習用鹼性CMP漿液之CMP製程比較,係具 有逆轉之抱光選擇比《因此,裝置特徵之降質可被防止,_· 這會造成半導體裝置之特徵與可靠性之改良,以製造高度 整合之半導體裝置。 【囷式簡單說明】 圖la至Id係概要地說明製造半導體裝置接觸塞柱之習用方 法。 圖2a與2b為SEM照片,顯示圖id之習用接觸塞柱之平面與 橫截面圖。 圖3a至3d係概要地說明根據本揭示内容製造半導體裝置接 觸塞柱之所揭示方法。 圖4a與4b為SEM照片,說明圖3c接觸塞柱之頂部視圖與橫 86356 13 1249198 截面。 圖5a與5b為SEM照片,顯示圖3d接觸塞柱之平面與橫截面 圖。 圖6為一圖表,說明當薄膜在晶圓上使用所揭示之CMP漿 液拋光時之抱光速度。 【圖式代表符號說明】 11,31 :矽基材 12, 32 :隔離薄膜 13, 33 :字元線導電層圖樣 14, 34 :硬罩蓋圖樣 15, 35 :隔體 16, 36 :字元線圖樣 17,37 :中間層絕緣薄膜 18, 38 :多晶矽層 _ 19, 39 :塞柱多晶矽 20, 21 :盤形化作用 20a :盤形化作用 20b :盤形化作用 21a :盤形化作用 21b :盤形化作用 22 :缺陷 86356 -14-
Claims (1)
1249198 拾、申請專利範圍: L —種製造半導體裝置接觸塞柱之方法,其包括: 形成字元線圖樣,其具有字元線導電性材料與硬罩言 氮化物薄膜之連續堆疊結構,在半導體基材上; 義 形成氮化物薄膜隔體於字元線圖樣之側面上; 形成平面化中間層絕緣薄膜於字元線圖樣上; 蝕刻中間層絕緣薄膜,直到基材外露為止,以形成接 點空穴; 形成多晶碎層於中間層絕緣薄膜之表面上,其中係形 成接點空穴;及 於^阳矽層與中間層絕緣薄膜上,使用氧化物薄膜用 (酸性CMP漿液,進行化學機械拋光(CMp)製程,該漿液 具有pH範圍從2至7,含有氧化劑,直到硬罩蓋氮化物薄 膜外露為止。 _ 2·根據申請專利範圍第1項之方法,其中氧化劑係選自包括 過氧化氫(氏〇2)、過碘酸田21〇6)、硝酸鐵的@3〇9)]及其 組合。 3.根據_請專利範圍第1項之方法,其中氧化劑之存在量範 圍係從1至40體積%,以CMP漿液為基準。 4·根據_請專利範圍第1項之方法,其中氧化劑之存在量範 圍係從20至30體積%,以CMP漿液為基準。 5·根據申請專利範圍第1項之方法,其中酸性漿液具有 範圍從2至5。 6.根據中請專利範圍第1項之方法,其中酸性漿液包含磨料 86356 1249198 ’選自包括矽石(sa)、氧化鈽(Ce〇2)、氧化锆(Zr〇2)、氧 化鋁(Al2 03 )及其組合。 7.根據申請專利範圍第6項之方法,其中磨料之存在量範圍 係從10至50重量%,以CMP漿液為基準。 8_根據申請專利範圍第7項之方法,其中磨料之存在量範圍 係從25至35重量%,以CMP漿液為基準。 9·根據中請專利範圍第η之方法,其中多^層係使用選 自包括Ρ-摻雜非晶質矽薄膜、ρ_摻雜多晶矽薄膜、&摻 雜羞晶矽薄膜及其組合之一形成。 10.根據中請專利範圍第1項之方法,其中字元線導電性材料 係由Si0N或有機底ARC層形成。 u.根據_請專利範㈣1項之方法,其中中間層絕緣薄模係 由BPSG(·❹酸鹽玻璃)或膽(高密度電幻氧化 膜形成。 12· —種製造半導體裝置接觸塞柱之方法,其包括·· 产形成字元線_樣,其具有字元線導電性材料與硬罩蓋 氮化物薄膜之連續堆疊,在半導體基材上; 形成氮化物薄膜隔體於字元線圖樣之側面上; 形成平面化中間層絕緣薄膜於字元線圖樣上; 姓刻中間層絕緣薄膜,直到基材外露為止,以形成接 點空穴; 形成夕日Ej矽層於中間層絕緣薄膜之表面上,其中 成接點空穴;及 ’' ^ 在多晶石夕層與中間層絕緣薄膜上,使用氧化物薄膜用 86356 1249198 之CMP漿液,進行CMP製程,該漿液具有pH範圍為2至7 ,含有H2〇2,其含量範圍從1至40體積%。 86356
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JP2006005237A (ja) * | 2004-06-18 | 2006-01-05 | Sharp Corp | 半導体装置の製造方法 |
CN100437929C (zh) * | 2004-08-04 | 2008-11-26 | 探微科技股份有限公司 | 蚀刻具不同深宽比的孔洞的方法 |
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JP2008264952A (ja) * | 2007-04-23 | 2008-11-06 | Shin Etsu Chem Co Ltd | 多結晶シリコン基板の平面研磨加工方法 |
US20090056744A1 (en) * | 2007-08-29 | 2009-03-05 | Micron Technology, Inc. | Wafer cleaning compositions and methods |
CN102479695B (zh) * | 2010-11-29 | 2014-03-19 | 中国科学院微电子研究所 | 提高金属栅化学机械平坦化工艺均匀性的方法 |
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US6607955B2 (en) * | 1998-07-13 | 2003-08-19 | Samsung Electronics Co., Ltd. | Method of forming self-aligned contacts in a semiconductor device |
US6206756B1 (en) * | 1998-11-10 | 2001-03-27 | Micron Technology, Inc. | Tungsten chemical-mechanical polishing process using a fixed abrasive polishing pad and a tungsten layer chemical-mechanical polishing solution specifically adapted for chemical-mechanical polishing with a fixed abrasive pad |
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US6348395B1 (en) * | 2000-06-07 | 2002-02-19 | International Business Machines Corporation | Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow |
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US6635576B1 (en) * | 2001-12-03 | 2003-10-21 | Taiwan Semiconductor Manufacturing Company | Method of fabricating borderless contact using graded-stair etch stop layers |
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