1351735 . 第96117764號專利說明書修正本 .修正曰期：100年2月〗5日 九、發明說明： . 【發明所屬之技術領域】 本發明係有關於一種半導體元件及其製造方法，特別 ' 有關於一種記憶體元件及其製造方法。 【先前技術】 - 隨著積體電路被廣泛地運用，為因應不同使用目的， 更高效能與更低廉價格之各類半導體元件相繼產出，其 中，動態隨機存取記憶體（DRAM)在現今資訊電子業中 # 更有著不可或缺的地位。 現今大多數的DRAM單元是由一個電晶體與一個電 容器所構成。由於目前DRAM之記憶容量已達到512百 萬位甚至1024百萬位元以上，在元件積集度要求越來越 南的情況下’記憶早元與電晶體的尺寸需要大幅縮小’才 可能製造出記憶容量更高，處理速度更快的DRAM。利用 立體化電容器的製程技術，可以大量地減少電容器於半導 體基底上所佔佈之面積，因此立體化電容器開始被運用於 φ DRAM的製程上，例如溝槽型電容器便被廣泛地運用在記 憶容量為1024百萬位元以上的DRAM。 第1A圖〜第1F圖揭示一種習知製作深溝槽記憶體之 ' 方法，首先，請參照第1A圖，提供一基底100，包括一 陣列區102和一週邊區104。接著，於基底100上形成複 數條導電層105,並於導電層105上和側壁形成間隙壁106 以形成閘極109，後續，以上述閘極109為罩幕，進行離 子佈植製程，以於基底100中形成摻雜區110、111，接 著，沉積一氮化矽襯層108於基底100和閘極109上。後 1351735 第96117764號專利說明書修正本 修正曰期：100年2月15曰 續’請參照第1B圖，毯覆性的沉積一侧填玻璃層 112(Boron phosphor silicate glass，以下可簡稱 BPSG)於氮 化石夕觀層108上’並沉積一硬式罩幕層114於棚填玻璃層 112 上。 接下來’請參照第1C圖，以黃光微影法形成 化之光阻層116於硬式罩幕層114上。請參照第1 d圖 以圖形化之光阻層116為罩幕蝕刻硬式罩幕層114，並以 圖开》化硬式罩幕層114為罩幕，鍅刻硼罐玻璃層ip,暴 露陣列區102中兩相鄰閘極109間之一摻雜區11〇和週邊 區104中之一摻雜區lu，如圖所示，此製程步驟一般使 用對氮化矽襯層108和硼填玻璃層112有高選擇比之姓刻 軋體或蝕刻劑，以使此蝕刻製程能不損傷閘極109，而能 自動對準（Self-alignment)的沿著閘極1〇9上氮化矽襯層 108暴露出兩相鄰閘極109間之摻雜區11〇，另外，此一 步驟亦同時_出—開口 ’暴露出位於週邊區1()4基底 100中之摻雜區1 i i。 -1351735. Amendment to Patent Specification No. 96117764. Revision Period: 100 years February, 5th, 9th, invention description: 1. Field of the Invention The present invention relates to a semiconductor element and a method of manufacturing the same, particularly A memory element and a method of manufacturing the same. [Prior Art] - As integrated circuits are widely used, various types of semiconductor components with higher performance and lower cost are successively produced for different purposes, among which dynamic random access memory (DRAM) is present. In the information electronics industry, # is more indispensable. Most DRAM cells today consist of a transistor and a capacitor. Since the memory capacity of DRAM has reached 512 million bits or even 1024 million bits or more, in the case where the component accumulation requirement is getting more and more south, the memory size and the size of the transistor need to be greatly reduced, and it is possible to create a memory. Higher capacity, faster processing DRAM. The process technology of the three-dimensional capacitor can greatly reduce the area occupied by the capacitor on the semiconductor substrate, so the three-dimensional capacitor is used in the process of φ DRAM, for example, the trench capacitor is widely used in the memory capacity. It is 1024 megabits or more of DRAM. 1A to 1F illustrate a conventional method of fabricating deep trench memory. First, referring to FIG. 1A, a substrate 100 including an array region 102 and a peripheral region 104 is provided. Then, a plurality of conductive layers 105 are formed on the substrate 100, and a spacer 106 is formed on the conductive layer 105 and the sidewalls to form the gate 109. Subsequently, the gate 109 is used as a mask to perform an ion implantation process. Doped regions 110, 111 are formed in the substrate 100, and then a tantalum nitride liner 108 is deposited on the substrate 100 and the gate 109. After the 1351735 patent specification No. 96117764, the revision period is as follows: February 15th, 2010. Please refer to Figure 1B. The blanket deposition layer 112 (Boron phosphor silicate glass, hereinafter referred to as BPSG) On the nitriding layer 108, a hard mask layer 114 is deposited on the shed glass layer 112. Next, please refer to FIG. 1C to form a photoresist layer 116 formed by a yellow lithography method on the hard mask layer 114. Referring to FIG. 1D, the patterned photoresist layer 116 is used as a mask to etch the hard mask layer 114, and the hard mask layer 114 is used as a mask to engrave the boron can glass layer ip to expose the array region. In one of the two adjacent gates 109, one of the doped regions 11〇 and one of the peripheral regions 104, as shown in the figure, the process step generally uses a tantalum nitride liner 108 and a boron-filled glass layer. 112 has a higher selectivity than the surname of the rolling body or etchant, so that the etching process can not damage the gate 109, but can automatically align (Self-alignment) along the gate 1〇9 on the tantalum nitride liner 108 exposes the doped region 11 间 between two adjacent gates 109. In addition, this step also exposes the doped region 1 ii in the substrate 100 of the peripheral region 1 () 4 at the same time. -
接著，請參照第汨圖，沉積一導電層118，填入上 述陣列區1 02中兩閘搞1 〇Q (f + ^ 閘> 1ϋ〃間之空隙，以形成位元線接觸 (contact to bit line)，並且導雷展 11e 104 Φ V電層亦填入上述週邊區 二，以形成週邊電路連接區104(contact tc) support)。後續，谁；^— :虛此 m 、 aci t0 接著，於則_層U2J^r^移衫制導電層l18, 和硼鱗玻璃層,U2，=:製，圖形化層間介電層12〇 一導電声⑴Γ 凡線開口⑷會示），並填入 導-層118於位凡線開口中， 1351735 4 第96】】7764號專利說明書修正本 修正日期··廳年2月15日 然而，上述用以製造記憶體元件之方法具有以下缺 '點··如第】D圖所示，以自動對準（self-angnment)蝕刻法 .钱刻硕4玻璃層〗12，沿著閘極1 〇9上氮化石夕觀層】暴 •，出兩相鄰閘極1〇9間之摻雜區〗10時，很難完全避免損 傷或是蝕刻部份之閘極間隙壁1〇6和其側邊之氮化矽襯 層】〇8 ’而因此容易造成位元、線122和字元線間之短路 (WL-BL short)。另外，上述自動對準蝕刻法蝕刻硼磷玻璃 層112時，很容易蝕刻到接觸位元線122之 #摻雜區no,造成石夕損失(siliconI〇ss)，而產生漏電流= t，著凡件的微縮’接觸位元線122之基底_中的 夕”區110的接面深度越來越淺（小於2⑼埃），因此， 述漏電流的問題也越來越嚴重。 、 【發明内容】 有鑑於此，為解決上述問題，本發明係提供 體元件和其製造方法，诘小 種》己隐 (WL-BL sh(m)，並可減和子元線間之短路 摻雜區，㈣成連接位元線之基底中的 至少法。首先，形成 基底上，並填人兩^間ϋ _層於上述鬧極和 層’保留位於兩閘極間之空『及:接：’圖形化摻雜介電 區域。後續，進行—選擇性㈣^雜”電層未覆蓋之 電層，至少暴露出兩閘極間空隙之基^擇除摻雜介 導電插塞於兩閘極間之空隙中，並:成一位元：:：:； 7 1351735 修正日期：100年2月μ曰 第96117764號專利說明書修正本 電插塞。 本發明提供一種記憶體元件之製造方法。首先，提供 二基底’包括-陣列區和—週邊區，形成複數個閘極於其 底上，其中上述閘極至少包括氧化石夕組成之間隙壁，且^ 於陣列區中之兩鄰近閘極間包括一間隙。接著 邊:於兩鄰近間極間隙下之基底中形成一摻雜區， 、:^邊區之部份基底中形成另一摻 於上述_上和基底上，形成-摻4電Cl 上’並Ϊ入陣列區中之兩鄰近閉極間之間 列區中之兩鄰近閉極間之間隙和週邊區：f:::陣 :更式罩幕層上形成圖形化光阻。後續，以== ^硬式罩恭層，並以硬式罩幕層為罩幕則八 雜區以外之部份掺 =/1之間隙和週邊區之摻 式罩幕層，形成—無摻雜;二除圖形化光阻和硬 電層，使無摻雜介選擇性的移除摻雜介 區。其後，形成—導 ，入接雜區和週邊區之摻雜 每雜區。最後，形成—Μ線接耗和週邊區之 本發明槎供—你^ 小牧咽等电層〇 之主要閘極和通過閘極隐:::二包括下列元件：兩相鄰 閘極和通過閘極間之美 、土底之陣列區中，其中主要 摻雜區之另-側連接：：：ί括—摻雜區，且主要閘極於 合裔，主要間極和通過閘極兩者 1351735 , 第細764號專利說明雜正本 —修正日期：刚年2肋日 -都在僅-側覆蓋有間隙壁，另一側覆蓋有一概層，其中觀 •層之厚度較間隙壁之厚度薄。一導電插塞，填入主要問極 和通過閘極間之間隙中。一位元線，連接導電插塞。 【實施方式】 以下將以實施例詳細說明做為本發明之 .斜隨著圖式說明之。在圖式或描述中，相似或相同= 使用相同之圖號。在圖式中’實施例之形狀或是厚； 述T或是方便標示。圖式中各元件之部分將： 二Ί月之，值传注意的是，圖中未繪示或描述之元 可3具有各種m技藝之人士所知的形式，另外， 憶體實=製，槽記 月/ ”，、弟2A圖，k供一基底200， 二列區202和―週邊區2〇4 ’基底2〇〇可以是半導 & 例如和絕緣層上有:Next, referring to the figure, a conductive layer 118 is deposited, and the gap between the two gates 1 〇Q (f + ^ gate > 1 填 is filled in the array area 102 to form a bit line contact (contact to Bit line), and the conductive layer 11e 104 Φ V electrical layer is also filled into the above peripheral area 2 to form a peripheral circuit connection area 104 (contact tc) support). Follow-up, who; ^-: virtual this m, aci t0 Next, then _ layer U2J ^ r ^ transfer shirt conductive layer l18, and boron scale glass layer, U2, =: system, patterned interlayer dielectric layer 12〇 A conductive sound (1) 凡 where the wire opening (4) will be shown, and filled into the guide layer 118 in the position of the line opening, 1351735 4 96]] 7764 patent specification revised this revision date · · Hall year February 15 However, The above method for manufacturing a memory device has the following disadvantages: as shown in the figure D, with a self-angnment etching method. The money is etched 4 glass layer 12, along the gate 1氮化9 on the nitriding layer of the nitriding layer] violently, when the doping area between the two adjacent gates is 1 〇9, it is difficult to completely avoid damage or etch the part of the gate spacer 1〇6 and its The tantalum nitride liner on the side is 〇8' and thus easily causes a short circuit (WL-BL short) between the bit, line 122 and the word line. In addition, when the borophosphosilicate layer 112 is etched by the above-described auto-alignment etching method, it is easy to etch into the #doped region no of the contact bit line 122, causing a silicon 〇ss loss, and a leakage current = t, The junction depth of the miniaturized 'contact area of the contact bit line 122' is shallower (less than 2 (9) angstroms), and therefore, the problem of leakage current is becoming more and more serious. In view of the above, in order to solve the above problems, the present invention provides a body element and a manufacturing method thereof, and a small type has been hidden (WL-BL sh (m), and can reduce the short-circuit doping region between the sub-line, (4) At least the method of connecting the base of the bit line. First, forming a substrate, and filling the two layers _ _ layer in the above-mentioned smashing layer and layer 'retaining the space between the two gates Dielectric region is doped. Subsequently, an electrical layer not covered by the selective (tetra)-electric layer is exposed, and at least the gap between the two gates is exposed to remove the intervening dielectric plug between the two gates.中,和:成一元::::; 7 1351735 Revision date: 100 years February, μ曰 No. 96117764 patent said The present invention provides a method of fabricating a memory device. First, a two substrate 'including-array region and a peripheral region are provided to form a plurality of gates on a bottom thereof, wherein the gate includes at least oxidation The stone wall comprises a gap, and comprises a gap between two adjacent gates in the array region. Then, a doping region is formed in the substrate under the two adjacent interpole gaps, and a part of the base region of the edge region Forming another gap between the two adjacent closed poles and the peripheral region formed on the above-mentioned upper and lower sides of the column region between the two adjacent closed electrodes in the array region: f::: array: a patterned photoresist is formed on the mask layer. Subsequently, the == ^ hard mask is layered, and the hard mask layer is used as the mask. The gap between the gap and the peripheral region of the doped mask layer, forming - no doping; the second removal of the patterned photoresist and the hard layer, so that the doping-free selective removal of the doped dielectric region. Thereafter, forming a guide , the doping region and the peripheral region are doped with each impurity region. Finally, the invention for forming the Μ line and the peripheral region 槎- You ^ The main gate of the electric layer of Xiaomuyan and the pass gate are hidden::: Two includes the following components: two adjacent gates and the area between the gate and the bottom of the gate, the main doping area The other side connection::: ί — - doped area, and the main gate is in the sacred, the main interpole and the pass gate are both 1351735, the second 764 patent description miscellaneous original - revised date: just 2 years rib Day-to-side is covered with a spacer on the other side, and the other side is covered with a layer, wherein the thickness of the layer is thinner than the thickness of the spacer. A conductive plug fills the gap between the main gate and the gate. A one-dimensional line is connected to a conductive plug. [Embodiment] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In the drawings or descriptions, similar or identical = use the same figure number. In the drawings, the shape of the embodiment is either thick or T; Part of each element in the drawing will be: Two months, the value of the note is that the figure not shown or described in the figure can be in the form known to those who have various m techniques, in addition, the memory is true, The groove is recorded in the month /", the second 2A picture, k is provided for a substrate 200, the second column area 202 and the "peripheral area 2〇4' substrate 2" can be semi-conductive &
tors) ^ ^ ^ ^ ^ ^ ^ - ^ ^ t „ ,tJ 深溝样•六哭"、=斤組成。接下來’形成一電容器（例如 :==底2°。上，在上= 开介電層-上，-例如金= 2〇8Λ 層上，及位於第-開極導電# 閘極導電層210上部和側壁之氧切所組成 9 1351735 第96117764號專利說明書修正本 修正日期：100年2月15曰 間隙壁212。上述形成電容器和閘極206之方法為此技藝 領域所熟的技術，在此不詳細說明。須注意的是，在此實 施例中，上述閘極206在陣列區202中至少包括一連接電 容器之主要閘極214和一鄰近主要閘極214之通過閘極 - 216(passing gate，其亦可以稱之通過字元線passing word line)，另外，週邊區204中亦可形成有閘極217。接著， 進行一或是複數個離子佈植製程，以於基底200中形成所 需之摻雜區203。後續，以例如化學氣相沉積法（chemical vapor deposition，以下可簡稱CVD)形成一第一襯層223 於閘極206之間隙壁212和基底200上，在本發明較佳實 · 施例中，第一概層223為氮化石夕所組成。 接下來，請參照第2B圖，以例如化學氣相沉積法形 成一掺雜介電層218於第一襯層223上，摻雜介電層218 較佳為鱗玻璃（Boron phosphor silicate glass，以下可簡 稱BPSG)，其厚度可約為2500〜3000埃，接著，對摻雜介 電層218進行一化學機械研磨製程（chemical mechanical polishing，以下可簡稱CMP)，以得到較平坦的表面。後 續，對摻雜介電層218進行例如熱回火之加熱步驟，以使 · 摻雜介電層218可填入上述閘極206間之空隙中，此步驟 可稱為BPSG再回流（BPSG re-flow)。後續，以例如化學 ^ 氣相沉積法形成一硬式罩幕層220於摻雜介電層218上， -硬式罩幕層220較佳為多晶矽所組成。 接著，請參照第2C圖，塗佈一光阻層（未繪示）於硬 式罩幕層220上，並以黃光微影方法圖形化光阻層，保留 陣列區202中位於主要閘極214和通過閘極216間隙上方 之部份光阻層222和週邊區204中預定形成週邊電路連接 10 1351735 第96117764號專利說明書修正本 修正日期：100年2月15日 . 區（contact to support)上方之部份光阻層222。其後，請參 . 照第2D圖，以圖形化光阻層222為罩幕，蝕刻硬式罩幕 層220，並以圖形化硬式罩幕層220為罩幕，進行一非等 向性姓刻製程，依序移除預定形成位元線接觸（contact to bit line)和週邊電路連接區外之部份摻雜介電層218、第一 襯層223和間隙壁212。後續，移除圖形化光阻層222。 接著，請參照第2E圖，移除硬式罩幕層220，並以 例如化學氣相沉積法毯覆性的沉積一第二襯層224於圖 形化之摻雜介電層218、圖形化之間隙壁212和基底200 ® 上，在本發明較佳實施例中，第二襯層224為氮化矽所組 成，且其厚度可以例如為100〜200埃。接下來，以例如高 密度電漿（High density plasma，以下可簡稱HDP)沉積法， 毯覆性的沉積一無摻雜介電層226於第二襯層224上，在 本發明較佳實施例中，無摻雜介電層226為四乙氧基矽烷 (TE0S)為前趨物所形成之氧化矽，其厚度可以例如為 4000〜7000埃。後續，進行一化學機械研磨法製程，移除 多餘厚度之無摻雜介電層226並使其平坦化，此步驟之化 • 學機械研磨法製程可停止於圖形化摻雜介電層218上之 第二襯層224上，且可於研磨製程中加一道過度研磨（over . polish)步驟，移除位於摻雜介電層218上之第二襯層 ' 224，以暴露摻雜介電層218。 接下來，請參照第2F圖，進行一選擇性蝕刻製程， 選擇性的移除摻雜介電層218，而保留其餘各層，在本發 明較佳實施例中，此選擇性蝕刻製程為以氣態氟化氫 (vaporHF，可簡稱VHF)進行蝕刻，由於氣態氟化氫對於 摻雜介電層218(特別是BPSG)之蝕刻率相當快，而對於無 1351735 第則編號專利說明書修正本. 修正日期：刚年2月日 摻雜介電層226之蝕刻率則較慢.，因此，可控制製程條件 (例如蝕刻時間，溫度，氣體流量等等）達到選擇性移除捭 雜介電層218,於陣列區202中位於主要閘極214和通過 閘，216間之間隙形成第一開口 228，並於週邊區2〇4中 預J形成週邊電路連接區上方之無摻雜介電層226中形 成第二開口 230。後續，可以例如浸泡磷酸的方法移除第 一開口 228和第二開口 23〇中的部份第—襯層2 '一 襯層224。 π步一 對第^須Τ'的是’以VHF製程移除捧雜介電層218 幼丨幵口 8下之基底200產生之損傷相當小（矽損失 :、’、於50埃），另外，由於進行VHF製程時，第一開^ 2198 之f要閘極214#°通過閘極216的兩側之間i壁 製程=如二^ 極叫•嶋 後續’請參照第2G圖，以你丨知風 性的沉積—導電 目％積法毯覆 口 228和第二門口㈣丨电層226上，並填入第-開 可以為摻雜多日/以形成導電插塞232，導電層 進行-化鶴、㈣銅之金屬。接下來， 於的導電^ =磨=呈，移除無推雜介電層W上方多 -層間介i岸… > 歹如化學氧相沉積法毯覆性的沉積 上，層間介^ 234於雜介電層226 *導電插塞232 組合，或低介i材料芦化石夕、氮氧化石夕或其 如為1500〜3〇〇〇埃。S 3間"電層234之厚度可以為例 12 丄乃1735 * 弟％im64號專利說明書修正本 修正日期：100年2月15日 接著’請參照第2H圖’圖形化層間介電層234和/ ' 或無摻雜介電層226，以形成複數個位元線236，分別連 接導電插塞232。 根據本發明上述之記憶體元件製造方法，以下揭示本 發明之結構，如第2H圖所示，由於本發明陣列區2〇2中 主要閘極214和通過閘極216上之部份氧化矽所組成之間 隙壁212係於製程步騾中圖形化，而於未覆蓋間隙壁212 之，份第一閘極導電層208和第二閘極導電層21〇上係形 • 1第二襯層224,因此，本發明形成主要間極Μ和通過 = 216僅-側覆蓋有間隙壁212，另一側覆蓋有一觀層 产广之、’°構其中5亥襯層之厚度較該間隙壁212之厚 以成位元接觸（CB)之開口係 3 1 I’其對基底細摻耗加產生之損傷 二；制， 可以減少漏電流相關問題，此外，進行 ’位元接觸（CB)開口兩側主要閘極214和通 過閘極216兩側之間隙壁212有例如氮化石夕所組成 襯層224保護，因此，vhf萝程亦尤备 二 兩側主要閘極214和通過閘’、曰’：於第一開口 228 損傷，而可減少位元線2 ^兩側之間隙壁212產生 short) 〇 ^線236和子元線間之短路（WL舰 —雖然本發明已以較佳實施例揭露如上，$ 限定本發明，任何熟習此技藝者， ” _用以 和範圍内，當可作些許之更動盥 ^本發明之精神 範圍當視後附之申請專利範圍所^定者因為^本發明之保護 1351735 第96117764號專利說明書修正本 修正日期：100年2月15曰 【圖式簡單說明】 第1A圖〜第1F圖揭示一種習知製作深溝槽記憶體之方 法。 第2A圖〜第2H圖揭示本發明一實施例製作深溝槽記 憶體之方法。 【主要元件符號說明】 100〜基底； 104〜週邊電路連接區， 106〜間隙壁； 109〜閘極； 111〜摻雜區； 114〜硬式罩幕層； 118〜導電層； 122〜位元線； 202〜陣列區； 204〜週邊區， 208〜第一閘極導電層； 212〜間隙壁； 216〜通過閘極； 217〜問極， 222〜光阻層； 224〜第二襯層； 228〜第一開口； 232〜導電插塞； 2 3 6〜位元線； 102〜陣列區； 105〜導電層； 108〜氮化矽襯層； 110〜摻雜區； 112〜蝴磷玻璃層； 116〜光阻層； 120〜層間介電層； 200〜基底； 203〜摻雜區； 206〜閘極； 210〜第二閘極導電層； 214〜主要閘極； 218〜摻雜介電層； 220〜硬式罩幕層； 223〜第一概層； 226〜無摻雜介電層； 230〜第二開口； 234〜層間介電層； 250〜閘極介電層。Tors) ^ ^ ^ ^ ^ ^ ^ - ^ ^ t „ , tJ deep groove like • six crying ", = kg composition. Next 'form a capacitor (for example: == bottom 2 °. upper, on top = Kaisuke The electric layer-upper, - for example, the gold = 2〇8Λ layer, and the oxygen-cutting portion located on the upper and side walls of the first-electrode conductive layer 210 of the gate conductive layer 210. 1 1351735 Patent Specification No. 96117764 Revision Date: 100 years February 15 曰 spacer 212. The above-described method of forming the capacitor and gate 206 is a technique well known in the art and will not be described in detail herein. It should be noted that in this embodiment, the gate 206 is in the array region. 202 includes at least one main gate 214 of the connection capacitor and a pass gate 216 (passing gate, which may also be referred to as a passing word line), and a peripheral word 204 A gate electrode 217 may be formed. Then, one or a plurality of ion implantation processes are performed to form a desired doping region 203 in the substrate 200. Subsequently, for example, chemical vapor deposition (chemical vapor deposition) Referred to as CVD), a first liner layer 223 is formed on the spacer of the gate 206. 212 and the substrate 200, in the preferred embodiment of the present invention, the first anisotropic layer 223 is composed of nitride nitride. Next, please refer to FIG. 2B to form a doping medium by, for example, chemical vapor deposition. The electric layer 218 is on the first lining layer 223. The doped dielectric layer 218 is preferably a Boron phosphor silicate glass (hereinafter referred to as BPSG), and has a thickness of about 2500 3,000 3,000 Å. The electric layer 218 performs a chemical mechanical polishing (hereinafter referred to as CMP) to obtain a relatively flat surface. Subsequently, the doped dielectric layer 218 is subjected to a heating step such as thermal tempering to dope the doping. The dielectric layer 218 can be filled in the gap between the gates 206. This step can be referred to as BPSG re-flow. Subsequently, a hard mask layer 220 is formed by, for example, chemical vapor deposition. On the hybrid dielectric layer 218, the hard mask layer 220 is preferably made of polysilicon. Next, please refer to FIG. 2C, and apply a photoresist layer (not shown) on the hard mask layer 220, and use yellow light micro- The shadow method graphically forms the photoresist layer, which is located in the array area 202 The gate electrode 214 and the portion of the photoresist layer 222 and the peripheral region 204 above the gate 216 are formed to form a peripheral circuit connection. 10 1351735 Patent Specification No. 96117764 This revision date is amended: February 15, 100. To a portion of the photoresist layer 222 above. Thereafter, please refer to FIG. 2D, with the patterned photoresist layer 222 as a mask, etching the hard mask layer 220, and using the patterned hard mask layer 220 as a mask to perform an anisotropic The process sequentially removes a portion of the doped dielectric layer 218, the first liner layer 223, and the spacers 212 that are intended to form a contact to bit line and a peripheral circuit connection region. Subsequently, the patterned photoresist layer 222 is removed. Next, referring to FIG. 2E, the hard mask layer 220 is removed, and a second liner layer 224 is blanket deposited on the patterned doped dielectric layer 218 by a chemical vapor deposition method, and the patterned gap is formed. On the wall 212 and the substrate 200 ® , in a preferred embodiment of the invention, the second liner layer 224 is composed of tantalum nitride and may have a thickness of, for example, 100 to 200 angstroms. Next, an undoped dielectric layer 226 is blanket deposited on the second liner layer 224 by, for example, a high density plasma (HDP) deposition method, in accordance with a preferred embodiment of the present invention. The undoped dielectric layer 226 is a ruthenium oxide formed by tetraethoxy decane (TEOS) as a precursor, and may have a thickness of, for example, 4000 to 7000 angstroms. Subsequently, a chemical mechanical polishing process is performed to remove and planarize the excess thickness of the undoped dielectric layer 226. The process of the mechanical polishing process can be stopped on the patterned doped dielectric layer 218. On the second liner layer 224, an over-polishing step can be added to the polishing process to remove the second liner layer 224 on the doped dielectric layer 218 to expose the doped dielectric layer. 218. Next, referring to FIG. 2F, a selective etching process is performed to selectively remove the doped dielectric layer 218 while leaving the remaining layers. In the preferred embodiment of the invention, the selective etching process is in a gaseous state. Hydrogen fluoride (vaporHF, abbreviated as VHF) is etched, because the etching rate of gaseous hydrogen fluoride for doped dielectric layer 218 (especially BPSG) is quite fast, and for the no. 1351735, the numbered patent specification is revised. Amendment date: just 2 The etch rate of the doped dielectric layer 226 is slower. Therefore, process conditions (eg, etch time, temperature, gas flow, etc.) can be controlled to selectively remove the doped dielectric layer 218 in the array region 202. The first opening 228 is formed in the gap between the main gate 214 and the pass gate 216, and the second opening 230 is formed in the undoped dielectric layer 226 formed in the peripheral region 2〇4 to form a peripheral circuit connection region. . Subsequently, a portion of the first opening 228 and the second opening 23A may be removed by, for example, immersion of phosphoric acid. The π step pair of the first is 'the removal of the dielectric layer 218 by the VHF process. The damage caused by the substrate 200 under the crotch 8 is relatively small (矽 loss:, ', at 50 angstroms), and Because of the VHF process, the first opening ^ 2198 f to the gate 214 # ° through the two sides of the gate 216 between the i wall process = such as two ^ pole called • 嶋 follow 'Please refer to the 2G map, to you丨 丨 的 — — — — — — — 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 - Huahe, (4) Copper metal. Next, the conductive ^ = grinding = present, remove the multi-layer dielectric layer above the non-extrusion dielectric layer W ... > such as chemical oxygen phase deposition blanket deposition, interlayer 234 The hybrid dielectric layer 226 * the conductive plug 232 is combined, or the low dielectric material is ruthenium fossil, or nitrous oxide oxide or it is 1500~3 〇〇〇. The thickness of the S 3 "Electrical layer 234 can be as an example 12 丄 is 1735 * Dimensional %im64 Patent Specification Amendment Revision Date: February 15, 100, then 'Please refer to Figure 2H' to pattern the interlayer dielectric layer 234 And / or the undoped dielectric layer 226 to form a plurality of bit lines 236, respectively connected to the conductive plugs 232. According to the above method for fabricating a memory device of the present invention, the structure of the present invention is disclosed below, as shown in FIG. 2H, because the main gate 214 in the array region 2〇2 of the present invention and a portion of the yttrium oxide on the gate 216 are The formed spacers 212 are patterned in the process step, and the first gate conductive layer 208 and the second gate conductive layer 21 are formed on the first and second gate conductive layers 21 without covering the spacers 212. Therefore, the present invention forms a main inter-pole enthalpy and is covered with a spacer 212 only by the side of the 216, and the other side is covered with a viewing layer, and the thickness of the 5 lining layer is larger than that of the spacer 212. The thickness of the open contact (CB) is 3 1 I', which causes damage to the fine doping of the substrate; the system can reduce the leakage current related problems, and further, the two sides of the 'bit contact (CB) opening are performed. The main gate 214 and the spacer 212 on both sides of the gate 216 are protected by a lining layer 224 such as a nitride nitride. Therefore, the vhf process is also provided with two main gates 214 and a gate ', 曰': An opening 228 is damaged, and the gap wall 212 on both sides of the bit line 2 can be reduced. Short-circuit between 〇^ line 236 and the sub-line (WL ship - although the invention has been disclosed above in the preferred embodiment, $ stipulates the invention, any one skilled in the art, _ The scope of the invention is determined by the scope of the patent application. The protection of the invention is 1351735. The patent specification of the 9611764 is amended. The date of revision: 100 years February 15 曰 [Simple diagram Description 1A to 1F show a conventional method of fabricating a deep trench memory. 2A to 2H illustrate a method of fabricating a deep trench memory according to an embodiment of the present invention. [Description of Main Components] 100~ Substrate; 104~ peripheral circuit connection region, 106~ spacer; 109~ gate; 111~ doped region; 114~ hard mask layer; 118~ conductive layer; 122~bit line; 202~ array area; Peripheral region, 208~first gate conductive layer; 212~ spacer; 216~ through gate; 217~dipole, 222~ photoresist layer; 224~second liner; 228~first opening; 232~conductive Plug; 2 3 6~bit line; 102 Array region; 105~ conductive layer; 108~ tantalum nitride liner; 110~ doped region; 112~phosphorus glass layer; 116~ photoresist layer; 120~ interlayer dielectric layer; 200~ substrate; Zone; 206~ gate; 210~second gate conductive layer; 214~ main gate; 218~ doped dielectric layer; 220~ hard mask layer; 223~ first layer; 226~ undoped layer Electrical layer; 230~ second opening; 234~ interlayer dielectric layer; 250~ gate dielectric layer.
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