TWI246170B - Super-thin high speed flip chip package - Google Patents

Super-thin high speed flip chip package Download PDF

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Publication number
TWI246170B
TWI246170B TW091103588A TW91103588A TWI246170B TW I246170 B TWI246170 B TW I246170B TW 091103588 A TW091103588 A TW 091103588A TW 91103588 A TW91103588 A TW 91103588A TW I246170 B TWI246170 B TW I246170B
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TW
Taiwan
Prior art keywords
substrate
die
package
patent application
scope
Prior art date
Application number
TW091103588A
Other languages
English (en)
Inventor
Rajendra Pendse
Samuel Tam
Original Assignee
Chippac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chippac Inc filed Critical Chippac Inc
Application granted granted Critical
Publication of TWI246170B publication Critical patent/TWI246170B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

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1246170 A7 B7 五、發明説明（， 相關申請案之交互參考 年2月27曰立案之臨時申請編號
本申請案主張於200! 6〇/272,236之優先權。 發明背景 本發明關於晶片級半導體裝置之封裝。 包覆積體電路晶粒之晶片封裝在應用上的需求日益增加 作例如旱上型或可攜式電子產品，並應用在小型化的儲存 =置中，例如磁碟機。在許多這種應用中，對這種封裝之 需求在於要以非常高頻率來作業，基本上在i GHz以上，以 滿足類比或射頻（RF)裝置的需要，以及在蜂巢式電話中使 用的高速記憶體。 - 所謂的”晶片級封裝"常用於這樣的應用中。晶片級封裝習 用上使用打線接合做為該積體電路晶粒與該基板之間的内 連線。其有需要最小化該晶片級封裝的厚度到實用化的程 ，。其已製造出具有打線内連線之晶片級封裝，其整體封 裝南度之範圍在0.6 — 〇.8 mm之間。 進-步降低封裝厚度是料困難的，其主要有兩個原因 。弟―，打線内連線使用有限高度（對於”z"方向的尺寸具 有-下限)及間距(對於T及，，γ，，方向的尺寸具有一的 導線迴路，其由該晶粒的上表面處的接合墊行進，向上， 並通過而向下到該基板的上表面之上的接合位置，其為晶 ;:要附著於其上之處。然後該迴路以—保護性封膠材料包 覆。該導線迴路及封膠基本上貢獻了約02 _ 04 mm給該封 裝厚度。第二’因為這些封裝製作地較薄，在該封裝與該 -4- 本紙張尺錢用中g g家標準(CNS) A4規格(21QX297^y 1246170 五 發明説明（ 印刷電路板之間的，，穿_ 位在亨曰位的" 二層級内連線|，較不可靠。特別是， 祖在a日日粒的丨遮蔽”之 影響。 一 ^、、内連線最為受到負面 再者要改善電性效能會遭遇很 個原因。第一，甘& J佻戰，其至少有兩 接人本身美太難降低該信號路經長度，因為該打線 接。本身基本上的典型長度約為10 二， 結構必彡f為導兩时& 。亥封衣的 須向外= 了 環繞'線路；也就是說，該跡線必 、σ 】通迢，然後向内回到該焊球位置。 所需要的一封裝結橼為可繞過以上的障 步的封裝小型化，及改良的高速運作。 μ、進 發明概要 、 根據本發明’—種晶片封裝可達到小型化 覆晶内連線在該晶粒與該封板之門$、告,错由使用 … /、必钌衣暴板之間來達到良好的高速 運作’並將該晶片黏著在該封裝基板上與該焊球相同的側 邊上，做為第二層級内連線到該印刷電路板。 因此’在本發明一通用方面，其特徵在於一晶片級積體 咆路曰曰片封莰’其包含藉由覆晶内連線來黏著一晶粒到一 封裝基板的―第一表面，並在該封裝基板的第—表面上形 成第二層級的内連線。該晶粒提供有内連線凸塊，其固定 於該晶粒的第一表面上一連接位置的配置，而該覆晶内連 線係由將該晶粒的第一表面置於該封裝基板的第一表面附 近來構成，並使得該内連線凸塊接觸於該基板的第一表面 上一互補的内連線墊之配置，而在促進在該墊上凸塊接合 的條件之下。 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 1246170 A7 B7 五 、發明説明（ -發Γ/:内連線:塊在該晶粒與該基板之間提供 曰@ IP 4 ~隙可至少部份由—晶粒111著材料（例如- 日日片固者壤氣樹脂）來填 合丨认丄“ 粒與该間隙所組合的厚产 曰小、、由该基板與該印刷 又 的_、㈤ 私㈣之間的焊球㈣線所提供 ㈣内、、/乂該有效晶粒厚度可容納於該第二層級内連線 、I不會貝獻厚度到整體的封裳厚度(即〃Z"方向之 小型化）。 再者’ ®為根據本發明，不具有連接此第—晶粒到該美 板之打線接合，其可不需要容納一打線接合間距，而同時 可在X"及”γ”方向上進行小型化。 ’ 在一些具體實施例中’該内連線凸塊與該塾之間的連接 係為一固態連接’其由施加熱量及機械性力量來構成，以 ㈣凸塊對該墊來變形，而不用炫解該接合表面。這種固 態接合可提ί共比使用炫解接合連接所能得到的内連線幾何 要更為微細。 ^ 在一些具體實施例中，該晶粒係附著在大約該基板的中 心處，而該第二層級内連線的焊球係位在較接近於該基 之周緣。 在這種具體實施例中，在該晶粒的遮蔽中沒有第—岸級 的連接焊球，所以該第二層級内連線可靠性可優於習用的 晶片級封裝’其中在該晶粒的遮蔽下具有焊球。 在一些具體實施例中，該電性跡線形成在該封裝基板的 第一表面中的一内連線層中’而該跡線由該内連線塾向外 展開到該焊球附著位置。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) -6- 1246170
在這種具體實施例中，該信號路徑可由明顯地降低整體 跡線長度來最小化，藉由同時消除打線接合及跡線的環繞 線路。 在一些這種具體實施例中，一接地平面依選擇性提供在 該基板的第二表面上，並經由該基板中一或多値通道來連 接到該第二層級内連線球及/或連接到該内連線跡線。這種 接地平面不需要具有任何”保留”區域，並可為在整個第二 表面之上不受干擾的接地平面架構。這種接地平面架構可 提供良好的電性效能，其可達到微型條狀傳輸線。 、在-些具體f施例中，至少-些跡線係建構成.共平面波 辱，其中接地線係形成來在一平面介電材料上沿著該信號 線行進。 ~ 在其它具體實施例中，一第二晶粒係附著於該基板，其 在相對於該第一個的表面上，並經由通道連接到該第二層 級内連線及/或連接到第一晶粒跡線。該第二晶粒可由習; 的打線接合來附著。此構成一封裝具有與習用建構的打線 接合晶片級封裝大約相同的厚度，但其根據本發明包含誃 第一晶粒，其除了該打線接合的晶粒之外，亦承載在與誃 第二層級焊球相同的基板表面上。也就是說，一具有兩個 晶片的封裝可根據本發明此方面來容納在一整體封裝高产 内，其大約與習用僅具有一單一晶粒之打線接合的晶片封 裝相同。或者’该第二晶粒可由一覆晶内連線附著。因為 該覆晶架構可製成比該打線接合架構要低的高度，此具體 實施例提供一更薄的兩晶粒式封裝。 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 1246170 A7 B7 五、發明説明 圖式簡單說明 圖1所示為一習用具有打線接合内連線之晶片級封裝的橫 載面圖。 圖2所示為根據本發明一具體實施例的薄型高速晶片級封 裝的橫截面圖。 圖3所示為根據本發明另一具體實施例的薄型高速晶片級 封裝的橫截面圖。 圖4所示為根據本發明又另一具體實施例的薄型高速晶片 級封裝的橫戴面圖。 發明詳細說明 現在本發明將參考圖面來詳細說明，其代表本發明不同 的具體實施例。該圖面為圖形化，以顯示本發明的特徵及 /、與其匕知彳政及結構之關係，其並未依比例繪製。為了改 善表達的明確性，在圖面中所示的本發明具體實施例中， 一些元件對應於其它圖面中所示的元件並未全部特別地重 新編號，縱使其可在所有圖面中皆可立即辨識出來。為了 清晰起見，圖式中將不會特別晝出某些本發明内不需要了 解的細節。 表面11。該晶粒14係藉由連接到該晶粒 之打線接合16來電性連接到該封裝基板 現在請參考圖1，所示為一習用晶片級封裝的橫截面圖 其包含_晶粒14’其附著於—封裝基板㈣ 14上打線接合墊15 12，並内連線到該 基板12的表面中U之内連線 ^ ^ .... 且 °》日日拉，該打線接合 及該基板1 2的上表面1丨，皆包覆 白匕设在一枳製的塑膠封膠材
1246170
之内並文其保護。一組第二層級内連線球1 8係附著於 X基板12的一表面丨9上的位置，其相對於該晶粒所附著的 表面Π。如所瞭解的，該基板，在圖i中標示為12，其包含 一些特徵未示於圖中；特別是，例如電性連接結構（電性跡 線）’習用上係提供位在或接近於該表面u及該表面19，用 以刀別連接於來自該晶粒的打線接合，及連接於該焊球， 而通道行經通過該基板的厚度，用來電性内連線該基板的 上方及下方之特徵。 現在請參考圖2，所示為根據本發明一晶片級封裝的具體 貝屹例，標示為20。此處，該封裝基板22係提供在一第一 (”下方"）表面21上，其具有一組第二層級内連線焊球28。在 此具體f ίΜ列巾，這些第二層、級焊球係配置在#進該基板 的周緣。根據本發明，該晶粒24係使用一晶粒固著材料27 固定一晶粒固著區域29在該封裝基板的第一（”下方”）表面21 之上，其基本上為一晶粒固著環氧樹脂。在該晶粒及該基 板之間的内連線係藉由内連線凸塊25來製成。覆晶内連線 為已知；通常該内連線凸塊25被附著於導電跡線（未示於圖 中）上一配置中的内連線位置，其係位在或靠近該晶粒的表 面23，然後這些内連線凸塊即接合到在該基板中或其上的 ‘電跡線上之互補配置（未示於圖中）中的連接位置。較佳地 是’泫内連線凸塊25係以一固態方式接合到其個別的墊； 也就是說，該凸塊係藉由同時對該墊強迫接合，並施加足 夠的熱量來對該墊來變形該接合，以熱機械性地連接到該 墊，其不需要熔解該接合材料或該墊材料。這種固態内連 -9- 本纸張尺度適用中國國家標準(CNS) Α4規格(210 X 297公ϋ---- A7 B7 1246170 玉、發明説明（ 線可提供内連線幾何在範圍小於約 0.1 mm的間距。 不同特徵的尺寸可被選擇來最小化該封裝的整體厚度。 舉例而言’該凸塊結構及内連線裝置可設計使得在該晶粒 表面23及該基板29的晶粒固著表面之間的間隙係小於約 0·025 mm。因為在此具體實施例中該晶粒係在該基板的下 方表面上進行’且因為其厚度容納在該基板的下方表面及 該底部積體電路之間的間隙内，其受限於該第二層級内連 線球28的尺寸，該整體封裝在此具體實施例中較薄，其量 ‘相對於約5亥打線接合晶粒及其封膠的厚度，如圖1的範例 所不。再者，因為該第二層級内連線結構係位在靠近該基 板的周緣，該第二層級可靠性係優於在該晶粒-的遮蔽中的 焊球所能得到的可靠性。 ”視而要，雖然非必要地，一接地平面26可提供成為一 貝貝上連績的導電片（例如像是銅的金屬），其大體上覆蓋爷 基的上表面。穿過該基板的—或多個通道（未示於圖中) f可形成來連接該接地平面到位在該基板的表面2 1處之 適當的第二層級焊球（”接地球"）。 田碌丞板的表面△ 1 τ Μ逆丧位置所行進 %跡線可根據本發明直接行進到所指定的焊球連接位 在-些具體實施例中，這些導電跡線係形成為共平面 ’其結構為已知。 、—V丹Μ貫施例中，該封裝基板的厚度大丨 mm ’由該基板表面量測的該焊球高度大 曰止V ΛΑ J III 111 曰曰’、、向度大約為〇· 18 mm ;此造成整體封裝高度 -10- 丨x 297公釐） 1246170 A7 B7 五 發明説明（^ ~- 在這些尺寸中有可能進一步降低，所以根據本發 月可^到整體封裝高度小於0.4 mm。 再者最長的導電跡線之長度在一具體實施例中可小於 m其必須以0.5 mm間距來配置焊球列在周緣。此可 提供額外的高電性效能。 ®3及4所示出本發明的其它具體實施例在如及利處，其 中4封衣包含由覆晶内連線附著一第一晶粒到與該第二層 級内連線結構中該基板的相同（’，下方，，）表面，一般可參考圖 2所述，及一第二晶粒，其固定於該封裝基板的第二（”上方，，) 表面。在圖3中，該第二晶粒係使用習用的打線接合内連線 土板而在圖4中’該第二晶粒係由覆晶内連線來内連 線於該基板。 在圖J中，該第一晶粒24使用一晶粒固著材料27固定在該 基板的第一（”下方”）表面21的中央晶粒附著區域中，並藉 由内連、、泉凸塊25來構成内連線；而第二層級内連線球28係 附著到A近於该基板的周緣之第一表面，如參考圖2之說 明所述。一第二晶粒34係附著於該基板32的相對（"上方"）表 面3 1之上，並錯由連接到晶粒3 4上打線接合蟄3 5之打線接 合j6而電性連接到該封裝基板，並連接到該基板32的表面 J 1中的内連線位置。該晶粒及相關的打線接合係包覆在封 膠材料37中，並受其保護。在該上表面上或其中的特徵係 經由行進通過該基板的通道（未示於圖中）而電性連接到該下 表面上或其中的特徵。 在圖J之具體實施例中該第二晶粒及相關結構的尺寸，可 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱） 1246170 五、發明説明（ 製成類似於圖i所示之習用 寸。大 白用封衣中该晶粒14及相關結構之尺 制 圖J所不，根據本發明該封裝的整體封裝高度可 一 、、，仁在圖3的具體實施例中，該封裝 ”、.兩曰曰粒式封裝’且其為一兩晶粒式 I 一 晶㈣具h好的電氣特性，如以上參相2所述。 -更加薄的整體兩晶粒式封裝，其中該第二晶粒也可具 有良好的電性效能，其可建構成如圖4中之4〇所示。此處， Μ之"A她例，该第一晶粒24使用一晶粒固著材料27 固定在該基板32的第一（”下方”）表面21之中央曰曰曰粒固著區域 上並藉由内連線凸塊25構成内連線；而第二層級内連線 球28被附著於靠近該基板的周緣之第一表面21 :如參考圖】 所述。然而在此具體實施例中，該第二晶粒係使用一覆晶 内連、’泉而葸性連接到该基板。也就是說，晶粒料係使用一 晶粒固著材料47來固定到該基板42的第二（”上方”）表面41上 的一第二晶粒固著區域，並藉由内連線凸塊45來内連線到 该基板。如圖3之具體實施例，在該上表面上或其中的特徵 係經由行進通過該基板的通道（未示於圖中）而電性連接到該 下表面上或其中的特徵。此封裝仍可比如圖3所建構者要薄 ，因為該晶粒及覆晶内連線本身可比一晶粒或打線接合内 連線要薄。 其它具體實施例皆包含在以下申請專利範圍中。 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)

Claims (1)

1246170 ^0911=88气專利申請案Q4. 6 i〇 中文申％專利範圍替拖木(94年6月、申請專利範圍 1. 2. 3. 4. 5. 6. 積體電路晶片封裝’其包含：一封裝基板， 壤安二表面具有導電跡線；一晶粒，藉由覆晶内連 ㈣裝基板的該第—表面之導電跡線上之連接 軛的楚弟二層級内連線，其形成並附著至該封裝基 板勺弟-表面之導電跡線上之附著位置i。 二:請：利範圍第1項之封裝，其中該晶粒具有-内連線 於該晶粒之第—表面中—連接位置的配置 且後晶内連線係、由放置該晶粒的第-表面在該封裳 二=:帛纟面附近’並將該内連線凸塊以互補性配置 該基板的第一表面在導電跡線上之連接位置，其 條件為需促進該連接位置上的凸塊之接合。 ’、 如申請專利範圍第旧之封裝，其中該晶粒的第一表面及 5亥基板的第一表面之間的間隙係至少由-晶粒固著材料 所部份填充。 W 如申請專利範圍第】項之封裝，其中該第二層級内連線的 mm-凸出物’而該第—晶粒的厚度與該晶粒的第 一表面及該基板的第一表面之間的間隙之總和小於該凸 出物。 如申請專利範圍第2項之封裝，其中該内連線凸塊及該連 接=置的連接為_gj態連接，其藉由施加熱量及機械性 力量來對該連接位置變形該凸塊所構成，而不需要熔解任 一配合表面。 如申請專利範圍第旧之封裝’其中該晶粒係大約附著在 該基板的第-表面之中心，而第二層級内連線的焊球係 本紙張尺度適用中國國家標準(CNS) Ad規格(21〇χ297公釐) 1246170 申請專利範圍 位在更靠近該基板的周緣。 如申請專利範圍第1 从卡坦糾+ 封裝’其中一接地平面係侬逸遥 性來美供在該基板的_第二表面上。 作依k擇 如申請專利範圍笛 闺第1項之封裝，其中至少一 b導 建構成共平面波導。 一蜍電跡線係 如申請專利範圍第1項之封裝 的一第二表面之第二晶粒。 10·如申請專利範圍第9項之封 接合至該基板之第_、矣而々\中，.Μ π 一日日料你田玎踝 連接到該基板。表面之導電跡線上之連接位置來内 η·如申請專利範圍第9項之封裝，其中該第二晶粒係由一覆 曰曰内連線至4基板之S二表面之導電跡線上之連接位置 來内連接到該基板。 7. 8. 9. 進一步包含附著於該基板 其中该第二晶粒係由打線 -2 - 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐）
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JP2004523121A (ja) 2004-07-29
US20020121707A1 (en) 2002-09-05
KR20040030509A (ko) 2004-04-09
EP1371094A4 (en) 2009-07-15
US20050056944A1 (en) 2005-03-17
JP2009038391A (ja) 2009-02-19
EP1371094A1 (en) 2003-12-17

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