CN111508947A - 半导体封装和印刷电路板 - Google Patents

半导体封装和印刷电路板 Download PDF

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Publication number
CN111508947A
CN111508947A CN202010052472.7A CN202010052472A CN111508947A CN 111508947 A CN111508947 A CN 111508947A CN 202010052472 A CN202010052472 A CN 202010052472A CN 111508947 A CN111508947 A CN 111508947A
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China
Prior art keywords
substrate
semiconductor package
circuit board
semiconductor chip
printed circuit
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CN202010052472.7A
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English (en)
Inventor
许家豪
陈泰宇
蔡宪聪
刘兴治
许耀邦
陈麒元
李钟发
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MediaTek Inc
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MediaTek Inc
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Priority to CN202211415765.2A priority Critical patent/CN115884499A/zh
Publication of CN111508947A publication Critical patent/CN111508947A/zh
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Abstract

本发明公开一种半导体封装，包括：基底，包括上表面和与所述上表面相对的下表面；射频结构，嵌入所述基底中，并靠近所述基底的上表面；集成电路晶粒，以倒装芯片的方式安装在所述基底的下表面上；导电结构，设置在所述基底的下表面上并围绕所述集成电路晶粒布置；以及金属热界面层，包括与所述集成电路晶粒的背面直接接触的背面金属层，以及印刷在所述背面金属层上的焊膏。这样可以通过集成电路晶粒的背面进行散热，并且金属热界面层加快了散热速度，提高了散热效率。

Description

半导体封装和印刷电路板
技术领域
本发明涉及机械技术领域，尤其涉及一种半导体封装和印刷电路板。
背景技术
如本领域中已知的，半导体芯片封装通常包括集成电路(integrated circuit，IC)晶粒和封装IC晶粒的模塑料。在运行过程中，IC晶粒会产生大量热量，这可能会损坏IC晶粒或降低IC的可靠性。例如，在混合芯片级封装(hybrid chip scale package，混合CSP)中，一个IC晶粒(例如SoC(system on chip)晶粒)产生的热量可能不利于邻近的IC晶粒(例如，堆栈在SoC晶粒上的DRAM(Dynamic Random Access Memory，动态随机存取存储器)晶粒)，从而导致芯片整体性能降低。
为了将热量从IC晶粒消散，半导体芯片封装经常与外部散热结构耦合，外部散热结构例如为附接到IC晶粒的散布器(spreader)或散热器(heat sink)。为了将热量散发到周围环境，通常通过在接触表面上施加诸如导热油脂或导电聚合物之类的热界面材料(thermal interface material，TIM)，将散热结构耦合到半导体芯片封装的接触表面。
然而，涉及使用TIM的常规热解决方案并不令人满意。使用TIM的传统设计具有诸如热瓶颈和较差的粘附性的问题。业界期望在IC晶粒与散热结构之间具有低的接触阻抗(contact resistance)或低的热传导阻抗和和良好的热界面，以从IC晶粒通过散热结构有效地进行热传导。业界还期望提供一种在部件之间可以采用的改进的热传递机构/介质，以有效地将热量从IC晶粒传递出去。
发明内容
有鉴于此，本发明提供一种半导体封装和印刷电路板，以更加有效的散热。
根据本发明的第一方面，公开一种半导体封装，包括：
基底，包括上表面和与所述上表面相对的下表面；
射频结构，嵌入所述基底中，并靠近所述基底的上表面；
集成电路晶粒，以倒装芯片的方式安装在所述基底的下表面上；
导电结构，设置在所述基底的下表面上并围绕所述集成电路晶粒布置；以及
金属热界面层，包括与所述集成电路晶粒的背面直接接触的背面金属层，以及印刷在所述背面金属层上的焊膏。
根据本发明的第二方面，公开一种印刷电路板组件，包括：
印刷电路板，具有直接面对基底的下表面的上表面，其中所述印刷电路板包括在所述印刷电路板的上表面上的导电导热垫的阵列，位于所述印刷电路板内且位于所述导电导热垫的阵列下方的导热通孔，安装在所述印刷电路板的下表面的散热结构，其中所述散热结构与所述导热通孔热接触；以及
如上所述的半导体封装，安装在所述导电导热垫的阵列上。
根据本发明的第三方面，公开一种半导体封装，包括：
基底，包括底表面和与所述底表面相对的顶表面；
第一半导体芯片，安装在所述基底的顶表面上；
第二半导体芯片，通过晶粒附着膜安装在所述第一半导体芯片上；
散热元件，通过高导热晶粒附接膜安装在所述第一半导体芯片上或所述第二半导体芯片上；以及
模塑料，封装所述第一半导体芯片，所述第二半导体芯片和所述散热元件。
本发明的半导体封装由于在集成电路晶粒的背面设置有金属热界面层，并且金属热界面层包括与所述集成电路晶粒的背面直接接触的背面金属层，以及印刷在所述背面金属层上的焊膏。这样可以通过集成电路晶粒的背面进行散热，并且金属热界面层加快了散热速度，提高了散热效率。
附图说明
图1是根据本发明的一个实施例的半导体封装的剖视图；
图2是示出根据本发明的一个实施例的包括图1中的半导体封装的示例性印刷电路板组件的示意性截面图；
图3至图6是示出根据本发明的各个实施例的半导体封装的示意性截面图。
具体实施方式
以下描述是实施本发明的最佳构想模式。进行该描述是为了说明本发明的一般原理，而不应被认为是限制性的。本发明的范围由所附权利要求确定。
将针对特定实施例并参考某些附图来描述本发明，但是本发明不限于此，而是仅由权利要求书来限制。所描述的附图仅是示意性的而非限制性的。在附图中，出于说明的目的，一些元件的尺寸可能被放大并且未按比例绘制。在本发明的实践中，尺寸和相对尺寸不对应于实际尺寸。
通常，本发明涉及一种半导体封装，该半导体封装包括至少一个集成电路芯片，其以例如“倒装芯片(flip chip)”构造附接到基板。在这种倒装芯片的配置中，凸块形成在IC晶粒的信号焊盘或端子上，并且IC晶粒可以倒置(“翻转”)并通过回流凸块附着在基板上，以便它们附着在基板表面上的相应的焊盘上。IC晶粒可以是多种类型的IC晶粒之一。例如，根据各种实施例，IC晶粒可以是射频(radio-frequency，RF)IC晶粒，微处理(microprocessor)器芯片，专用集成电路(application-specific integratedcircuit，ASIC)或存储器芯片。
基板可以是相关领域技术人员已知的不同类型的基板之一(例如，有机或无机基板)。基板可由与介电材料结合的一个或多个导电层制成。例如，电介质材料可以由各种物质制成，例如双马来酰亚胺三嗪(bismaleimide triazine，BT)。导电层可以由金属或金属的组合(合金)制成，例如铜和铝，其有助于IC晶粒和焊球之间的耦合。可以通过例如蚀刻导电层在导电层中形成迹线或布线图案。基板可以是单层，两层或多层基板。
示例性半导体封装可以是具有天线阵列结构的RFIC芯片封装，该天线阵列结构特别适合毫米波(millimeter wave，mmW)应用或雷达系统。然而，应当理解，本发明的原理不应限于任何特定的封装类型或IC晶粒。相反，本发明的原理广泛地涉及用于在包括集成电路封装和传热装置的印刷电路板(printed circuit board，PCB)组件的制造过程中改进热界面材料应用的技术。
图1是示出根据本发明的一个实施例的示例性半导体封装的示意性截面图。如图1所示，半导体封装1包括基底10，基底10具有嵌入在基底10的上表面10a附近的射频(RF)结构11。在一些实施例中，基底10可以是封装基板，硅中间体(silicon interposer)或印刷电路板(PCB)。在其他实施例中，射频(RF)结构11包括天线阵列，例如，射频(RF)结构11可以包括顶部天线层111和与顶部天线层间隔开的底部天线层112。例如，可以在顶部天线层111和底部天线层112之间插入至少一个介电层113。根据一个实施例，顶部天线层111和底部天线层112可以在基底10的较上层的金属层中形成，但不限于此。基底10可以包括用于互连的金属迹线114和通孔115。其中，RF结构11可以是形成基底10时共同形成的，例如在形成布线(例如金属迹线114和通孔115等)时，将底部天线层112和顶部天线层111形成，并且期间形成至少一个介电层113，因此RF结构11可以理解为包含在基底10中。
根据一个实施例，例如，半导体封装1可以进一步包括IC晶粒20，例如安装在基底10的下表面10b上的RFIC晶粒。IC晶粒20可以以倒装芯片的方式安装在下表面10b上，使得IC晶粒20的背面20b暴露并且可用于散热。倒装芯片型连接是一种用于将倒装的IC晶粒20与外部电路互连的方法，其具有诸如设置在IC晶粒20的芯片焊盘上的微凸块或铜柱凸块之类的凸块202。凸块202对准并电连接设置在基底10的下表面10b上的铜焊盘116上。可选地，可以将底部填充物210施加到IC晶粒20和基底10的下表面10b之间的间隙中。
例如，根据一个实施例，半导体封装1可以进一步包括多个导电焊盘118，布置在基底10的下表面10b上并且围绕IC晶粒20布置。导电焊盘118可以电连接至电路，包括通过金属迹线114和通孔115(电连接到)的基底10的RF结构11。多个导电结构120，例如球栅阵列(ball grid array，BGA)球(或焊球)可以分别设置在导电焊盘118上，用于电连接包括基底10的RF结构11至具有外部电路装置，例如印刷电路板(PCB)。
根据一个实施例，例如，半导体封装1可以进一步包括金属热界面层30。金属热界面层30可以是金属双层结构，其包括与IC晶粒20的背面20b直接接触的背面金属层310，和共形地印刷在背面金属层310上的焊膏(或预焊剂)320。其中共形地可以是说背面金属层310与焊膏320的形状相同，制作方式相同。根据一个实施例，优选地，背面金属层310可以包括Au(金)，但不限于此。例如，背面金属层310可以是溅射到IC晶粒20的背面20b上的Au层。采用这种方式可以利用IC晶粒20的背面进行散热，并且背面金属层310和焊膏320的设置和组合可以提高散热效率，此外这种将背面金属层310和焊膏320的组合形成在IC晶粒20的背面方式易于制造，有利于制程设计。
例如，焊膏(或预焊剂)320可以通过模版印刷(stencil printing)方法形成，但不限于此。例如，焊膏320可包括商业用途的任何无铅(lead-free)焊料，其可包含锡，铜，银，铋，铟，锌，锑和其他微量的金属。例如，根据一个实施例，焊膏320可以比背面金属层310更厚，以便于后续安装。值得注意的是，金属热界面层30不包括常规的热界面材料(TIM)，例如导热油脂或导电聚合物。相比先前的TIM，本实施例中的焊膏320和背面金属层310导热性能更好，并且还可以方便后续的安装。
根据一个实施例，底部填充物210，IC晶粒20和金属热界面层30的组合厚度基本上等于从基底10的下表面10b测量的导电结构120的球高h。需要说明的是，在一些实施例中，导电焊盘118可以位于基底10的下表面10b之内，也即导电焊盘118嵌入在基底10内部，此时导电结构120的高度即为从基底10的下表面10b开始测量直到导电结构120的另一侧的高度。如果如图1和图2所示，导电焊盘118位于基底10的下表面10b的表面上时，在安装(将图1所示的半导体封装1安装到图2中的PCB 4)时，导电结构120会被压缩，因此导电结构120会包裹到导电焊盘118的外侧壁(例如继而接触到基底10的下表面10b)，这样导电结构120的高度也为从基底10的下表面10b开始测量直到导电结构120的另一侧的高度。实际上，在安装后，导电结构120的下表面与金属热界面层30的下表面是齐平的。
请参考图2，图2为根据本发明一实施例的包括图1中的半导体封装的示例性PCB组件的示意性截面图。如图2所示，示例性PCB组件2包括PCB4，该PCB 4具有直接面对基底10的下表面10b的上表面4a。根据一个实施例，可以在PCB 4的上表面4a上的阻焊剂层402中的阻焊剂开口402a内布置铜的导电导热垫(conductive thermal pad)410的阵列。
根据一个实施例，导电导热垫410的阵列的跨度(span)可以与IC晶粒20的背面20b的面积相对应。根据一个实施例，导电导热垫410的阵列的跨度可以是略微的大于IC晶粒20的背面20b的面积。例如，从IC晶粒20的边缘到导电导热垫410的阵列的边缘的距离可以是大约150微米，但不限于此。
根据一个实施例，可以在相邻的导电导热垫410之间形成狭缝或间隙411。根据一个实施例，在导电导热垫410的阵列下方的PCB 4内形成多个导热通孔420。在一个实施例中，导热通孔420分别与导电导热垫410热接触，例如每个导热通孔420分别与每个导电导热垫410热接触。根据一个实施例，导热通孔420是电镀的穿孔(电镀通孔)，即在通孔中电镀有金属，以导电及散热。根据一个实施例，诸如散热器之类的散热结构5可以安装在PCB 4的下表面4b上。散热结构5与导热通孔420热接触，因此热量可以通过导热通孔420传导到散热结构5，进而散发出去。
根据一个实施例，如图1所示的半导体封装1安装到PCB 4的上表面4a上，使得焊膏320层压到导电导热垫410的阵列上。在适当的压力下，焊膏320可以被强压(或挤压)到狭缝或间隙411中。通过提供这种构造，可以产生更多的散热表面积。导电结构120与PCB 4的上表面4a上的匹配焊盘412对准。可以对焊膏320和导电结构120进行回流制程以形成永久性接合。金属热界面层30用作高效热传递介质，以允许热能从IC晶粒20快速移动到导电热焊盘410以及PCB 40的导热通孔420，接着到散热结构5。本实施例中，为避免过高的温度对RF结构和IC晶粒20等的不利影响，在IC晶粒20的背面设置散热路径，这样可以使热量通过背面的散热路径散出，而减小对RF结构的影响。此外，使用本发明是有利的，因为对焊膏320和导电结构120进行回流制程可以显著改善半导体封装1和PCB 4之间的粘附性。
请参考图3至图6。图3至图6是示出根据本发明的各个实施例的半导体封装的示意性截面图。例如，说明性半导体封装可以是具有倒装芯片晶粒和堆栈在倒装芯片晶粒上的引线接合晶粒的混合CSP。
如图3所示，半导体封装3a包括具有顶表面100a和底表面100b的基底100。诸如焊球的多个连接元件1002可以设置在底表面100b上用于进一步的连接。半导体芯片101安装在基底100的顶表面100a上。在非限制性示例中，半导体芯片101可以是系统单芯片(system-on-a-chip，SoC)，并且可以在运行期间产生热量。
根据一个实施例，通过将在半导体芯片101的有源表面上的凸块(微凸块或铜柱凸块)1011与在基底100的顶表面100a上的匹配焊盘1001对准和连接，半导体芯片101可以以倒装芯片的方式安装到顶表面100a上。可以应用可选的底部填充物110以填充半导体芯片101和基底100的顶表面100a之间的间隙。
根据一个实施例，半导体芯片(或半导体封装)103可以直接堆栈在半导体芯片101上，并且可以通过使用引线接合WB电耦合到基底10。在非限制性示例中，半导体芯片103可以是存储芯片；但是，可以不限于此。在另一示例中，半导体芯片103可以是已知的良好晶粒(Known Good Die，KGD)芯片，但是不限于此。根据一个实施例，可以通过使用包括例如环氧粘合剂层的晶粒附着膜(die attach film，DAF)102将半导体芯片103粘附到半导体芯片101的顶表面。根据一个实施例，例如，DAF 102具有约0.3W/m-K的热导率。半导体芯片101和103也可以是半导体晶粒。
根据一个实施例，半导体封装3a还包括封装内的散热元件105，例如虚设硅晶粒，封装内的散热元件105通过使用高导热晶粒附接膜(高导热DAF)104粘附在半导体芯片103的顶表面上。根据一个实施例，高导热DAF 104是具有高导热特性的粘合膜。根据一个实施例，高导热DAF 104具有比DAF102更高的导热率。例如，根据一个实施例，高导热DAF 104可以具有约2-50W/m-K的导热率。本实施例中散热元件105采用高导热DAF 104安装在半导体芯片103的顶表面上，可以使半导体芯片101和103产生的热量通过高导热DAF 104和散热元件105快速的散发出去，从而提高散热效率。
根据一个实施例，半导体封装3a还包括模塑料500，其密封半导体晶粒101，半导体芯片103和散热元件105。根据一个实施例，例如，模塑料500可以具有约2-8W/m-K的导热率，又例如，模塑料500可以具有1W/m-K的导热率。本实施例中的高导热DAF 104的导热率可以比模塑料500和DAF102的导热率都高，因此可以更快的将热量从半导体封装中散发出去，特别是将半导体芯片101产生的热量更高效的传递出去。
同样，在图4中，半导体封装件3b包括基底100，以倒装芯片方式安装在基底100上的诸如SoC之类的半导体芯片101，通过使用DAF 102粘附到半导体芯片101上的诸如DRAM芯片之类的半导体芯片103，通过使用高导热DAF 104粘附到半导体芯片103上的诸如虚设硅芯片之类的散热元件104。图4中的半导体封装3b与图3中的半导体封装3a不同之处在于，图4中的半导体封装3b的散热元件105的顶表面105a暴露于空气，这样可以进一步提高散热效率，使热量通过散热元件105的顶表面105a更快的散发出去。为了形成这种构造，可以对模塑料500进行抛光或研磨处理。在去除一部分模塑料500之后，散热元件105的顶表面105a可以与模塑料500的顶表面500a齐平。
在图5中，如上描述，通过使用高导热DAF 104将半导体封装5a的散热元件105附接到半导体芯片101的顶表面，来代替将散热元件105附接到半导体芯片103上。因此，半导体芯片103和散热元件105都以并排的方式附接到半导体芯片101的顶表面上。由于一般半导体芯片101为主要热源，因此可以仅将散热元件105通过高导热DAF 104安装到半导体芯片101上，这样可以更快速的将半导体芯片101产生的热量散发出去。
同样，在图6中，半导体封装件5b包括基底100，以倒装芯片方式安装在基底100上的诸如SoC之类的半导体芯片101，通过使用DAF 102粘附到半导体芯片101上的诸如DRAM芯片之类的半导体芯片103，通过使用高导热DAF 104粘附到半导体芯片101上的诸如虚设硅芯片之类的散热元件104。图6中的半导体封装5b与图5中的半导体封装5a不同之处在于，图6中的半导体封装5b的散热元件105的顶表面105a暴露于空气。这样散热会更快，半导体芯片101的热量可以直接通过高导热DAF 104和散热元件105到达外界空气，更快的散热。
根据一个实施例，半导体芯片101是半导体封装3a的主要热源，并且需要将热量从半导体封装3a迅速地散发到周围环境。通过提供图3到图6的配置，显著提高了散热性能(散热性能提高了约50％)。例如，图6中的示例性半导体封装5b的测量的θJC(θJC)可以为大约2.20。θJC代表从半导体芯片101到散热路径的散热能力，越高表示散热能力越强。
本领域的技术人员将容易地观察到，在保持本发明教导的同时，可以做出许多该装置和方法的修改和改变。因此，上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。

Claims (10)

1.一种半导体封装，其特征在于，包括：
基底，包括上表面和与所述上表面相对的下表面；
射频结构，嵌入所述基底中，并靠近所述基底的上表面；
集成电路晶粒，以倒装芯片的方式安装在所述基底的下表面上；
导电结构，设置在所述基底的下表面上并围绕所述集成电路晶粒布置；以及
金属热界面层，包括与所述集成电路晶粒的背面直接接触的背面金属层，以及印刷在所述背面金属层上的焊膏。
2.如权利要求1所述的半导体封装，其特征在于，所述射频结构包括：顶部天线层和与所述顶部天线层间隔开的底部天线层；以及至少一个介电层，插入在所述顶部天线层和所述底部天线层之间。
3.如权利要求1所述的半导体封装，其特征在于，所述基底包括用于互连的金属迹线和通孔，所述导电结构通过所述金属迹线和所述通孔电连接到所述基底的所述射频结构。
4.如权利要求1所述的半导体封装，其特征在于，还包括：
底部填充物，位于所述集成电路晶粒和所述基底的下表面之间的间隙中。
5.如权利要求1所述的半导体封装，其特征在于，所述底部填充物，所述集成电路晶粒和所述金属热界面层的组合厚度等于从所述基底的下表面测量的所述焊球的焊球高度。
6.如权利要求1所述的半导体封装，其特征在于，所述焊膏比所述背面金属层厚。
7.一种印刷电路板组件，其特征在于，包括：
印刷电路板，具有直接面对基底的下表面的上表面，其中所述印刷电路板包括在所述印刷电路板的上表面上的导电导热垫的阵列，位于所述印刷电路板内且位于所述导电导热垫的阵列下方的导热通孔，安装在所述印刷电路板的下表面的散热结构，其中所述散热结构与所述导热通孔热接触；以及
如权利要求1所述的半导体封装，安装在所述导电导热垫的阵列上。
8.如权利要求7所述的印刷电路板组件，其特征在于，所述焊膏与所述导电导热垫的阵列直接接触。
9.如权利要求8所述的印刷电路板组件，其特征在于，所述导电导热垫之间的狭缝，所述狭缝填充有所述焊膏。
10.一种半导体封装，其特征在于，包括：
基底，包括底表面和与所述底表面相对的顶表面；
第一半导体芯片，安装在所述基底的顶表面上；
第二半导体芯片，通过晶粒附着膜安装在所述第一半导体芯片上；
散热元件，通过高导热晶粒附接膜安装在所述第一半导体芯片上或所述第二半导体芯片上；以及
模塑料，封装所述第一半导体芯片，所述第二半导体芯片和所述散热元件。
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