CN112447621A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN112447621A
CN112447621A CN202010595487.8A CN202010595487A CN112447621A CN 112447621 A CN112447621 A CN 112447621A CN 202010595487 A CN202010595487 A CN 202010595487A CN 112447621 A CN112447621 A CN 112447621A
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China
Prior art keywords
semiconductor chip
semiconductor
heat dissipation
package
dissipation member
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Pending
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CN202010595487.8A
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English (en)
Inventor
金宣澈
吴琼硕
金泰勳
金坪完
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN112447621A publication Critical patent/CN112447621A/zh
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Abstract

提供了一种半导体封装件，所述半导体封装件包括：封装基底；第一半导体芯片，在封装基底上；第二半导体芯片，在第一半导体芯片的上表面上；绝缘层，在第一半导体芯片的表面和第二半导体芯片的表面上；散热构件，在绝缘层上，使得散热构件包括处于第一半导体芯片的上表面上的未设置第二半导体芯片的区域以及处于第二半导体芯片的上表面上的区域；模制构件，在封装基底上并且包封第一半导体芯片、第二半导体芯片和散热构件，使得模制构件暴露散热构件的上表面的至少一部分；以及加强构件，在散热构件和模制构件上。

Description

半导体封装件
于2019年8月28日在韩国知识产权局提交的且名称为“Semiconductor Package(半导体封装件)”的第10-2019-0105755号韩国专利申请通过引用全部包含于此。
技术领域
实施例涉及一种半导体封装件。
背景技术
随着电子组件的高功能性和小型化的趋势，已经使用具有各种功能的多个半导体芯片嵌入在单个封装件中的系统级封装(SIP)技术来实现封装件的高性能和小型化。
发明内容
实施例可以通过提供一种半导体封装件来实现，该半导体封装件包括：封装基底；第一半导体芯片，位于封装基底上；至少一个第二半导体芯片，位于第一半导体芯片的上表面的区域上；绝缘层，位于第一半导体芯片的表面和所述至少一个第二半导体芯片的表面上；散热构件，位于绝缘层上，使得散热构件包括处于第一半导体芯片的上表面上的未设置所述至少一个第二半导体芯片的区域以及处于所述至少一个第二半导体芯片的上表面上的区域；模制构件，位于封装基底上并且包封第一半导体芯片、所述至少一个第二半导体芯片和散热构件，使得模制构件暴露散热构件的上表面的至少部分；以及加强构件，位于散热构件和模制构件上。
实施例可以通过提供一种半导体封装件来实现，该半导体封装件包括：封装基底；第一半导体芯片，位于封装基底上；散热构件，位于第一半导体芯片的上表面的部分上；模制构件，位于封装基底上并且覆盖封装基底的上表面、第一半导体芯片的一个侧表面和散热构件的一个侧表面，使得模制构件暴露散热构件的上表面的至少部分；以及加强构件，位于散热构件和模制构件上，其中，加强构件包括聚合物化合物，并且具有大于散热构件的热膨胀系数且大于模制构件的热膨胀系数的热膨胀系数。
实施例可以通过提供一种半导体封装件来实现，该半导体封装件包括：封装基底；第一半导体芯片，位于封装基底上；至少一个第二半导体芯片，位于第一半导体芯片上；绝缘层，位于封装基底的表面、第一半导体芯片的表面和所述至少一个第二半导体芯片的表面上；散热构件，位于绝缘层上，使得散热构件包括处于第一半导体芯片上的未与所述至少一个第二半导体芯片叠置的区域以及当从垂直于封装基底的上方观看时处于所述至少一个第二半导体芯片上的与第一半导体芯片叠置的区域；模制构件，位于封装基底上并且包封第一半导体芯片、所述至少一个第二半导体芯片和散热构件中的每个的至少部分；以及加强构件，位于散热构件和模制构件上。
实施例可以通过提供一种半导体封装件来实现，该半导体封装件包括：基底；第一半导体芯片，位于基底上；第二半导体芯片，位于第一半导体芯片上；绝缘层，位于第一半导体芯片的表面和第二半导体芯片的表面上；散热构件，位于绝缘层上；模制构件，包封第一半导体芯片、第二半导体芯片和散热构件中的每个的至少部分；以及加强构件，位于散热构件和模制构件上，其中，散热构件和模制构件中的每个独立地具有5ppm/℃至40ppm/℃的热膨胀系数(CTE)，并且加强构件具有50ppm/℃或更大的CTE。
附图说明
通过参照附图详细描述示例性实施例，特征对于本领域技术人员将是明显的，在附图中：
图1示出了根据示例实施例的半导体封装件的侧面剖视图；
图2示出了图1中的半导体封装件的局部构造的平面图；
图3至图8示出了制造图1中的半导体封装件的方法中的各阶段的侧面剖视图；
图9示出了示出根据图1中的半导体封装件的加强构件的物理性质(CTE和弹性模量)施加到散热构件的应力的曲线图；
图10A示出了当在半导体封装件中不存在加强构件时在散热构件中出现的裂纹的剖视图；
图10B和图10C示出了通过具有高热膨胀系数的加强构件来释放施加到半导体封装件的应力的原理的剖视图；
图11示出了根据示例实施例的半导体封装件的侧面剖视图；
图12示出了根据示例实施例的半导体封装件的侧面剖视图；
图13示出了根据示例实施例的半导体封装件的侧面剖视图；
图14示出了图13中的半导体封装件的局部构造的平面图；
图15示出了根据示例实施例的半导体封装件的侧面剖视图；
图16示出了根据示例实施例的半导体封装件的侧面剖视图；以及
图17至图22示出了制造图16中的半导体封装件的方法中的各阶段的侧面剖视图。
具体实施方式
图1示出了根据示例实施例的半导体封装件100A的侧面剖视图。图2示出了图1中的半导体封装件100A的局部构造的平面图。图1示出了沿着图2中的局部构造的线I-I'截取的剖视图。
参照图1和图2，根据示例实施例的半导体封装件100A可以包括封装基底110、第一半导体芯片120、至少一个第二半导体芯片130a和130b、散热构件150、模制构件160以及加强构件170。
半导体封装件100A可以是其中嵌入有各种类型的半导体芯片的系统级封装件(SIP)。例如，第一半导体芯片120可以是逻辑芯片，并且至少一个第二半导体芯片130a和130b可以是存储器芯片。
封装基底110可以是半导体封装基底，例如，印刷电路板(PCB)、陶瓷基底、带式引线基底等。例如，封装基底110可以包括热固性树脂(诸如，环氧树脂)或热塑性树脂(诸如，聚酰亚胺)或者光敏绝缘层。在实施方式中，基底可以包括诸如预浸料、味之素复合膜(ABF)、FR-4、双马来酰亚胺三嗪(BT)、可光成像电介质(PID)树脂等的材料。
在实施方式中，封装基底110可以包括分别在彼此背对的上表面和下表面上的多个垫以及将多个垫彼此电连接的引线。此外，封装基底110的下部还可以包括连接到封装基底110的下表面上的垫的连接端子114。
连接端子114可以电连接到外部装置，诸如，主板。例如，连接端子114可以具有倒装芯片连接结构，该倒装芯片连接结构包括焊球、导电凸块或栅格阵列(诸如，引脚栅格阵列、球栅格阵列或平面栅格阵列)。
第一半导体芯片120可以在封装基底110的上表面(面向第一半导体芯片的表面)上，并且可以电连接到封装基底110的上表面上的垫。例如，第一半导体芯片120可以以倒装芯片结合方式通过连接构件124安装在封装基底110上，连接构件124在有源表面(图1中的“120”的下表面或面向封装基底的表面)上的连接电极上。覆盖连接构件124的包括环氧树脂等的底部填充树脂125可以在第一半导体芯片120的有源表面与封装基底110的上表面之间。
在实施方式中，第一半导体芯片120可以以引线结合方式安装到封装基底110上。
第一半导体芯片120可以包括例如系统大规模集成电路(LSI)、逻辑电路、CMOS成像传感器(CIS)等。
至少一个第二半导体芯片130a和130b(在下文中，至少一个第二半导体芯片130a和130b可以被称为“第二半导体芯片130a和130b”)可以在第一半导体芯片120的上表面的一部分上(例如，在第一半导体芯片120的背离封装基底110的表面上)。例如，第二半导体芯片130a和130b可以在第一半导体芯片120上并且可以暴露第一半导体芯片120的至少一部分。例如，当从上方观看或在平面图中观看(例如，如在图2中观看)时，至少一个第二半导体芯片130a和130b可以在第一半导体芯片120上并且可以覆盖第一半导体芯片120的上表面的一部分。至少一个第二半导体芯片130a和130b可以与第一半导体芯片120部分地叠置。
例如，当从上方观看时，第二半导体芯片130a和130b可以在第一半导体芯片120的上表面上并排并且彼此间隔开，以暴露第一半导体芯片120的中心部分。散热构件150(下面更详细地描述)可以在第一半导体芯片120的暴露的中心部分上，以有效地向半导体封装件的外部散热(例如，在第一半导体芯片120中产生的热)。
在实施方式中，单个第二半导体芯片130a可以在第一半导体芯片120的一侧上(见图12)，或者多个第二半导体芯片130a和130b可以堆叠在第一半导体芯片120的一侧上(见图13和图15)。
在实施方式中，至少一个第二半导体芯片130a和130b可以通过结合引线134a和134b电连接到封装基底110。在实施方式中，第一半导体芯片120上的至少一个第二半导体芯片130a和130b可以通过第一半导体芯片120的上表面上的引线层或连接垫电连接到第一半导体芯片120。
至少一个第二半导体芯片130a和130b可以通过附着构件135a和135b附着到第一半导体芯片120。附着构件135a和135b可以包括具有改善的导热性的聚合物材料。在实施方式中，附着构件135a和135b可以是导热胶带、导热油脂、导热粘合剂等。
至少一个第二半导体芯片130a和130b可以包括例如存储器芯片，诸如，DRAM、SRAM、闪存、PRAM、ReRAM、FeRAM、MRAM、高带宽存储器(HBM)、混合存储器立方体(HMC)等。
上面描述的第一半导体芯片和第二半导体芯片的类型、数量、设置等是作为示例而提出的，并且可以根据需要而变化。
绝缘层140可以在第一半导体芯片120、第二半导体芯片130a和130b的表面上。绝缘层140可以共形地涂覆在封装基底110、底部填充树脂125、第一半导体芯片120、第二半导体芯片130a和130b的整个暴露表面上。例如，绝缘层140可以涂覆在封装基底110的上表面、底部填充树脂125的侧表面、第一半导体芯片120的上表面和侧表面的至少一部分(例如，其上没有设置第二半导体芯片130a和130b或者没有被第二半导体芯片130a和130b覆盖的表面)以及第二半导体芯片130a和130b的上表面和侧表面上。绝缘层140可以共形地涂覆在第一半导体芯片120以及第二半导体芯片130a和130b上，从而当散热构件150形成在第一半导体芯片120以及第二半导体芯片130a和130b上时帮助减小散热构件150与第一半导体芯片120以及第二半导体芯片130a和130b之间的短路的可能性和/或防止散热构件150与第一半导体芯片120以及第二半导体芯片130a和130b之间的短路。
绝缘层140可以包括具有良好导热性的绝缘材料。在实施方式中，绝缘层140可以包括例如二氧化硅(SiO2)、氧化铝(Al2O3)、氮化硼(BN)、氮化铝(AlN)、陶瓷涂覆金属球等。
散热构件150可以在绝缘层140上。在实施方式中，散热构件150可以在第一半导体芯片120的上表面的未被第二半导体芯片130a和130b覆盖的区域上，并且可以在第二半导体芯片130a和130b的上表面的区域上。例如，散热构件150可以具有在被第二半导体芯片130a和130b暴露的第一半导体芯片120上的第一区域151以及在第二半导体芯片130a和130b上的第二区域152。散热构件150可以在绝缘层140上，并且当从上方(例如，在平面图中)观看时，可以遍及其中第一半导体芯片120与第二半导体芯片130a和130b叠置的区域以及其中第一半导体芯片120与第二半导体芯片130a和130b不叠置的区域形成。
第一区域151可以直接在第一半导体芯片120上，以致力于帮助消散大量的热，例如，在第一半导体芯片120中产生的热。第二区域152可以直接在第二半导体芯片130a和130b上，以致力于帮助散热，例如，在第二半导体芯片130a和130b中产生的热以及从第一区域151传递的在第一半导体芯片120中产生的热。当从上方观看时(例如，当沿与封装基底110的上表面正交的方向观看时)，第一区域151的面积可以比第二区域152的面积大。可以通过显著地确保直接形成在具有比第二半导体芯片130a和130b相对大的散热量的第一半导体芯片120上的第一区域151的面积来改善散热性能。
在实施方式中，散热构件150的第一区域151和第二区域152可以一体地形成。例如，第一区域151和第二区域152中的每个的上表面可以设置在同一水平上(例如，距封装基底110的上表面距离相同或共面)。第一区域151可以与涂覆在第一半导体芯片120的上表面上的绝缘层140的至少一部分以及涂覆在第二半导体芯片130a和130b的侧表面上的绝缘层140的至少一部分接触。第二区域152可以与涂覆在第二半导体芯片130a和130b的上表面上的绝缘层140的至少一部分接触。
散热构件150可以包括例如金属(诸如，金(Au)、银(Ag)、铜(Cu)等)或导电材料(诸如，石墨、石墨烯等)。
模制构件160可以在封装基底110上，并且可以覆盖第一半导体芯片120、第二半导体芯片130a和130b、封装基底110的上表面以及散热构件150的侧表面，并且可以暴露散热构件150的上表面的至少一部分。例如，模制构件160可以覆盖散热构件150的侧表面，并且可以暴露散热构件150的上表面。例如，模制构件160可以不完全覆盖散热构件150，使得散热构件150的上表面可以被暴露(例如，散热构件150的上表面可以在半导体封装件100A中面向外)。例如，散热构件150的上表面可以与模制构件160的上表面在同一水平上(例如，这些上表面可以距封装基底110距离相同或者可以共面)。模制构件160可以包括绝缘材料。在实施方式中，模制构件160的绝缘材料可以包括例如环氧模塑料(EMC)等。
加强构件170可以在散热构件150和模制构件160上，并且可以具有比散热构件150和模制构件160中的每个的弹性模量和热膨胀系数(CTE)大的弹性模量和CTE。加强构件170可以与散热构件150的上表面直接接触以帮助防止散热构件150的上表面中的裂纹。在实施方式中，散热构件150可以是具有例如约5ppm/℃至约40ppm/℃的CTE和约10GPa至约20GPa的弹性模量的导电材料，并且模制构件160可以是具有例如约5ppm/℃至约40ppm/℃的CTE和约20GPa至约35GPa的弹性模量的绝缘材料。
加强构件170可以具有比散热构件150和模制构件160中的每个的弹性模量大的弹性模量，以帮助分散施加到散热构件150的应力。此外，加强构件170可以具有比散热构件150和模制构件160中的每个的CTE大的CTE，以帮助抵消或补偿由模制构件160与散热构件150之间的CTE的差异引起的翘曲应力。
加强构件170可以具有例如在约5μm至约40μm或约10μm至约30μm的范围内的厚度。加强构件170可以包括具有例如约50ppm/℃或更大的CTE和约35GPa或更大的弹性模量的聚合物化合物。在实施方式中，加强构件170可以包括具有例如约100ppm/℃或更大的CTE和约56GPa或更大的弹性模量的聚合物化合物。在实施方式中，加强构件170可以在散热构件150上方(例如，在半导体封装件100A的外侧上或朝向半导体封装件100A的外侧)，并且加强构件170可以具有例如约3W/MK或更大的热导率以帮助保持或促进散热性能。
如上所述，根据示例实施例的半导体封装件100A可以包括散热构件150(具有在第一半导体芯片120上的第一区域151以及在第二半导体芯片130a和130b上的第二区域152)和覆盖散热构件150的加强构件170。
散热构件150的第一区域151可以在第一半导体芯片120上，并且散热构件150的上表面可以被暴露(例如，通过模制构件160暴露，使得散热构件150的上表面在半导体封装件100A中面向外)，使得在具有相对高散热量的第一半导体芯片120中产生的热可以通过散热构件150的第一区域151有效地消散。
如果散热构件150的上表面被完全暴露，则上表面会容易由于外部冲击而破裂或翘曲。在实施方式中，加强构件170可以覆盖散热构件150的(例如，暴露的)上表面，从而减小散热构件150的变形或对散热构件150的损坏的可能性或者防止散热构件150的变形或对散热构件150的损坏。
图3至图8示出了制造图1中的半导体封装件的方法中的各阶段的侧面剖视图。
参照图3，可以在封装基底110的上表面上安装第一半导体芯片120。封装基底110可以包括印刷电路板(PCB)、陶瓷基底等。
可以在封装基底110上以倒装芯片结合方式安装第一半导体芯片120。第一半导体芯片120可以通过连接构件124电连接到封装基底110。连接构件124可以是焊球，并且可以连接到封装基底110的上表面上的垫。
可以在第一半导体芯片120与封装基底110之间形成或设置底部填充树脂125(用于包封和支撑连接构件124)。
参照图4，第二半导体芯片130a和130b可以在第一半导体芯片120的上表面上彼此间隔开，例如，可以暴露第一半导体芯片120的中心部分。当从上方观看时，第二半导体芯片130a和130b可以与第一半导体芯片120部分地叠置。
第二半导体芯片130a和130b可以通过附着构件135a和135b附着到第一半导体芯片120。附着构件135a和135b可以包括具有良好导热性的聚合物材料。
可以将第二半导体芯片130a和130b以引线结合方式电连接到封装基底110。可以通过结合引线134a和134b将第二半导体芯片130a和130b连接到封装基底110上的垫。
参照图5，可以在封装基底110、底部填充树脂125、第一半导体芯片120以及第二半导体芯片130a和130b上形成绝缘层140。在实施方式中，可以通过例如喷涂工艺在封装基底110、底部填充树脂125、第一半导体芯片120以及第二半导体芯片130a和130b的整个暴露表面上共形地涂覆绝缘层140。
例如，可以在封装基底110的上表面、底部填充树脂125的侧表面、第一半导体芯片120的上表面和侧表面的至少一部分(其上没有设置第二半导体芯片130a和130b)以及第二半导体芯片130a和130b的上表面和侧表面上形成具有均匀厚度的绝缘层140。
绝缘层140可以包括例如具有良好导热性的二氧化硅(SiO2)、氧化铝(Al2O3)、氮化硼(BN)、氮化铝(AlN)、陶瓷涂覆金属球等。
参照图6，可以在涂覆在第一半导体芯片120上的绝缘层140和涂覆在第二半导体芯片130a和130b上的绝缘层140上形成散热构件150。
散热构件150可以具有第一区域151(位于涂覆在第一半导体芯片120上的绝缘层140上)和第二区域152(位于涂覆在第二半导体芯片130a和130b上的绝缘层140上)。
可以通过例如滴涂工艺、丝网印刷工艺等形成散热构件150。例如，可以通过在涂覆在第一半导体芯片120上的绝缘层140以及涂覆在第二半导体芯片130a和130b上的绝缘层140上连续地或重复地(两次或更多次)滴涂金属膏来形成第一区域151和第二区域152。例如，第一区域151和第二区域152可以一体地形成。
散热构件150可以包括具有良好导热性的金属材料。可以在涂覆在第一半导体芯片120以及第二半导体芯片130a和130b上的绝缘层140上形成散热构件150，并且可以防止与第一半导体芯片120以及第二半导体芯片130a和130b的短路。
参照图7，可以在封装基底110上形成模制构件160。模制构件160可以包封散热构件150的侧表面，并且可以暴露散热构件150的上表面的至少一部分。
例如，在施加模制构件160以覆盖散热构件150的上表面之后，可以研磨或另外去除模制构件160的上部，以暴露散热构件150的第一区域151和第二区域152中的每个的上表面。例如，散热构件150的第一区域151和第二区域152中的每个的上表面可以与模制构件160的上表面处于同一水平(例如，这些表面可以是共面的)。
参照图8，可以在散热构件150的第一区域151和第二区域152中的每个的上表面以及模制构件160的上表面上形成加强构件170。可以使用例如喷涂工艺、物理气相沉积(PVD)工艺、化学气相沉积(CVD)工艺等形成加强构件170。加强构件170可以形成为具有例如约5μm至约40μm的厚度。
加强构件170可以包括具有比散热构件150和模制构件160的弹性模量和CTE高的弹性模量和CTE的聚合物化合物。
最后，可以在封装基底110下方形成连接端子114。连接端子114可以连接到封装基底110的下表面上的垫。连接端子114可以是焊球。
图9示出了示出根据图1中的半导体封装件中的加强构件的物理性质(CTE和弹性模量)施加到散热构件的应力的曲线图。
图10A示出了示出当在半导体封装件中不存在加强构件时在散热构件中出现的裂纹的剖视图。图10B和图10C示出了通过具有高热膨胀系数的加强构件来释放施加到半导体封装件的应力的原理的剖视图。在图9中，CTE的单位是ppm/℃，弹性模量的单位是GPa。
参照图9，可以确认的是，随着加强构件170的CTE和弹性模量增大，施加到散热构件150的应力减小。将理解的是，加强构件170具有比散热构件150和模制构件160中的每个的弹性模量大的弹性模量，以分散施加到散热构件150的应力，并且加强构件170具有比散热构件150和模制构件160中的每个的CTE大的CTE，以抵消由封装基底110与模制构件160和散热构件150之间的CTE的差异引起的翘曲应力。例如，在约50ppm/℃或更大的CTE和约35GPa或更大的弹性模量下，施加到散热构件150的应力的相对值可以被减小到2.0或更小。
参照图10A，当模制构件160暴露散热构件150的上表面以确保散热路径时，由于外部冲击或热循环测试，在散热构件150的上表面中可能出现裂纹(由“A”表示)。这样的现象可以主要发生在散热构件150的第一区域151和第二区域152之间的边界处或附近。
参照图10B，在图10A中出现的裂纹可能是由半导体封装件下方的封装基底L与封装基底L上方的包括半导体芯片、模制构件、散热构件等的中间层M之间的CTE的差异引起的。在附图中，封装基底L和中间层M的CTE的大小(热变形的程度)由虚线箭头表示(见图10B中的上图)。封装基底L的CTE可能比中间层M的CTE大，并且封装基底L的收缩可以相对大，并且在执行热循环测试之后可以如实线箭头所示产生翘曲应力(见图10B中的下图)。
参照图10C，在示例实施例中，加强构件T可以在中间层M上。加强构件T的CTE可以比中间层M的CTE大(见图10C中的上图)。在这种情况下，由封装基底L的相对侧上的加强构件T的收缩产生的翘曲应力和在封装基底L中产生的翘曲应力可以彼此抵消(见图10C中的下图)。例如，施加到中间层M的应力可以被释放，以改善半导体封装件的翘曲特性。
图11示出了根据示例实施例的半导体封装件100B的侧面剖视图。
参照图11，在根据示例实施例的半导体封装件100B中，绝缘层140可以涂覆在结合引线134a和134b的表面上，并且散热构件150可以覆盖结合引线134a和134b。
当在例如喷涂工艺中将绝缘材料涂覆到封装基底110、第一半导体芯片120、第二半导体芯片130a和130b的整个暴露表面时，绝缘层140可以涂覆在结合引线134a和134b的表面上。
因此，即使当散热构件150的第二区域152形成为覆盖结合引线134a和134b时，结合引线134a和134b与散热构件150也可以通过绝缘层140电绝缘。
例如，当从上方观看时，第二半导体芯片130a和130b上的散热构件150的第二区域152可以覆盖第二半导体芯片130a和130b的上表面的大部分。第二区域152可以延伸到其中设置有结合引线134a和134b的区域，以覆盖涂覆有绝缘层140的结合引线134a和134b的表面的部分。
结果，可以增大其中形成有散热构件150的区域的面积，以进一步改善散热性能。除非另有具体描述，否则本实施例的组件的描述可以参考图1中示出的半导体封装件100A的相同或相似组件的描述。
图12示出了根据示例实施例的半导体封装件100C的侧面剖视图。
参照图12，根据示例实施例的半导体封装件100C可以包括在第一半导体芯片120的一侧上的单个第二半导体芯片130a。当从上方观看时，第二半导体芯片130a可以与第一半导体芯片120的一部分叠置，使得第一半导体芯片120的上表面的一部分被暴露。
散热构件150的第二区域152可以形成在第一半导体芯片120和第二半导体芯片130a彼此叠置的区域中，散热构件150的第一区域151可以形成在第一半导体芯片120和第二半导体芯片130a彼此不叠置的区域中。除非另有具体描述，否则本实施例的组件的描述可以参考图1中示出的半导体封装件100A的相同或相似组件的描述。
图13示出了根据示例实施例的半导体封装件100D的侧面剖视图，图14示出了图13中的半导体封装件的局部构造的平面图。图13示出了沿着图14中的局部构造的线II-II'截取的剖视图。
参照图13和图14，根据示例实施例的半导体封装件100D可以包括堆叠在第一半导体芯片120的一侧上(例如，以偏移或未对齐的布置堆叠在第一半导体芯片120的一侧上)的多个第二半导体芯片130a和130b。多个第二半导体芯片130a和130b可以分别通过使用附着构件135a和135b堆叠在第一半导体芯片120上。当从上方观看时，第一半导体芯片120的暴露面积(当多个第二半导体芯片130a和130b堆叠时)可以增大到比当多个第二半导体芯片130a和130b在横向方向上并排时第一半导体芯片120的暴露面积大。
当从上方观看时，多个第二半导体芯片130a和130b可以交替地布置以暴露每个连接垫(见图14)。多个第二半导体芯片130a和130b可以通过结合引线134a和134b电连接到封装基底110。
散热构件150的第一区域151可以在第一半导体芯片120的上表面上的绝缘层140上，散热构件150的第二区域152可以在多个第二半导体芯片130a和130b之中的上面堆叠的第二半导体芯片130b的上表面上的绝缘层140上。例如，当绝缘层140涂覆在结合引线134a和134b的表面上时，散热构件150的第二区域152也可以形成在下述绝缘层140上：该绝缘层140形成在多个第二半导体芯片130a和130b之中的下面堆叠的第二半导体芯片130a的上表面上。除非另有具体描述，否则本实施例的组件的描述可以参考图1中示出的半导体封装件100A的相同或相似组件的描述。
图15示出了根据示例实施例的半导体封装件100E的侧面剖视图。
参照图15，根据示例实施例的半导体封装件100E可以包括堆叠在第一半导体芯片120的一侧上以彼此叠置(例如，使得第二半导体芯片130a和130b的边缘对齐)的多个第二半导体芯片130a和130b。多个第二半导体芯片130a和130b可以分别通过附着构件135a和135b堆叠在第一半导体芯片120上。
当从上方观看时，多个第二半导体芯片130a和130b可以彼此叠置。例如，第一半导体芯片120的暴露在平面上的面积可以大于当多个第二半导体芯片130a和130b交替设置(例如，未对齐或偏移)时第一半导体芯片120的暴露在平面上的面积。多个第二半导体芯片130a和130b可以通过结合引线134a和134b电连接到封装基底110。
散热构件150的第一区域151可以在第一半导体芯片120的上表面上的绝缘层140上。散热构件150的第二区域152可以在多个第二半导体芯片130a和130b之中的上面堆叠的第二半导体芯片130b的上表面上的绝缘层140上。除非另有具体描述，否则本实施例的组件的描述可以参考图1中示出的半导体封装件100A的相同或相似组件的描述。此外，在上述各种实施例之中，两个或更多个实施例可以彼此组合，只要没有技术限制即可。
图16示出了根据示例实施例的半导体封装件100F的侧面剖视图。
参照图16，至少一个第二半导体芯片130a和130b可以包括高带宽存储器(HBM)。至少一个第二半导体芯片130a和130b可以包括顺序堆叠的缓冲器裸片131a以及多个存储器裸片131b和131c。在实施方式中，如附图中所示，可以堆叠两个存储器裸片131b和131c，或者可以堆叠更多数量的存储器裸片。缓冲器裸片131a与多个存储器裸片131b和131c可以通过硅通孔(TSV)132v彼此电连接。缓冲器裸片131a与多个存储器裸片131b和131c可以通过TSV 132v传送数据信号和控制信号。缓冲器裸片131a可以通过多个连接端子134电连接到第一半导体芯片120。
例如，当从上方观看时，多个第二半导体芯片130a和130b可以在第一半导体芯片120的上表面上并排并且彼此间隔开，使得第一半导体芯片120的中心部分和外部部分被暴露。在这种情况下，当从上方观看时，散热构件150的第一区域151可以位于涂覆在暴露的第一半导体芯片120的中心部分和外部部分上的绝缘层140上，散热构件150的第二区域152可以位于涂覆在多个第二半导体芯片130a和130b的上表面上的绝缘层140上。除非另有具体描述，否则本实施例的组件的描述可以参考图1中示出的半导体封装件100A的相同或相似组件的描述。此外，在上述各种实施例之中，两个或更多个实施例可以彼此组合，只要没有技术限制即可。
图17至图22示出了制造图16中的半导体封装件100F的方法中的各阶段的侧面剖视图。可以通过与参照图3至图8(分别对应于图17至图22)描述的制造半导体封装件100A的方法相同或相似的方法来制造半导体封装件100F。在下文中，将给出描述以集中于图17至图22中制造半导体封装件100F的方法与图3至图9中制造半导体封装件100A的方法之间的差异。
参照图17，类似于图3中描述的工艺，可以在封装基底110上安装第一半导体芯片120。
参照图18，当从上方观看时，包括高带宽存储器(HBM)的多个第二半导体芯片130a和130b可以在第一半导体芯片120的上表面上并排设置并且彼此间隔开，使得第一半导体芯片120的中心部分和外部部分(例如，外边缘)被暴露。
多个第二半导体芯片130a和130b中的每个可以包括顺序堆叠的缓冲器裸片131a以及多个存储器裸片131b和131c。缓冲器裸片131a与多个存储器裸片131b和131c可以通过硅通孔(TSV)132v彼此电连接。缓冲器裸片131a可以通过多个连接端子电连接到第一半导体芯片120。
参照图19，可以在封装基底110、第一半导体芯片120、底部填充树脂125以及多个第二半导体芯片130a和130b上形成绝缘层140。例如，可以通过喷涂工艺在封装基底110、第一半导体芯片120、底部填充树脂125以及第二半导体芯片130a和130b的整个暴露的表面上共形地涂覆构成绝缘层140的绝缘材料。
参照图20，可以在第一半导体芯片120以及多个第二半导体芯片130a和130b上形成具有第一区域151和第二区域152的散热构件150。第一区域151可以位于涂覆在第一半导体芯片120的其上没有设置多个第二半导体芯片130a和130b的中心部分和外部部分的上表面上的绝缘层140上，第二区域152可以位于涂覆在多个第二半导体芯片130a和130b的上表面上的绝缘层140上。
参照图21和图22，类似于图7和图8中描述的工艺，可以形成模制构件160，并且可以形成加强构件170和连接端子114。结果，可以制造出半导体封装件。
通过总结和回顾，在系统级封装件(SIP)中，散热路径会被嵌入有其中出现过度热量产生的半导体芯片(例如，逻辑芯片)的其他半导体芯片限制或阻挡。会难以将封装件中产生的热消散到封装件的外部。此外，由于多个半导体芯片与构成半导体芯片的其他材料之间的热膨胀系数(CTE)的差异，会出现翘曲或裂纹。
如上所述，根据示例实施例，加强构件可以被引入到散热构件的上部(例如，面向外的面)，以提供具有良好散热性能和良好翘曲特性的半导体封装件。
这里已经公开了示例实施例，虽然采用了特定术语，但是仅以一般的和描述性的含义来使用和解释它们，而不是出于限制的目的。在某些情况下，除非另外特别说明，否则如本领域普通技术人员将清楚的，自提交本申请之时起，结合具体实施例描述的特征、特性和/或元件可以单独使用，或者可以与结合其他实施例描述的特征、特性和/或元件组合起来使用。因此，本领域技术人员将理解的是，在不脱离本发明的由权利要求阐述的精神和范围的情况下，可以做出形式上和细节上的各种改变。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
封装基底；
第一半导体芯片，位于所述封装基底上；
至少一个第二半导体芯片，位于所述第一半导体芯片的上表面的区域上；
绝缘层，位于所述第一半导体芯片的表面和所述至少一个第二半导体芯片的表面上；
散热构件，位于所述绝缘层上，使得所述散热构件包括处于所述第一半导体芯片的上表面上的未设置所述至少一个第二半导体芯片的区域以及处于所述至少一个第二半导体芯片的上表面上的区域；
模制构件，位于所述封装基底上并且包封所述第一半导体芯片、所述至少一个第二半导体芯片和所述散热构件，使得所述模制构件暴露所述散热构件的上表面的至少一部分；以及
加强构件，位于所述散热构件和所述模制构件上。
2.根据权利要求1所述的半导体封装件，其中，所述加强构件的厚度为10μm至30μm。
3.根据权利要求1所述的半导体封装件，其中，所述加强构件：
包括聚合物化合物，并且
与所述散热构件的所述上表面直接接触。
4.根据权利要求3所述的半导体封装件，其中，所述散热构件的所述上表面与所述模制构件的上表面在同一水平上。
5.根据权利要求1所述的半导体封装件，其中，所述加强构件具有大于所述散热构件的热膨胀系数并且大于所述模制构件的热膨胀系数的热膨胀系数。
6.根据权利要求5所述的半导体封装件，其中：
所述散热构件和所述模制构件中的每个独立地具有5ppm/℃至40ppm/℃的热膨胀系数，并且
所述加强构件具有50ppm/℃或更大的热膨胀系数。
7.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
连接构件，位于所述第一半导体芯片的下表面上，以将所述第一半导体芯片电连接到所述封装基底；以及
底部填充树脂，覆盖所述第一半导体芯片的所述下表面和所述连接构件，
其中，所述绝缘层覆盖所述底部填充树脂的侧表面。
8.根据权利要求1所述的半导体封装件，其中，所述绝缘层在所述封装基底的上表面、所述第一半导体芯片的其上未设置所述至少一个第二半导体芯片的上表面和侧表面的至少一部分以及所述至少一个第二半导体芯片的上表面和侧表面上。
9.根据权利要求1所述的半导体封装件，其中，所述至少一个第二半导体芯片通过结合引线电连接到所述封装基底。
10.根据权利要求9所述的半导体封装件，其中，所述绝缘层位于所述结合引线的表面上。
11.根据权利要求10所述的半导体封装件，其中，所述散热构件覆盖所述结合引线的一部分。
12.根据权利要求1所述的半导体封装件，其中：
所述至少一个第二半导体芯片包括多个半导体芯片，并且
所述多个第二半导体芯片在所述第一半导体芯片的所述上表面上彼此间隔开，使得当从垂直于所述封装基底的上方观看时，所述多个第二半导体芯片与所述第一半导体芯片的中心部分不叠置。
13.根据权利要求1所述的半导体封装件，其中：
所述至少一个第二半导体芯片包括多个第二半导体芯片，并且
所述多个第二半导体芯片堆叠在所述第一半导体芯片的所述上表面的一部分上。
14.一种半导体封装件，所述半导体封装件包括：
封装基底；
第一半导体芯片，位于所述封装基底上；
散热构件，位于所述第一半导体芯片的上表面的一部分上；
模制构件，位于所述封装基底上并且覆盖所述封装基底的上表面、所述第一半导体芯片的一个侧表面和所述散热构件的一个侧表面，使得所述模制构件暴露所述散热构件的上表面的至少一部分；以及
加强构件，位于所述散热构件和所述模制构件上，
其中，所述加强构件包括聚合物化合物，并且具有大于所述散热构件的热膨胀系数且大于所述模制构件的热膨胀系数的热膨胀系数。
15.根据权利要求14所述的半导体封装件，所述半导体封装件还包括：
第二半导体芯片，位于所述第一半导体芯片的所述上表面上；
底部填充树脂，覆盖所述第一半导体芯片的下表面；以及
绝缘层，至少覆盖所述第一半导体芯片的所述上表面、所述第二半导体芯片的上表面和侧表面以及所述底部填充树脂的侧表面的区域，
其中，所述第二半导体芯片是存储器芯片。
16.一种半导体封装件，所述半导体封装件包括：
封装基底；
第一半导体芯片，位于所述封装基底上；
至少一个第二半导体芯片，位于所述第一半导体芯片上；
绝缘层，位于所述封装基底的表面、所述第一半导体芯片的表面和所述至少一个第二半导体芯片的表面上；
散热构件，位于所述绝缘层上，使得所述散热构件包括处于所述第一半导体芯片上的未与所述至少一个第二半导体芯片叠置的区域以及当从垂直于所述封装基底的上方观看时处于所述至少一个第二半导体芯片上的与所述第一半导体芯片叠置的区域；
模制构件，位于所述封装基底上并且包封所述第一半导体芯片、所述至少一个第二半导体芯片和所述散热构件中的每个的至少一部分；以及
加强构件，位于所述散热构件和所述模制构件上。
17.根据权利要求16所述的半导体封装件，其中：
所述散热构件和所述模制构件中的每个独立地具有5ppm/℃至40ppm/℃的热膨胀系数，并且
所述加强构件具有50ppm/℃或更大的热膨胀系数。
18.根据权利要求16所述的半导体封装件，其中，
所述散热构件具有10GPa至20GPa的弹性模量，
所述模制构件具有20GPa至35GPa的弹性模量，并且
所述加强构件具有35GPa或更大的弹性模量。
19.根据权利要求16所述的半导体封装件，其中，所述加强构件与所述散热构件的上表面直接物理接触。
20.一种半导体封装件，所述半导体封装件包括：
基底；
第一半导体芯片，位于所述基底上；
第二半导体芯片，位于所述第一半导体芯片上；
绝缘层，位于所述第一半导体芯片的表面和所述第二半导体芯片的表面上；
散热构件，位于所述绝缘层上；
模制构件，包封所述第一半导体芯片、所述第二半导体芯片和所述散热构件中的每个的至少一部分；以及
加强构件，位于所述散热构件和所述模制构件上，
其中：
所述散热构件和所述模制构件中的每个独立地具有5ppm/℃至40ppm/℃的热膨胀系数，并且
所述加强构件具有50ppm/℃或更大的热膨胀系数。
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