TW586165B - Self-aligned nanotube field effect transistor and method of fabricating same - Google Patents

Self-aligned nanotube field effect transistor and method of fabricating same Download PDF

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TW586165B
TW586165B TW092104050A TW92104050A TW586165B TW 586165 B TW586165 B TW 586165B TW 092104050 A TW092104050 A TW 092104050A TW 92104050 A TW92104050 A TW 92104050A TW 586165 B TW586165 B TW 586165B
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carbon nanotube
gate
metal
effect transistor
dielectric layer
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TW200304679A (en
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Joerg Appenzeller
Phaedon Avouris
Kevin K Chan
Philip G Collins
Richard Martel
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
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    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
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Description

586165
一、【發明所屬之技術領域】 本發明係有關於-種場效電晶體，特別有關於一種碳 奈米管場效電晶體。 二、【先前技術】 在分子奈米電子學（molecular nanoelectronics) 領域中，很少有材料像奈米管那麼有希望，特別是碳奈米 管，其包含有埃米等級直徑的石墨中空圓柱。奈米管可被 使用於電子元件中，如二極體及電晶體，視奈米管的電子 特性而定。奈米管具有特殊的尺寸、形狀以及物理特性。 結構上碳奈米管類似碳的六角形晶格滾入一圓柱中。 除了有趣的低溫下量子行為，碳奈米管具有至少兩項 重要特性：奈米管可以是金屬或是半導體的，依其對掌性 (chirality )而定（即構造幾何，conf〇rmati〇nai geometry)。金屬奈米管可以固定電阻率傳載極大電流。 半導體奈米管則可以電切換開或關，類似一場效電晶體 (field-effect transistor，FET)。這兩種奈米管可共價 連接（分享電子）。這些特性使得奈米管成為製作奈米等 級半導體電路之良好材料。 -此外，碳奈米管為——維電導體，意即僅有一維量子 ‘ 力學模式傳載電流。因為材料内之散射（scattering )被· 強烈壓抑，而使得使用碳奈米管之電晶體的元件效能具有
第5頁 586165
強大的優勢。元件具有較低之散射 代表具有較好之效
…對一個三端元件而言，例如場效電晶體，一閘極（第 二端）需要與主動通道區、源極以及汲極絕緣。因此需要 使用例如是二氧化矽等介電材料。要改善矽元件内之元件 特性介電層厚度可降低。而介電層厚度減少，使得閘極 電谷i曰加，且促進閘極對通道— channei)之耦 合。對標準矽場效應元件而言，閘極電容之大小與介電能 厚度成反比。現今製造的高效能處理器中，二氧化矽之厚 度低於4nm。重要的是，不易達到更低之厚度，因為當氧 化層厚度低於4nm時，閘極透過介電層之漏電流指數增 加0 ;、、、、而’對於一碳奈米管電晶體而言，閘極電容與介電 f厚度不呈反比關係。&而代之的是，碳奈米管依循-對 =關，。與-般標準之發場效電晶體相較，因為其圓柱狀 成何外形，碳奈米管電晶體之閘極電容可以更大。 未有已知系統或方法在一場效電晶體中使用奈米管以 Φ : 5表現與較小尺寸。因11匕，需要-製作-奈米管場效 電日日體的系統及方法。 三
發明内容
第6頁
ου 丄 CO
自對準碳奈米管場效 根據本發明之一實施例，提供_ 電晶體半導體元件。此元件包二 山 _ -基板。-源極形成於上述碳太：：一：示米管放置於 形成於上述碳奈米管之-第：：未官之H -沒極 上述碳奈米管之一部分上，」及-閘極實質形成於 述碳奈米管隔開。 、’"電層使上述閘極與上 上述基板包括一I之厚度約為150nm ‘ 热礼化層沉積於 帘丞敗上 以 此元件更包括一保護介電層於元件上。 此半導體元件更包括一對準記號於基板上，供源極以 上述閘極披覆於介電層以及碳奈米管，並與碳奈米管 之一背面接觸。 ” & 根據本發明之一實施例，提供一自對準碳奈米管場效 電aa體半導體元件。此元件包括以下。一垂直碳奈米管， 以一介電材料纏繞。一源極，形成於上述碳奈米管之一第 586165
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五、發明說明（5) 金屬接點係利用一光阻形成。 根據本發明之一實施例，提供一形成自對準碳奈米管 場效電晶體半導體元件的方法。此方法包括以下步驟。放 置一碳奈米管於一熱氧化物基板上，其中基板包括一對準 "己號。以反應式離子#刻（reactive ion etch)方式， ^碳奈米管之每一端形成一金屬接點，其中一第一金屬接 點係一源極，且一第二金屬接點係一汲極。形成一氮化間 ^壁於每一金屬接點之兩側。沉積具有高介電常數（high 之了介電層’於自對準碳奈米管場效電晶體半導體元件 上。以及形成一閘極，實質位於源極以及汲極之間，並於 碳奈米管上。 上述方法更包含一步驟：沉積一保護介電層於元件 場效ί f 5::之一實施例，提供-形成自對準碳奈米管 置-件的方法。此方法包括以下步驟。激 記號。在碳I米管：mi: 基板包括-對準 層使非晶矽柱絕緣。 : 虱化 間。形成-閉^實質位於間於ί晶：柱之― 上。形成-氮化層，於閘極上。於 ^二：奴奈米官 氧化間隙壁。以金屬接點取代非…第2屬 586165 五、發明說明（6) 以及沉積一 接點係一源極，且一第二金屬接點係一汲極。 保護介電層於元件上。 …根據本發明之另一實施例，提供一形成自對準碳 管場效電晶體半導體元件的方法’此方法包括以下？ 沉積-金屬催化劑於-熱氧化物基板。沉積一低 於元件上。姓刻形成一溝槽（trench)，溝槽通過氧化^ 以及金屬催化劑，並進入位於金屬催化劑下方之一埶氧化 層。蝕刻低溫氧化層以形成氧化物島。剝除 … (stripping )暴露之金屬催化劑。成長一奈米管，位於 該等氧化物島之下的該金屬催化劑之間。以一閘極介電層 包覆碳奈米管。形成氮化物間隙壁於氧化物島相對之表 面。以化學氣相沉積方式形成一閘極，實質位於氧化物島 之間，並位於奈米管上。以及沉積一保護介電層於元件 上。 根據本發明之一實施例，提供一形成自對準碳奈米管 場效電晶體半導體元件的方法，此方法包括以下步驟。成 長一奈米管垂直於該半導體元件之一表面所形成之一金屬 催化劑。形成一氮化物塊結構。以一閘極介電層包覆破奈 米管。沉積一閘極金屬’並以閘極介電層使閘極金屬與金 屬催化劑隔開。沉積一氮化層。形成閘極金屬柱，被氮化 層所覆蓋。形成氮化物間隙壁，包覆閘極金屬柱。沉積一 >及極金屬’實質位於閘極金屬柱之間，以介電層使汲極金
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586165 五、發明說明（8) 1 〇 9以形成金屬接點1 〇 6、1 〇 7之側的間隙壁11 〇。而非晶石夕 1 08可以選擇性方式移除或以濕式化學方法氧化之。一@問 極介電層111形成於元件上。這裡以及以下的方法中，介 電層可以是二氧化矽或是任何高介電常數之材料，例如： Hf〇2。閘極112可利用化學氣相沉積以及蝕刻法實質形成金 屬接點106、107、源極以及汲極之間。一保護介電層113 沉積於元件上。源極、汲極以及閘極皆自對準於 ^呓號 101。 〇
在另一實施例中，在形成閘極之前，源極以及汲極以 反應式離子蝕刻方法而成。請參閱第2a〜2b圖，形成源 極、汲極以及金屬接點1〇6、107之方法，首先利用反應式 離子钱刻方式定義源極以及汲極之金屬。其中，反應式離 子餘刻需絕緣於碳奈米管104。一氮化層2〇ι沉積於^牛 上，並自金屬接點周圍區域蝕刻之。氮化物間隙壁2〇2形 成於金屬接點之側邊。一閘極介電層2 〇 3沉積於元件上。 閘極金屬204實質形成於源極以及閘極1〇6、1〇7之門。一 保護介電層205可沉積於元件上。熱氧化層厚度約。
、，根據本發明之另一實施例，閘極可形成於源極/汲極 之丽。非晶矽301可沉積於碳奈米管1〇4之兩端。此非晶矽 可以一氧化物層302覆蓋。一閘極介電層3〇3沉積於非晶矽 層，例如301，之間。一閘極304實質形成於此非晶矽柱 301之間。一氮化層3 0 5形成覆蓋閘極3〇4。氧化物間隙壁
586165 五、發明說明（9) 306形成於閘極304金屬之兩端。而暴露出之非晶石夕/ 物之角^，可以被剝除以露出非晶石卜餘下之非晶秒乳化费 閘極金屬，可以反應式離子㈣方式移除之。金屬接^ 307、308與奈米管1〇4連接，奈米管1〇4部分位於閘極3〇4 以及閘極介電層3 03下方。金屬接點3〇7、3〇8形成此半 體兀，之源極以及汲極。金屬接點3〇7、3〇8可以對準沉 於熱氧化層102以及矽基板103内之對準記號1〇1。最貝 保護介電層3 0 9於此元件上。 、，根據本發明之一實施例，一碳奈米管場效電晶體可於 適當處成長。其中源極/汲極形成於閘極之前，一非晶石夕 層401/儿積於一熱氧化層1Q2上。一低溫氧化層jog (lt〇) 可沉積於金屬催化劑上。蝕刻低溫氧化層4〇2、非晶矽層 4〇1以及熱氧化層1〇2以形成一溝槽。則部分位於氧化層 402下方之非晶石夕層4〇1被底切（un(jer cut)。一金屬催 化劑40 1B則進入非晶矽4〇1被底切之邊緣，其中，金屬催 化劑可以為Fe、Co、Ni或是Fe/Mo。一碳奈米管403可成長 於金屬催化劑40 1B之間，其中一部分奈米管懸吊於熱氧化 層1 02上。一閘極介電層4〇4以化學氣相沉積方式沉積並包 覆奈米管403。因此奈米管403可完全以閘極介電層覆蓋。 間隙壁405可形成於氧化層402之側邊。一閘極40 6可實質 形成於氧化層402之間。若是熱氧化層102被蝕刻的夠深， 則閘極金屬406可包覆整個碳奈米管403以及介電層404。 為達到此目的’閘極金屬可以化學氣相沉積之方式，以覆
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蓋奈米管/介電層堆疊之背面。此一包覆方式，提供較佳 之閘極與奈米管之耦合。一保護介電層4〇6沉積於表 面上。 、根據本發明之另一實施例，一碳奈米管於適當處垂直 成長。成長一奈米管垂直於例如於基部的一金屬源極戍一 金屬催化劑。請參閱第5a〜5n圖，一金屬催化劑5〇1形1於 矽基板502上。一氮化物503之第一層沉積於半導體元件 上。在氮化物503上沉積一氧化層504，再在氧化層5〇4上 >儿積第二層氮化物5 0 5。一光阻5 0 6以一般微影製程形成於 此半導體元件，且曝露出金屬催化劑5 〇 1之部分。將複數 個第二金屬催化劑5 0 7沉積於此元件上。再將光阻5 〇 6剝 離，使得第二金屬催化劑507僅存在於第一金屬催化劑5〇1 上。而在每一第二金屬催化劑5〇7上，垂直地成長一奈米 管5 0 8，如此形成奈米管的二維以及三維陣列。 當分子金屬催化劑設置對準於基板上之細孔 (pore ) ’則碳奈米管垂直於基板成長。在此情形下，成 長空間被偈限，並使奈米管之成長僅在垂直方向。原則 上，垂直之細孔，如第5b圖所示，可利用光阻及圖案轉移 製作。 一非晶矽層5 0 9形成覆蓋元件。元件可被平坦化至與 氮化層5 0 5齊。再移除部分之氮化物—氧化物-氮化物層5 0 3
第14頁 586165 五、發明說明（11) -- 〜505。奈米管5〇8周圍以及金屬催化劑5〇ι、5〇7周圍留下 ，狀物（Pillar )。一犧牲層51〇覆蓋氮化物5〇5、碳夺 官508以及非晶州9。接觸層可以為η或是w。移除氮化、 ”03以及505間之氧化物5〇4。接著非晶矽5〇9同時自 = 5 08周圍被移除。非晶㈣9亦可以在移除氧化物之、 後被移除。一閘極介電層5n ,形成於奈米管5〇8周圍 於犧牲層51〇下，金屬催化劑51()上。若為二維奈米管陣位· 列，閘極介電層511可形成於碳奈米管間。犧牲層51〇可 Π方5移除。接著沉積於元件表面上。沉積第三氮化層 13於閘極金屬512上。接著移除部份氮化物513以及閘^
512，而形成柱狀之氮化物513以及閘極512仍包覆前述 I 屬催化劑-奈米管結構。氮化物間隙壁514形成於柱狀两 圍。汲極接點5 1 5形成於金屬催化劑_奈米管結構上，形二 一場效電晶體。沉積一保護介電層516於各個場效電晶體 之間。 、必須注意的是，自金屬催化劑成長奈米管之確實機 並不被知道。不過此一金屬催化劑成長單壁奈米管之過， 程，例如鈷於氧化鋁支撐之鉬顆粒上（c〇baU Mer之 alumina-supported Molybdenum particles)，可採用不 根據本發明之另一實施例，可採用應用組裝之 而非如前所述放置或成長的方式來擺放奈米管。應 方 用 式， 組裝
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可用於垂直或是水平之奈米管放置，此放置係利用化學或 物f方式驅動之選擇性設置。此一選擇性放置包括形成一 黏著層或是化學基團（chemical gr〇ups)作為接收體， 用以幫助奈米管放置在所需之位置上。第6a〜6b圖分別顯 示水平以及垂直應用組裝之方法。其中，一奈米管6〇1兩 端包括預設之化學基團602，例如DNA股（strand )或是醇 類。奈米管601被帶到靠近具有接收體6〇4之基板6〇3，若 用DNA，則使用互補之DNA股。而若用醇類，則金粒或包含 金的接點可用以作為鏈結具有此類化學基團6 〇 2之奈米管 601。而奈米管601可以此組裝方式設置於基板6〇3内。 效能較佳之高介電常數介電層可作為閘極之絕緣層。 了碳奈米管場效電晶體之電容不會隨介電層厚度產生巨 變化，因此較難達到所需之電容，甚至是較薄之閘極介 層。Abo〆介電常數k = 9)以及Hf〇2(介電常數k = 2〇)在此背旦 之下，則有希望可以作為介電層用。化學氣相沉積銘，‘ 氧化以形成高介電常數之閘極介電層，或是直接沉積八 (則2亦可以直接沉積）。與二氧切相較，使用上述材^ 約可增加五倍之問極電$，且對半導體元件之效能比減少 介電層厚度具有較大之影響效果。纟於奈米管在—空 境下為PFET，而在真空下通入氬氣並經過退火後，會轉變 為nFET，0此在介電層沉積前，可對此半導體元件進 火，使^奈米管轉變為nFET。在原處Un以汕）以一介 電層加蓋此一半導體元件’以防止奈米管再次轉換為
586165 五、發明說明（13) pFET。對^互補技術而言，應轉為矸^的場效電晶體上的 介電層可被移除，且仍可摻雜此些場效電晶體。再在低溫 下利用-化學氣相沉積塗佈此些元件，不需額外之退 驟0 適结Λ，或是nm)皆以氧化層 適田之"電層）覆盍’目此在閘極電極製造時，並不 ΠΪ之沉積可使用化學氣相沉積。如第4以及第5 學氣相沉積法進行此-製程可確定介電層 :王二；官丄同時閘極金屬亦完全包覆介電層，而形 Ϊ: Π 管輕合之條件。閘極金屬可以在所需 可以開放（。pen)以供電接觸。疋移除而源極和汲極 雖然本發明已以一較佳青祐 以限定本發明，任何熟習此技藝j揭：並非用 二圍；當可作些許之更動與潤飾，因此本發 乾圍s視後附之申請專利範圍所界定者為準。 ’、凌 586165 圖式簡單說明 五、【圖式簡單說明】 第1 a〜1 i圖顯示本發明一實施例之一源/閘極第一碳奈米管 場效電晶體， 第2 a〜2 b圖顯示本發明另一實施例之一源/閘第一碳奈米管 場效電晶體； 第3 a〜3 g圖顯示本發明一實施例之一閘極第一碳奈米管場 效電晶體； 第4 a〜4 d圖顯示本發明一實施例之一碳奈米管場效電晶體 包含適當地方成長之一奈米管； 第5 a〜5 η圖顯示本發明一實施例之一碳奈米管場效電晶體 包含適當地方垂直成長之一奈米管；以及 第6 a〜b圖顯示本發明一實施例奈米管之應用組裝。 元件符號說明 1 (Π〜對準記號； 1 0 2〜熱氧化層； 103、 502、603〜石夕基板； 104、 403、508、601〜奈米管； 105、 506〜光阻； 106、 107、307、308、515〜接點； 108、 301、401、50 9〜非晶石夕層； 109、 201、30 5、503、50 5、513〜氮化層； 110、 2 0 2、30 6、40 5、514〜間隙壁； 111 、113 、203 、205 、303 、309 、404 、 511、 516〜介電
第18頁 586165 圖式簡單說明 層； 1 1 2、2 0 4、3 0 4、4 0 6、5 1 2 〜問極； · 3 0 2、4 0 2、5 0 4〜氧化物層； ， 4 0 1 B、5 0 1、5 0 7〜金屬催化劑； 5 1 0〜犧牲層； 6 0 2〜化學基團； ， 604〜接收體。
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Claims (1)

  1. 586165 六、申請專利範圍 1. 一種自對準碳奈米管場效電晶體半導體元件，包括： 一碳奈米管放置（deposited)於一基板； 一源極形成於該碳奈米管之一第一端； 一汲極形成於該碳奈米管之一第二端；以及 一閘極實質形成於該碳奈米管之一部分上，並以一介 電層使該閘極與該碳奈米管隔開。
    2. 如申請專利範圍第1項所述之自對準碳奈米管場效電晶 體半導體元件，其中該基板包括一熱氧化層沉積於一矽基 板。 3. 如申請專利範圍第2項所述之自對準碳奈米管場效電晶 體半導體元件，其中該熱氧化層之厚度約為150 nm。 4. 如申請專利範圍第1項所述之自對準碳奈米管場效電晶 體半導體元件，其中一部分之該閘極更以一氧化層與該碳 奈米管隔開。
    5. 如申請專利範圍第1項所述之自對準碳奈米管場效電晶 體半導體元件，其中該閘極以一氮化物間隙壁 (spacer )，與該源極和沒極隔開。 6.如申請專利範圍第1項所述之自對準碳奈米管場效電晶 體半導體元件，更包括一保護介電層（passivation
    第20頁 586165 六、申請專利範圍 dielectric layer)覆蓋該元件。 7 ·如申請專利範圍第1項所述之自對準碳奈米管場效電晶 體半導體元件，更包括一對準記號於該基板上，供該源極 以及該汲極對準。 8 ·如申請專利範圍第1項所述之自對準碳奈米管場效電晶 體半導體元件，其中該閘極披覆於（wraps around )該介 電層以及該碳奈米管，以與該碳奈米管之一背面接觸。 9. 一種碳奈米管場效電晶體半導體元件，包括： 一垂直碳奈米管，以一介電材料纏繞（wrap ); 一源極，形成於該碳奈米管之一第一端； 一汲極，形成於該碳奈米管之一第二端； 一雙層氮化物複合體（bilayer nitride complex )，供形成該源極以及該汲極各自之一捆帶 (band strap)，並使該源極以及該汲極與該介電材料纏 繞之該碳奈米管連接；以及 一閘極’實質形成於該碳奈米管之一部分上。 1 0 ·如申請專利範圍第9項所述之碳奈米管場效電晶體半導 體元件’其更包括—金屬催化劑於該碳奈米管之一基部 (base ) °
    586165 六、申請專利範圍 11·、種形成一自對準碳奈米管場效電晶體半導體元件的 方法，包括下列步驟： 放置一奈米管於一熱氧化物基板上，其中該基板包括 一對準記號； 於该奈米官之每一端形成一金屬接點，其中一第一金 屬接點係一源極，且一第二金屬接點係一汲極； 沉積一非晶矽層於該元件上； 形成一氮化間隙壁，於每一該等金屬接點之兩側 (oppos i ng sides); 沉積具有高介電常數（high k)之一介電層於該元件 上； 氧化该非晶秒層；以及 形成一閘極，實質上位於該源極以及該汲極之間，並 位於該奈米管上。 1 2·如申請專利範圍第11項所述之方法，其更包含一步 驟··沉積一保護介電層於該元件上。 1 3 ·如申請專利範圍第丨丨項所述之方法，其中該奈米管係 一單壁（single-waiied)奈米管。 1 4 ·如申請專利範圍第丨丨項所述之方法，其中該等金屬接 點係利用一光阻形成。
    第22頁 586165 六、申請專利範圍 1 5 · —種形成一自對準碳奈米管場效電晶體半導體元件的 方法，包括下列步驟： 散I 奈米管於一熱氧化物基板上，其中該基板包括 一對準記號； 以反應式離子餘刻（reactive i〇n etch)方式，於 ΰ玄示米’之母一端形成一金屬接點，其中一第一金屬接點 係一源極，且一第二金屬接點係一汲極； 形成一氮化間隙壁於每一該等金屬接點之兩側； >冗積具有高介電常數之一介電層於該元件上；以及
    形成一閘極，實質位於該源極以及該汲極之間，且位 於該奈米管上。 16.如申請專利範圍第15項所述之方法，其更包含一步 驟：沉積一保護介電層於該元件上。 1 7 · —種形成一自對準碳奈米管場效電晶體半導體元件的 方法，包括下列步驟： 放置一奈米管於一熱氧化物基板上，其中該基板包括 一對準記號； 在邊奈米管之每一端上，形成一非晶矽柱 (amorphous silicon pillar ) \ 以一氧化層使該等非晶矽柱絕緣（丨s〇丨at i叫）； 形成一閘極介電層於該等非晶矽柱之間； 升/成閘極貝貝位於该專非晶石夕柱之間，且位於該
    第23頁 586165 六、申請專利範圍 奈米管上； 形成一氮化層於該閘極上； 於该閘極之每一邊，形成一氧化間隙壁； 以i屬接點取代該等非晶矽柱，其中一第一金屬接點 係一源極，且一第二金屬接點係一汲極；以及 沉積一保護介電層於該元件上。 18· —種形成一自對準碳奈米管場效電晶體半導體元件的 . 方法，包括下列步驟： 沉積一金屬催化劑於一熱氧化物基板上； · 沉積一低溫氧化層於該元件上； I虫刻形成一溝槽，該溝槽通過該氧化層以及該金屬催 化劑，並進入位於該金屬催化劑下方之一熱氧化層； 蝕刻該低溫氧化層以形成氧化物島； 剝除暴露之該金屬催化劑； 成長一奈米管，位於該等氧化物島之下的該金屬催化 劑之間； 以一閘極介電層包覆該奈米管； 形成氮化物間隙壁於該等氧化物島相對之表面； 以化學氣相沉積方式形成一閘極，實質位於該等氧化 | 物島之間，並位於該奈米管上；以及 沉積一保護介電層於該元件上。 . 1 9 · 一種形成一自對準碳奈米管場效電晶體半導體元件的
    586165 六、申請專利範圍 方法，包括下列步驟： 成長一奈米管垂直於該半導體元件之一表面所形成之 一金屬催化劑； 形成一氮化物塊結構（n i t r i d e b 1 〇 c k structure ); 以一閘極介電層包覆該奈米管； 沉積一閘極金屬，並以該閘極介電層使該閘極金屬與 該金屬催化劑隔開； 沉積一氮化層； 形成閘極金屬柱，被該氮化層所覆蓋； 形成氮化物間隙壁於該柱周圍； 沉積一汲極金屬，實質位於該柱之間，以該介電層使 該汲極金屬與該閘極金屬分開；以及 沉積一保護介電層於該元件上。
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