TW567601B - Module device of stacked semiconductor package and method for fabricating the same - Google Patents

Module device of stacked semiconductor package and method for fabricating the same Download PDF

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Publication number
TW567601B
TW567601B TW091124044A TW91124044A TW567601B TW 567601 B TW567601 B TW 567601B TW 091124044 A TW091124044 A TW 091124044A TW 91124044 A TW91124044 A TW 91124044A TW 567601 B TW567601 B TW 567601B
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Taiwan
Prior art keywords
circuit board
semiconductor
semiconductor package
conductive element
wafer
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TW091124044A
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English (en)
Inventor
Han-Ping Pu
Chih-Ming Huang
Chien Ping Huang
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Siliconware Precision Industries Co Ltd
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Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW091124044A priority Critical patent/TW567601B/zh
Priority to US10/319,262 priority patent/US6828665B2/en
Application granted granted Critical
Publication of TW567601B publication Critical patent/TW567601B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description

567601 五、發明說明（1) ---- 【發明領域】 本發明係關於一種模組化之半導體封裝件，尤指一種 以堆$方式結合有複數個半導體封裝件之模組化裝置。 【背景說明】 現今電子產品係朝多功能、高電性及高速運作之方向 發展’為配合此一發展方向，半導體業者莫不積極研發4 整合有複數個晶片之半導體裝置之多晶片模組（Multix b Chip Module, MCM)以符合電子產品之需求。 此種整合有複數個晶片之半導體裝置主要類型之一， 係在單一之半導體裝置中整合複數個晶片者，如第1 &及i b 圖所示之半導體裝置乃在一基板上承載多數個堆疊之半導 體曰曰片1 0 (如第1 a圖所示）’或於一基板2 0上佈設多數個置 於同 平面上之半導體晶片21 (如第1 b圖所示）。是種半導 體裝置之缺點在於其完成封裝後始能對各晶片進行電性及 信賴性等測試，若其中有任一晶片無法通過測試，將導致 整個半導體裝置即無法使用。 如第1 c圖所示，美國專利第6，3 0 3，9 9 7號揭露另一整 合有複數個晶片之半導體裝置類型，即在一基板3 0之上表 面安置有一電性連接至該基板3 0之半導體晶片3 1與另一半 導體封裝件3 2，該模組化之半導體裝置3製程時，係先將 該半導體晶片3 1藉由銲線3 1 1電性連接至該基板3 0上表面 並進行測試，俟確認功能正常後，再以表面藕接（S u r f a c e Mount Technology, SMT)方式將另一已完成封裝並經測試 之BGA半導體封裝件32藉銲球321電性連接至該基板30，最
16930.ptd 第7頁 567601 五、發明說明（2) 後再進行整體測試，以避免前述傳統之多晶片模組所存在 之良晶片（Known Good Die，KGD)的問題。然該半導體裝 置3必須在該基板3 0上表面同時設置多數之銲線墊與銲球 墊’俾供該半導體晶片3 1與封裝件32電性連接至該基板 3 0，不僅造成基板佈局限制，同時必須使用高密度之製 程，如積層基板（Build_Up substrate)，導致生產成本之 提昇。 美國專利第5, 78 3, 8 7 0號揭露另一整合有複數個晶片 之半導體裝置的類型，如第1 d圖所示，係將複數個半導體 封裝件整合為單一之模組化之半導體裝置（M〇dule
Semiconductor Device)者。該模組化半導體裝置4，係將 一第二半導體封裝件40b疊接於一第一半導體封裝件4〇a 上，以藉該第二半導體封裝件4〇b之多數銲球411瞵接至 該第一半導體封裝件41a之基板41a上表面，使該第二半導 體封裝件40b得電性連接至該第一半導體封裝件；同理， 第三半導體封裝件4〇c與第二半導體封裝件4〇b之疊接亦 然。其中該模組化之半導體裝置所使用之半導體封裝 個別予以進行所需之測試，俟測試通過後再加以疊接。盆 雖可利用一般基板即解決多晶片模組所存在之良晶片八 Unown Good Die’ KGD)的問題，然而，該種具複數個最 接半導體封裝件之裝置巾，位於下層之半導體封裝件二 板部分，僅在安置有半導體晶片之晶片接置區其餘部分： 區域，才可供上層半導體封裝件之銲球進行銲接以電 接至下層半導體封裝件，亦gp，使該基板上之電性連接區
第8頁 567601 五、發明說明（3) 域(Electrically-connecting area)大小為到 響到基板之電路佈局性，遂亦侷限往上> I ^ 輸入/輸出端（I/O Connection)之數量與佈# 裝裝置之設計靈活性（D e s i g n F 1 e X i h彳1 · w
υ 1 1 1t V 響。 J y又 因此，如何藉由簡單之製程技術、花 可提供半導體裝置高度積體化之發展，、二 決的課題。 、已成 【發明概述】 鑒於以上所述習知技術之缺點，太 个赞明之 提供一種具較佳之作業性及信賴性之具聂 之模組化裝置及其製法。 一登半 本發明之另一目的係提供一種得以 術、花費較少之成本即可達到模組化封^社丄 導體封裝件之模組化裝置及其製法。 、、、Ό 本發明之又一目的係提供一種呈 -y. ^ ：佳電路 伸佈局空間供多數之半導體封裝件進行 體封裝件之模組化裝置及其製法。 為達上揭及其它目的，本發明具堆最 模組化裝置，係包括一第一半導體封裝$，以 疊於該第一半導體封裝件上並與該第一 連接之第二半導體封裝件。 a 该第一半導體封裝件包含有一晶片承載件 置於該晶片承載件之半導體晶片；一提供該半 限制， 體封裝 ，致整 到不利 少之成 目前亟 而影 件之 體封 之影 本即 欲解 主要目 導體封 單之製 之具堆 佈局性 具堆疊 體封裝 及至少 封裝件 ;至少 導體晶 的係 裝件 程技 疊半 以延 半導 件之 —堆 電性 一安 片電
第9頁 567601 五、發明說明（4) 性連接至該晶片承載件之第一導電元件；一位於該半導體 晶片上方之電路板；一用以支撐並提供該電路板電性連接 至該晶片承載件之第二導電元件；一形成於該晶片承載件 與該電路板間’用以包覆該半導體晶片與該第二導電元 件，並外露出該電路板上表面之封裝膠體；以及一用以提 供該半導體晶片電性連接至外界之第三導電元件。 該第二半導體封裝件係藉由一導電元件電性連接至該 外露於第一半導體封裝件之電路板上表面，俾整合該第一 半導體封裝件，形成一具堆疊半導體封裝件之模組化裝 置。 本發明所提供之模組化裝置之製法係包括下列步驟： 製備一晶片承載件，並於其上安置有至少一藉由第一導電 元件與該晶片承載件電性連接之晶片；提供一電路板，具 有一上表面及一下表面，同時於該下表面上預設一第二導 電元件；將該電路板安置於該結合有半導體晶片之晶片承 載件上方，並藉由該第二導電元件電性連接至該晶片承載 件；填充一封裝膠體至該晶片承載件與該電路板間，用以 包覆該半導體晶片、第一導電元件與第二導電元件，並使 該電路板之上表面得以外露於該封裝膠體；設置一第三電 元件於該晶片承載件，以提供上述封裝之第一半導體封裝 件電性連接至外部裝置；以及將至少一第二半導體封裝件 電性連接至該第一半導體封裝件之電路板上表面。 由於該電路板係藉由第二導電元件結合於該第一半導 體封裝件中，其間並包覆有該封裝膠體，故在該第二半導
16930.ptd 第10頁 567601
五、發明說明（5) 得提供較佳 裝件之電路 件之接置， ί ty or 體封瓜件電性連接至該第一半導體封裝件時， 之作業性及信賴性，且該外露於第一半導體封 板’ f上表面整體均可提供該第二半導體封裝 故可提供較佳之電路佈局性（Trace Routab i 1
Layout)以供忠里壬 a , y A仏女置更多之電子元件。 【發明詳細說明】 請參閱第2e圖，為 組化裝置剖面示意圖。 如第2e圖所示，該 封裝件5 0，以及至少一 與該第一半導體封裝件 5 0 0 ° 本發明之具堆疊半導體封裝件之模 半導體裝置係包括有一第一半導_ 堆疊於該第一半導體封裝件5〇上^ 電性連接之第二半導體封裝件 該第 安置於該 晶片52電 位於該半 牛導體封裝件 電路板54上表面 晶片52電性連接 板5 4上表面外露 供至少一第二半 俾整合該第一半 半導體 承载件 之電路 晶片承 件51與 電元件 之封裝 至外界 出該第 導體封 導體封 晶片承載件5 1之 性連接至該晶片 導體晶片5 2上方 該電路板5 4電性連接至該 5 5，一形成於该晶片承載 該半導體晶片52、第—導 外露出該 該半導體 將該電路 面，以提 路板5 4， 一晶片承載件5 1 ;至少_ 晶片5 2 ; —提供該半導體 51之第一導電元件53 ; 一 板54; —用以支撐並提供 載件5 1之第二導電元件 該電路板54間，用以包覆 53與第二導電元件55，】 膠體5 6，以及一用以提供 之第三導電元件57。藉由 一半導體封裝件5 0之外表 裝件5 0 0電性連接至該冑 裝件5 0與第二半導體封裝 567601 五、發明說明（6) ^ — ' - 件5 0 0 ’ g形成一具堆疊半導體封裝件之模組化裝置。 。亥曰曰片承載件51為一球柵陣列型基板，其具有一第一 表面51 a和一第二表面51b，在該第一表面51&和第二表面 5 1 b均设置有複數個電性銲接點5丨c與導電跡線（未圖示）， 且在該基板中形成有複數個導電貫孔（Vias)51d，藉以提 供利用如銀膠之膠黏劑5丨e黏置於該晶片承載件5丨上之半 導體晶片52,得藉由該第一導電元件53，如金線，透過打 線作業電性連接至該晶片承载件5 i。 該電路板54具有一上表面54a及一下表面54b，在該上 表面54a和下表面54b上形成有多數個電性銲接點54c與導 電跡線（未圖示）之電性連接區，並在該電路板54中設置有 複數们‘電貝孔5 4 d ’同時於該下表面5 4 b上預設之電性銲 接點54c上銲結有第二導電元件55，如銲球、銲錫凸塊亦 j金屬導腳（P i η )等，使該電路板54安置於該結合有半導 體::片52之晶片承載件51上方時，得藉由回銲該第二導電 =55至該晶片承載片第—表面…上相對應之電性銲接 j 5=’，以使該電路板54與該晶片承載件51產生電性連 二^ Ϊ弟二導電元件55予以支樓該電路板54避免接 觸到该丰V體晶片52或該帛_導電元件53產生短路。 2 1裝膠體5曰6係藉由如環氧樹脂（Ερ〇χγ Res ιη)等封 4丰11#入至3玄曰曰片！、載件51與該電路板5 4間，用以包覆 I夺片導電元件55,並使該電路板54之 上表面54a得以外露於該封裝膠體56。 該第三導電元件57為—球柵陣列，係植置多數個銲球
567601 五、發明說明（7) , 於該晶片承載件5 1之第二表面5 1 b，以提供該半導體裝置 電性連接至如印刷電路板（未圖示）之外界裝置。如此，即 完成該包含有電路板5 4，並使該電路板5 4之上表面5 4 a得 以外露出該封裝膠體5 6之第一半導體封裝件5 0。 該第二半導體封裴件5 〇 〇，為一球柵陣列式半導體封 裳件’並預先完成封裝及相關測試後，俟確認功能正常， ，以表面藕接（Surface Mount Technology，SMT)方式將 该已完成封裝並經測試之第二半導體封裝件5 〇 〇利用該球 ^ ί列、5 〇1電性連接至該電路板上表面54a，藉以堆疊至少 一第,半導體封裝件5 0 0至該第一半導體封裝件50上。 化梦3 h圖至第2e圖係本發明具堆疊半導體封裝件之模組 置2 ΐ ί第一實施例之製造過程示意圖。本發明模組化裝 一曰^ f #係包括下列步驟。首先，如第2a圖所示，製備 至Ζ — ίΪΐ如一球栅陣列式（BGA)基板，並於其上安置 脂材質ϋ ί二承載件電性連接之晶u基板51得以樹 樹脂、、BTq 脂（Ep〇Xy Resin)、聚亞醯胺（Polyimide〕 成，1且右^Alaleimide Trazine)樹脂、FR4樹脂等製 表面5la和第二声一而表^51妨口一第二表面511)，以在該第一 導電跡線（夫^ 置有複數個電性銲接點5。與 5 1 d，藉以提二=)，且在該基板中形成有複數個導電貫孔 件51上之半仏利曰用如銀膠之膠黏劑51e黏置於該晶片承載 線，透過打線作ί : 52，得藉由該第一導電元件53，如金 該電S I業電性連接至該晶片承载件5卜 寸接點51〇:係以預先於該基板51之表面上形成
l693〇.ptd 第13頁 567601 五、發明說明（8) — 一導電層（未圖示），例如為一銅声 導電層之特定部分而形成者。s 再進行選擇性移除該 如弟2 b圖所示，與祖_ m 面5 4a及一下表面54b，在兮:上電路板5心其具有一上表 有多數個電性料點54^表面54f下表面⑽上形成 區，並在該電路板5钟^、置1電、=、線（未圖示）之電性連接 元件55，如銲球、p錫Λ换女干接點54C上銲結有第二導電 \ 吁錫凸塊亦或金屬導腳（Pin)等。 半導。片，將該電路板54安置於該結合有 :¥體曰曰片52之晶片承載件51上$，並藉由該第 5曰5¾性連接至該晶片承載片第一表面5 i让相對應之電 性】二點51c’以使該電路板54與該晶片承載件Η;生電 之後’如弟2d圖所示’進行一封裝膠體製程 (Encapsulation Process)，以習知環氧樹脂（Ep〇xy
Resin)等封裝材料填充至該晶片承載件51與該電路板 間，用以包覆該半導體晶片52與該第二導電元件55，並使 該電路板5 4之上表面5 4 a得以外露於該封裝膠, ^ 57,σ ^ ,a ,5ΐΛ^ 表面51b’以提供該半導體封裝件電性連接至外部印刷電 路板。如此’即完成該包含有電路板54，並使該電路板54 之上表面5 4 a得以外露出該封裝膠體5 6之第一半導體封裝 件5 0 〇 最後，如第2d圖所示，以表面藕接（Surface M〇unt
16930.ptd
567601 五、發明說明（9) "-- τ 體 表 echn〇1〇gy， SMT)方式將已完成封裝並餘 :封裝件5 0 0利用該一球柵陣垃°，弟一半導 半導體封裝件50上。 弟—+ *體封裝件5 0 0至該第一 該第導ΐ封裝件之模組化裝置中，由於 55結合於二f反54係藉由該第二導電元件 體56，故在該第二丰^髀^ 50’其間並包覆有該封裝膠 ^ r α ^ 一丰v體封衷件5 0 0電性連接至該第一半 π 封：r:r之作業性及信賴… 54a均可作為ζ體封衣表面之電路板54, I整個上表面 佳之電路你Α二弟一半^封裝件5〇0之接置，藉以提供較 時，兮第 f 性（Trace Routability 打 Layout);同 板型二半導體封裝件50及第二半導體封裝件5 0 0之基 本，即；、金ί傳統之基，不須額外花費複雜之製程與成 ^ 了達到堆疊半導體封裝件之目的。 化裝^ Ϊ Ξ第3圖’係本發明具堆疊半導體封裝件之模組 實施例之實施例剖面示意圖。如圖所*，本發明第二 不同卢+果、、且化裝置與第一實施例所揭示者大致相同，其 該第:於该第一半導體封裝件6 0之半導體晶片6 2係藉由 方式雷t電兀件63，如銲錫凸塊，利用覆晶（Flip Chip) 电性連接至該晶片承載件6 1。 十隹 P) % 點及 所述之具體實施例，僅係用以例釋本發明之特 本發^ t，而非用以限定本發明之可實施範疇，在未脫離 揭之精神與技術範疇下，任何運用本發明所揭示
567601 五、發明說明（ίο) 内容而完成之等效改變及修飾，均仍應為下述之申請專利 範圍所涵蓋。 16930.ptd 第16頁 111 567601 圖式簡單說明 【圖式簡單說明】 第1 a圖係習知整合有複數個晶片之半導體封裝件剖面 不意圖， 第1 b圖係習知整合有複數個晶片之半導體封裝件剖面 不意圖， 第1 c圖係習知之美國專利第6，3 0 3，9 9 7號半導體裝置 之剖面示意圖； 第Id圖係習知之美國專利第5, 78 3, 8 7 0號半導體裝置 之剖面示意圖； 第2 a至2 e圖係本發明之具堆疊半導體封裝件之模組化 裝置製程示意圖；以及 第3圖係本發明之具堆疊半導體封裝件之模組化裝置 第二實施例剖面示意圖。 【元件符號說明】 10 基 板 11 半 導 體 晶 片 20 基 板 21 半 導 體 晶 片 3 半 導 體 裝 置 30 基 板 31 半 導 體 晶 片 32 半 導 體 封 裝 件 311 銲 線 321 銲 球 4 半 導 體 裝 置 40a 第 一 半 導 體 封 裝 件 40b 第 二 半 導 體 封 裝 件 40c 第 二 半 導 體 封 裝 件 41a 基 板 411b 銲 球 50 第 一 半 導 體 封 裝 件， 500 第 二 半 導 體 封 裝 件 51 基 板 51a 基 板 第 一 表 面
16930.ptd 第17頁 567601 圖式簡單說明 51b 基 板 第 二 表 面 51c 電 性 銲 接 點 51d 貫 孔 51e 膠 黏 層 52 半 導 體 晶 片 53 第 一 導 電 元 件 54 電 路 板 54a 上 表 面 54b 下 表 面 54c 電 性 銲 接 點 54d 貫 孔 55 第 二 導 電 元 件 56 封 裝 膠 體 57 第 二 導 電 元 件 60 第 一 導 電 元 件 61 基 板 62 半 導 體 晶 片 63 第 一 導 電 元 件
16930. pi cl 第18頁

Claims (1)

  1. 567601 六、申請專利範圍 1. 一種具堆疊半導體封裝件之模組化裝置，係包括： 一第一半導體封裝件；以及 至少一第二半導體封裝件，係堆疊並電性連接至 該第一半導體封裝件上；其中 該第一半導體封裝件包含： 一晶片承載件； 至少一安置於該晶片承載件之半導體晶片； 一提供該半導體晶片電性連接至該晶片承載件之 第一導電元件； 一位於該半導體晶片上方並具有一上表面及一下 表面之電路板； 一設置於該電路板下表面，用以支撐並提供該電 路板電性連接至該晶片承載件之第二導電元件； 一形成於該晶片承載件與該電路板間，以包覆住 該半導體晶片、第一及第二導電元件，並外露出該電 路板上表面以供至少一第二半導體封裝件作電性連接 之封裝膠體；以及 一用以提供該半導體晶片電性連接至外界之第三 導電元件。 2. 如申請專利範圍第1項之具堆疊半導體封裝件之模組化 裝置，其中該第一導電元件為銲線及銲錫凸塊之任一 者。 3. 如申請專利範圍第1項之具堆疊半導體封裝件之模組化 裝置，其中該第二導電元件為銲球、銲錫凸塊及金屬
    16930.ptd 第19頁 六、申請專利範圍 4.::。)之任—者。 明專利範圍第 骏置’其中該第 雷/、堆疊半導體封裝件之模組化 5·如申請專利範圍第件為鮮球。 裳置，其中該第二半^堆疊半導體封褒件之模組化 導體封裝件。 -十裝件為球柵陣列式（BGA)半 如申請專利範圍第丨 w 裝置，J:中1電& 4、，、堆璺半導體封裝件之模組化 7.如申：奎I:板為-雙層電路板。 跋置==第6項之具堆疊半導體封裝件之模組化 性r垃u ;路板上表面和下表面形成有多數個電 以點與導電跡線，並在該電路板中設置有複數個 导電貫孔。 種具堆疊半導體封裝件之模組化裝置製法，係包括： (1 )製備一晶片承載件，並於其上安置至少一藉由 導電元件與該晶片承載件電性連接之晶片； (2)提供一電路板，具有一上表面及一下表面，並 於該下表面預設有一第二導電元件； (3 )將該電路板安置於該結合有半導體晶片之晶片 承載件上方，並藉由該第二導電元件電性連接至該晶 片承载件； (4 )填充一封裝膠體至該晶片承載件與該電路板間 ，用以包覆該半導體晶片、第一導電元件與該第二導 電元件，並使該電路板之上表面得以外露於該封裝膠 體；
    16930.ptd 第20頁 六 10. 11. 12. 13. '申請專利範圍 (5)设置一第二 上述完成封裝之m 兀件於該晶片承载件，以楛# 置，·以及 弟—半導體封裝件電性連接至外=供 (6 )將至少一第一 半導體封裝件之電路導體封裝件電性連接至該第一 如申請專利範圍第8項板夕上目表面。 裝置製法，其中於+、之具堆疊半導體封裝件之模&彳卜 及銲錫凸塊之任一者。 以苐一導電元件為銲線 b申請專利範園笛Q s 裝置製法，其中於二之 工= = 件… 裝置製法，盆由 、之具堆疊半導體封裝件之Μέ π 長置I法，纟中於步 J件之摈組化 。 T忒第一導電元件為銲球 b申請專利範圍第8項 裝置製法…於步驟（6)中U體；；件之模組化 求栅陣列式（BGA)半導體封褒件^第一 +導體封裝件為 κη;第8項之具堆疊半導體封裝件之… :置於步驟(2)中，該電路板 如申請專利範圍帛"項之具堆最丰導 化裝置製法，其中於步驟隹“導體封敦件之模組 =面=有多數個電性鲜接點與導電板上表面和下 路板中設置有複數個導電貫孔。 、、友，並在該電 14.
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