TW541585B - Chip-stacked semiconductor device - Google Patents

Chip-stacked semiconductor device Download PDF

Info

Publication number
TW541585B
TW541585B TW091110913A TW91110913A TW541585B TW 541585 B TW541585 B TW 541585B TW 091110913 A TW091110913 A TW 091110913A TW 91110913 A TW91110913 A TW 91110913A TW 541585 B TW541585 B TW 541585B
Authority
TW
Taiwan
Prior art keywords
wafer
connection
terminals
substrates
wiring
Prior art date
Application number
TW091110913A
Other languages
English (en)
Chinese (zh)
Inventor
Katsuhiko Oyama
Mitsuyoshi Endo
Chiaki Takubo
Takashi Yamazaki
Takashi Imoto
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW541585B publication Critical patent/TW541585B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW091110913A 2001-06-01 2002-05-23 Chip-stacked semiconductor device TW541585B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001167185A JP4109839B2 (ja) 2001-06-01 2001-06-01 半導体装置

Publications (1)

Publication Number Publication Date
TW541585B true TW541585B (en) 2003-07-11

Family

ID=19009610

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091110913A TW541585B (en) 2001-06-01 2002-05-23 Chip-stacked semiconductor device

Country Status (5)

Country Link
US (1) US6861738B2 (https=)
JP (1) JP4109839B2 (https=)
KR (1) KR100512835B1 (https=)
CN (1) CN100524744C (https=)
TW (1) TW541585B (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
JP4799157B2 (ja) 2005-12-06 2011-10-26 エルピーダメモリ株式会社 積層型半導体装置
CN100547784C (zh) * 2005-12-16 2009-10-07 晨星半导体股份有限公司 多芯片封装结构的内连线
JP2009026884A (ja) 2007-07-18 2009-02-05 Elpida Memory Inc 回路モジュール及び電気部品
TWI721960B (zh) * 2014-12-18 2021-03-21 日商新力股份有限公司 半導體裝置、製造方法及電子機器
US11824009B2 (en) * 2018-12-10 2023-11-21 Preferred Networks, Inc. Semiconductor device and data transferring method for semiconductor device
WO2023119450A1 (ja) * 2021-12-21 2023-06-29 ウルトラメモリ株式会社 半導体モジュール及び積層モジュール

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04284661A (ja) * 1991-03-13 1992-10-09 Toshiba Corp 半導体装置
KR100204753B1 (ko) * 1996-03-08 1999-06-15 윤종용 엘오씨 유형의 적층 칩 패키지
JPH10107205A (ja) * 1996-09-27 1998-04-24 Hitachi Ltd 積層半導体モジュール
SE511425C2 (sv) * 1996-12-19 1999-09-27 Ericsson Telefon Ab L M Packningsanordning för integrerade kretsar
JP2870530B1 (ja) * 1997-10-30 1999-03-17 日本電気株式会社 スタックモジュール用インターポーザとスタックモジュール
JP3519924B2 (ja) * 1997-11-21 2004-04-19 ローム株式会社 半導体装置の構造及びその製造方法
KR100271639B1 (ko) * 1997-12-23 2000-11-15 김영환 적층형 반도체패키지 및 그 제조방법 및 그 적층방법
DE19801312A1 (de) 1998-01-15 1999-07-22 Siemens Ag Halbleiterbauelement mit mehreren Substratlagen und zumindest einem Halbleiterchip und einem Verfahren zum Herstellen eines solchen Halbleiterbauelementes
JP3186700B2 (ja) * 1998-06-24 2001-07-11 日本電気株式会社 半導体装置及びその製造方法
KR20000011420U (ko) * 1998-12-02 2000-07-05 김영환 적층형 반도체 패키지

Also Published As

Publication number Publication date
KR100512835B1 (ko) 2005-09-07
JP4109839B2 (ja) 2008-07-02
CN1399338A (zh) 2003-02-26
JP2002368185A (ja) 2002-12-20
CN100524744C (zh) 2009-08-05
KR20020092193A (ko) 2002-12-11
US20020180030A1 (en) 2002-12-05
US6861738B2 (en) 2005-03-01

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Legal Events

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees